2334results about "Logic circuits characterised by logic function" patented technology

The invention discloses a power-on reset circuit, and relates to the technical field of integrated circuits, in order to eliminate static power consumption of the power-on reset circuit and reduce power consumption of the power-on reset circuit, the power-on reset circuit comprises a discharge delay circuit, a current mirror circuit and a buffer circuit; the discharge delay circuit comprises a capacitor and an NMOS (N-channel Metal Oxide Semiconductor) tube M4, and the NMOS tube M4 is used for discharging the capacitor; the current mirror image circuit comprises an NMOS tube M2, an NMOS tube M3 and a PMOS tube M9. The grid electrode of the NMOS tube M2 and the grid electrode of the PMOS tube M9 are respectively connected with the output end of the buffer circuit; the grid electrode of the NMOS tube M3 is respectively connected with the source electrode of the PMOS tube M9, the drain electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M4; the current mirror image circuit is used for turning off the NMOS tube M2 after the reset signal is ended, and pulling up the drain electrode voltage of the NMOS tube M3 to the power supply voltage through the PMOS tube M9, so that the NMOS tube M3 enters a deep linear region, and a direct current path from the power supply to the ground in the current mirror image circuit is cut off; and the buffer circuit is used for outputting a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

The invention discloses a photoelectric logic gate, which relates to the technical field of photoelectric logic gates, and is characterized in that a Bi2Se3 film is arranged on a substrate, two metal electrodes are arranged on the Bi2Se3 film at intervals, the two metal electrodes are connected with current testing equipment, and a channel is formed between the two metal electrodes and the current testing equipment; the two metal electrodes are connected, current flowing through the two metal electrodes serves as output, optical signals with different illumination intensities smaller than 468nm irradiate a Bi2Se3 thin film of a channel part to form an OR logic gate or AND logic gate through modulation, and irradiation under different combination conditions of two groups of optical signals larger than 468nm serves as signal input; for an NOT logic gate or an NOR logic gate or an NAND logic gate, optical signals with different illumination intensities larger than 468nm can be modulated, and irradiation under different combination conditions of two groups of optical signals smaller than 468nm is used as signal input. The structure is simple, and integration of the multifunctional logic gate is realized.

Glitch detection is provided for a clock signal in a semiconductor integrated circuit (IC), for example between an input buffer and a Phase Locked Loop (PLL). A first pulse signal is generated in response to a rising edge of the clock signal, and a second pulse signal is generated in response to its falling edge. A third pulse signal is generated at a predetermined period of time after a start of the first pulse signal, and a fourth pulse signal is generated at a predetermined period of time after a start of the second pulse signal. A glitch in the clock signal is indicated based on the third pulse signal having an opposite logical level to the clock signal, and / or based on the fourth pulse signal having the same logical level as the clock signal.

A structure includes a level shifter, first and second variable voltage generators, and a programmable voltage generator. The level shifter includes low and high supply voltage nodes and two parallel branches, including multiple transistors, connected between the nodes. The programmable voltage generator generates and applies a high supply voltage (VH) to the high supply voltage node. VH is programmable to one of multiple possible VH levels. Based on the voltage level of VH, the first variable voltage generator generates and applies a low supply voltage (VL) to the low supply voltage node and the second variable voltage generator generates and applies a gate bias voltage (VGB) to gates of some transistors. By tracking VH and adjusting VL and VGB based on thereon, the voltage level shifter operates within the SOA at high VHs, remains operable at low VHs, and maintains operating speed at mid-level VHs.

The invention discloses an anti-single event upset latch circuit structure with fewer sensitive nodes. The anti-single event upset latch circuit structure comprises a clock filter circuit, a delay filter circuit, a latch circuit and a stacked inverter circuit. The clock filter circuit is used for filtering single-particle transient pulses at a clock end and providing clock signals for the latch circuit. The delay filter circuit is used for filtering single-particle transient pulses of a data end and providing input signals for the latch circuit. And the latch circuit is used for realizing data transmission and latch, and maintaining a correct signal output state and level correction after single-particle radiation in a latch state. The stacked inverter circuit is used for providing an inversion signal. The designed latch circuit can realize single-particle transient reinforcement and single-particle transient pulse filtering, has few circuit sensitive nodes, is good in reinforcement effect, and is simple and easy to realize.

The utility model relates to a phase interpolator circuit, a clock recovery circuit and a chip, and the phase interpolator circuit mainly comprises a first clock filter which is used for filtering a high-frequency harmonic wave of a first clock signal to generate a first filtering signal; the second clock filter is used for filtering the high-frequency harmonic wave of the second clock signal to generate a second filtering signal; the phase mixer is coupled to the first clock filter and the second clock filter and is used for generating a phase mixed signal according to the first filtering signal and the second filtering signal; and the alternating current coupling output circuit is used for receiving the phase mixed signal and generating an interpolation clock signal according to the phase mixed signal. The phase interpolator circuit can support phase interpolation operation in a wide frequency range, the output linearity performance is optimized, the sensitivity of INL and DNL to power supply amplitude changes is weakened, the duty ratio of the output interpolation clock signal can be optimized, and the interpolation clock signal can support a high-speed interface half-rate transmission mode.

An ultra-low power consumption and high speed level shift circuit and method based on subthreshold conduction comprises an input shift circuit and a low power consumption output buffer, the input shift circuit comprises a pull-up network, a pull-down network and a feedback transistor, the pull-up network is of a current mirror structure, the pull-down network is composed of a first pull-down tube and a second pull-down tube, and the feedback transistor is connected with the first pull-down tube and the second pull-down tube. A feedback transistor is added, and when input signal high level conduction succeeds, the current mirror structure is switched off; and the second pull-down tube uses a common-gate transistor, and pulls down the output end of the input shift circuit to a low level by using the sub-threshold conduction principle of the common-gate transistor when the input signal is at a low level. According to the invention, the conversion speed of the falling edge signal in the circuit is effectively improved, the time delay is reduced, the static power consumption is ultralow, the wide voltage conversion range is provided, and meanwhile, the area is very small.

A PUF circuit based on the threshold loss of MOSFETs comprises N stages of delay units and an arbiter. Each stage of delay unit comprises six inverters and four MOS transistors, wherein the four MOS transistors are all PMOS transistors or NMOS transistors. Each path in each stage of delay unit uses only one PMOS or NMOS transistor and does not use a transmission gate formed by a PMOS transistor and an NMOS transistor. Therefore, it reduces hardware cost. Each MOS transistor on the transmission path has a threshold loss, PMOS and NMOS transistors in a third inverter and a sixth inverter are in an on-state, and output terminals of the third inverter and the sixth inverter will be charged to a high level or discharged to a low level, thus greatly increasing a delay difference between two square signals and enhancing randomness.

A transimpedance amplifier device for an optical receiver disclosed by the present invention comprises a bias circuit, a transimpedance amplifier and an amplification driving circuit which are connected in sequence, the bias circuit comprises an upper bias structure and a lower bias structure, and the upper bias structure and the lower bias structure are both connected with the transimpedance amplifier to generate different bias currents. It is ensured that the photodiode PD1 can be conducted and generate light current when light passes through the photodiode PD1, the transimpedance amplifier is used for converting the current into voltage to be output, and the amplification driving circuit is used for amplifying the voltage. According to the optical receiver circuit, micro current generated by the photodiode can be converted into output voltage in a relatively high output range through the transimpedance amplifier, and compared with a traditional optical receiver circuit, the optical receiver circuit is relatively low in cost in circuit structure and has the advantages of low power consumption and high reliability. The driving capability of the circuit can be improved under the condition that a complex amplifier loop and a photoelectric conversion module are not needed, the output voltage in a high range is output, and the performance and the stability are further enhanced.

A structure includes a level shifter, first and second variable voltage generators, and a programmable voltage generator. The level shifter includes low and high supply voltage nodes and two parallel branches, including multiple transistors, connected between the nodes. The programmable voltage generator generates and applies a high supply voltage (VH) to the high supply voltage node. VH is programmable to one of multiple possible VH levels. Based on the voltage level of VH, the first variable voltage generator generates and applies a low supply voltage (VL) to the low supply voltage node and the second variable voltage generator generates and applies a gate bias voltage (VGB) to gates of some transistors. By tracking VH and adjusting VL and VGB based on thereon, the voltage level shifter operates within the SOA at high VHs, remains operable at low VHs, and maintains operating speed at mid-level VHs.

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

The present disclosure relates to a universal logic memory cell composed of triple-gate silicon devices. The universal logic memory cell according to one embodiment of the present disclosure may perform a ternary logic operation function and a memory function using triple-gate silicon devices driven by a positive feedback loop.

A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.

A PCIe clock detection circuit includes a clock detector, a clock receiver, a counter coupled to the clock receiver, a multiplexer coupled to the counter, and an AND gate coupled to the clock detector and the multiplexer. The clock detector is used to detect amplitude of a clock signal and generate a clock detection signal accordingly. The clock receiver is used to generate a reference clock signal according to the clock signal. The counter is used to generate a counter signal according to the reference clock signal. The multiplexer is used to generate a MUX output signal according to the counter signal and a reference signal. The AND gate is used to generate a clock detection output signal according to the clock detection signal and the MUX output signal.

A level shifter includes: a low voltage domain configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal; and a high voltage domain comprising a latch and a current mirror circuit configured to mirror the non-overlapping first and second current pulses such that the latch is set when the first current pulse is active and reset when the second current pulse is active. The current mirror circuit includes a first mirroring path for the first current pulse and a second mirroring path for the second current pulse. The level shifter has a common mode slew current that is added to the non-overlapping first and second current pulses. The first mirroring path and the second mirroring path are cross-coupled such that the common mode slew current is reduced or cancelled before the non-overlapping first and second current pulses are input to the latch.

The present invention provides a common-mode transient suppression protection circuit for a digital isolator, including a modulation circuit, a demodulation circuit and an isolation capacitor connected between the modulation circuit and the demodulation circuit. The modulation circuit includes a modulation circuit front-end and a drive circuit, which are connected in sequence, and a clamping module is arranged in the drive circuit. The protection circuit further includes a linear voltage regulator structure connected with the drive circuit, and a power supply clamp is arranged in the linear voltage regulator structure. By providing the linear voltage regulator structure having the power supply clamp and the drive circuit having the clamping module in the protection circuit, low-voltage devices in the drive circuit can be protected from being damaged by high-voltage signals generated by common-mode transient interference.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

An apparatus and configuring scheme where a capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and / or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

Systems and devices for signal arbitration are described. A first asynchronous circuit can receive and sanitize a first non-persistent signal representing a first request to generate a first persistent signal. A second asynchronous circuit can receive and sanitize a second non-persistent signal representing a second request to generate a second persistent signal. A mutual exclusive circuit can arbitrate between the first persistent signal and the second persistent signal and output a grant signal to issue a grant. A control circuit can control an operation mode of the first and second asynchronous circuits based on a control signal, a first grant signal indicating a grant status of the first request, a second grant signal indicating a grant status of the second request, the first persistent signal and the second persistent signal.

The invention belongs to the field of analog integrated circuit design and integrated systems, and particularly relates to a programmable dead time control circuit for a high-voltage half-bridge driver. Comprising a dead zone time selection circuit (100), a multi-selection mode circuit module and a dead zone logic control circuit (105) which are connected in sequence, and the multi-selection mode circuit module comprises an overlapped input mode circuit (101), an equal ratio input mode circuit (102), a fixed mode input circuit (103) and a dead zone forbidden mode circuit (104) which are connected in parallel. According to the invention, the control of four kinds of dead time can be completed on one driving circuit, so that the circuit can freely control the magnitude of the output dead time without other external structures.

The utility model discloses a storage and calculation integrated majority voting logic gate circuit based on ferroelectric field effect transistors. The storage and calculation integrated majority voting logic gate circuit comprises an input module, an operation module, a discharge module and an output module, the input module receives three voltage signals and transmits the three voltage signals to the operation module according to a time sequence; the operation module comprises a ferroelectric field effect transistor, formation and damage of a conducting channel of the ferroelectric field effect transistor are directionally changed according to voltage signals received by a grid electrode and a source electrode, a nonvolatile operation relation with an external voltage signal as input and on-off of an internal channel as output is established, a logic input variable form is unified, and majority voting logic operation is executed. The discharging module adjusts a voltage signal of the operation module in a reading stage to prevent misreading; the output module accurately reads a nonvolatile operation result as a voltage signal; the circuit has the advantages that the storable majority voting logic function can be realized with a small number of transistors, the logic input variable form is unified, and the operation cascading capability and the circuit expandability are improved.

An apparatus includes a transmitter, a voltage regulator, an isolator, and a test controller. The transmitter has an input, an output, and a first supply voltage terminal. The input couples to the apparatus' input terminal. The voltage regulator's input couples to a second supply voltage terminal. The voltage regulator's output couples to the first supply terminal. The first terminal of the isolator couples to the output of the transmitter. A first test controller terminal couples to the second supply voltage terminal. A second test controller terminal couples to the input terminal of the apparatus. The first control output couples to the control input of the voltage regulator. The test controller changes a logic state of a control signal at the first control output from a first logic state to a second logic state.

A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

The invention discloses a high-speed serial signal linear equalization circuit which comprises an input terminal, a continuous time linear equalizer (CTLE), a super source follower, a variable gain amplifier (VGA) and an adaptive feedback. The input end is connected with a 100-ohm internal resistance differential signal source of the transmitting end through a channel; the equalization circuit CTLE is connected to the output end of the input end connection module, two groups of resistance switches (RsMF and RsHF) of the CTLE module are respectively controlled by 4-bit binary codes to enable source degeneration resistors Rs of two stages of CTLEs to be variable, two groups of capacitance switches (CsMF and CsHF) are respectively controlled by 2-bit binary codes to enable source degeneration capacitors Cs of the two stages of CTLEs to be variable, and the two groups of capacitance switches (CsMF and CsHF) are respectively controlled by 2-bit binary codes to enable source degeneration capacitors Cs of the two stages of CTLEs to be variable. The change of a zero pole of the circuit is realized through the change of the source degeneration resistor Rs and the source degeneration capacitor Cs, and the adjustability of the difference between the high-frequency gain and the low-frequency gain of the circuit is realized, so that the multi-gear adjustability of the equalization capability is realized.

The invention provides a voltage-controlled oscillator and a phase-locked loop circuit, and relates to the technical field of integrated circuits. The voltage-controlled oscillator comprises a voltage-controlled circuit, a current copying circuit and an oscillating circuit, the voltage control circuit comprises a comparison unit, a switch unit and a voltage acquisition unit. A first input end of the comparison unit is used for receiving input control voltage, a second input end of the comparison unit is grounded through the voltage acquisition unit, an output end of the comparison unit is connected with a control end of the switch unit, one end of the switch unit is grounded through the voltage acquisition unit, and the other end of the switch unit is connected with an input end of the current copying circuit; the output end of the current copying circuit is connected with the input end of the oscillation circuit, and the output end of the oscillation circuit is used for outputting a control signal with target oscillation frequency. According to the voltage-controlled oscillator, the linearity of voltage control current is optimized, and meanwhile, the working voltage range of the voltage-controlled oscillator is expanded.

The invention discloses a single-cluster XNOR logic gate and a signal reading method thereof. One end of a single cluster device is provided with a source electrode and a drain electrode, and the other end of the single cluster device is provided with a gate electrode. A single-cluster XNOR logic gate is placed in a resonance tunneling area for signal reading, and when the input potential difference between a source electrode and a drain electrode of a single-cluster device is 0, the gate electrode outputs a high level; and when the input potential difference between the source electrode and the drain electrode of the single cluster device is not 0, the gate electrode outputs a low level.

A system includes: an inverter, wherein the inverter includes: a power module including: a flex layer including a gate trace, a first substrate, a second substrate including a source plane and a gate plane separated from the source plane by a full trench, the source plane including a step trench, and the gate plane including an electrical connection through the gate trace of the flex layer to a gate input connection of the power module, a semiconductor die disposed between the first substrate and the second substrate, the step trench formed in a portion of the source plane corresponding to at an edge of the semiconductor die, and the semiconductor die including a gate connected to the gate plane, and a sinter element disposed between the semiconductor die and the second substrate to connect the semiconductor die to the second substrate; a battery; and a motor.

The invention discloses a digital-to-analog converter chip which comprises an analog power supply for supplying power to an analog power supply domain, a digital power supply for supplying power to a digital power supply domain and a clock power supply for supplying power to a clock power supply domain, the digital power supply domain comprises a first linear voltage regulator, and the clock power supply domain comprises a second linear voltage regulator. Power supply output ends of the analog power supply, the digital power supply and the clock power supply are respectively connected with a power supply detection circuit; the power supply detection circuit is used for outputting a power supply establishment signal; the digital power domain comprises a second AND gate unit, and the clock power domain comprises a third AND gate unit; wherein the second AND gate unit is used for enabling the first linear voltage regulator to start; and the third AND gate unit is used for enabling the second linear voltage regulator to start. The problem that in the prior art, the LDO of the digital power domain and the LDO of the clock power domain are likely to be different in voltage building time in the power-on starting process, and consequently overvoltage of a low-voltage device is caused is solved, and the reliability of a digital-to-analog converter chip is improved.

Techniques facilitating error mitigation for quantum computing devices. In one example, a system can comprise a process that executes computer executable components stored in memory. The computer executable components comprise: an approximation component; a budget component; and an optimization component. The approximation component can generate an approximate decomposition of a quantum gate. The budget component can set a budget value (Cbudget) for a C-factor that is a metric for increase in variance of quasi-probability sampling. The optimization component can determine an optimal decomposition for the quantum gate as a function of Cbudget.