1660results about "Logic circuits characterised by logic function" patented technology

The invention discloses a power-on reset circuit, and relates to the technical field of integrated circuits, in order to eliminate static power consumption of the power-on reset circuit and reduce power consumption of the power-on reset circuit, the power-on reset circuit comprises a discharge delay circuit, a current mirror circuit and a buffer circuit; the discharge delay circuit comprises a capacitor and an NMOS (N-channel Metal Oxide Semiconductor) tube M4, and the NMOS tube M4 is used for discharging the capacitor; the current mirror image circuit comprises an NMOS tube M2, an NMOS tube M3 and a PMOS tube M9. The grid electrode of the NMOS tube M2 and the grid electrode of the PMOS tube M9 are respectively connected with the output end of the buffer circuit; the grid electrode of the NMOS tube M3 is respectively connected with the source electrode of the PMOS tube M9, the drain electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M4; the current mirror image circuit is used for turning off the NMOS tube M2 after the reset signal is ended, and pulling up the drain electrode voltage of the NMOS tube M3 to the power supply voltage through the PMOS tube M9, so that the NMOS tube M3 enters a deep linear region, and a direct current path from the power supply to the ground in the current mirror image circuit is cut off; and the buffer circuit is used for outputting a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

A transimpedance amplifier device for an optical receiver disclosed by the present invention comprises a bias circuit, a transimpedance amplifier and an amplification driving circuit which are connected in sequence, the bias circuit comprises an upper bias structure and a lower bias structure, and the upper bias structure and the lower bias structure are both connected with the transimpedance amplifier to generate different bias currents. It is ensured that the photodiode PD1 can be conducted and generate light current when light passes through the photodiode PD1, the transimpedance amplifier is used for converting the current into voltage to be output, and the amplification driving circuit is used for amplifying the voltage. According to the optical receiver circuit, micro current generated by the photodiode can be converted into output voltage in a relatively high output range through the transimpedance amplifier, and compared with a traditional optical receiver circuit, the optical receiver circuit is relatively low in cost in circuit structure and has the advantages of low power consumption and high reliability. The driving capability of the circuit can be improved under the condition that a complex amplifier loop and a photoelectric conversion module are not needed, the output voltage in a high range is output, and the performance and the stability are further enhanced.

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

The present disclosure relates to a universal logic memory cell composed of triple-gate silicon devices. The universal logic memory cell according to one embodiment of the present disclosure may perform a ternary logic operation function and a memory function using triple-gate silicon devices driven by a positive feedback loop.

A level shifter includes: a low voltage domain configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal; and a high voltage domain comprising a latch and a current mirror circuit configured to mirror the non-overlapping first and second current pulses such that the latch is set when the first current pulse is active and reset when the second current pulse is active. The current mirror circuit includes a first mirroring path for the first current pulse and a second mirroring path for the second current pulse. The level shifter has a common mode slew current that is added to the non-overlapping first and second current pulses. The first mirroring path and the second mirroring path are cross-coupled such that the common mode slew current is reduced or cancelled before the non-overlapping first and second current pulses are input to the latch.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

An apparatus and configuring scheme where a capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and / or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

An apparatus includes a transmitter, a voltage regulator, an isolator, and a test controller. The transmitter has an input, an output, and a first supply voltage terminal. The input couples to the apparatus' input terminal. The voltage regulator's input couples to a second supply voltage terminal. The voltage regulator's output couples to the first supply terminal. The first terminal of the isolator couples to the output of the transmitter. A first test controller terminal couples to the second supply voltage terminal. A second test controller terminal couples to the input terminal of the apparatus. The first control output couples to the control input of the voltage regulator. The test controller changes a logic state of a control signal at the first control output from a first logic state to a second logic state.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

The invention discloses a high-speed serial signal linear equalization circuit which comprises an input terminal, a continuous time linear equalizer (CTLE), a super source follower, a variable gain amplifier (VGA) and an adaptive feedback. The input end is connected with a 100-ohm internal resistance differential signal source of the transmitting end through a channel; the equalization circuit CTLE is connected to the output end of the input end connection module, two groups of resistance switches (RsMF and RsHF) of the CTLE module are respectively controlled by 4-bit binary codes to enable source degeneration resistors Rs of two stages of CTLEs to be variable, two groups of capacitance switches (CsMF and CsHF) are respectively controlled by 2-bit binary codes to enable source degeneration capacitors Cs of the two stages of CTLEs to be variable, and the two groups of capacitance switches (CsMF and CsHF) are respectively controlled by 2-bit binary codes to enable source degeneration capacitors Cs of the two stages of CTLEs to be variable. The change of a zero pole of the circuit is realized through the change of the source degeneration resistor Rs and the source degeneration capacitor Cs, and the adjustability of the difference between the high-frequency gain and the low-frequency gain of the circuit is realized, so that the multi-gear adjustability of the equalization capability is realized.

The invention provides a voltage-controlled oscillator and a phase-locked loop circuit, and relates to the technical field of integrated circuits. The voltage-controlled oscillator comprises a voltage-controlled circuit, a current copying circuit and an oscillating circuit, the voltage control circuit comprises a comparison unit, a switch unit and a voltage acquisition unit. A first input end of the comparison unit is used for receiving input control voltage, a second input end of the comparison unit is grounded through the voltage acquisition unit, an output end of the comparison unit is connected with a control end of the switch unit, one end of the switch unit is grounded through the voltage acquisition unit, and the other end of the switch unit is connected with an input end of the current copying circuit; the output end of the current copying circuit is connected with the input end of the oscillation circuit, and the output end of the oscillation circuit is used for outputting a control signal with target oscillation frequency. According to the voltage-controlled oscillator, the linearity of voltage control current is optimized, and meanwhile, the working voltage range of the voltage-controlled oscillator is expanded.

The invention discloses a single-cluster XNOR logic gate and a signal reading method thereof. One end of a single cluster device is provided with a source electrode and a drain electrode, and the other end of the single cluster device is provided with a gate electrode. A single-cluster XNOR logic gate is placed in a resonance tunneling area for signal reading, and when the input potential difference between a source electrode and a drain electrode of a single-cluster device is 0, the gate electrode outputs a high level; and when the input potential difference between the source electrode and the drain electrode of the single cluster device is not 0, the gate electrode outputs a low level.

A system includes: an inverter, wherein the inverter includes: a power module including: a flex layer including a gate trace, a first substrate, a second substrate including a source plane and a gate plane separated from the source plane by a full trench, the source plane including a step trench, and the gate plane including an electrical connection through the gate trace of the flex layer to a gate input connection of the power module, a semiconductor die disposed between the first substrate and the second substrate, the step trench formed in a portion of the source plane corresponding to at an edge of the semiconductor die, and the semiconductor die including a gate connected to the gate plane, and a sinter element disposed between the semiconductor die and the second substrate to connect the semiconductor die to the second substrate; a battery; and a motor.

The invention discloses a digital-to-analog converter chip which comprises an analog power supply for supplying power to an analog power supply domain, a digital power supply for supplying power to a digital power supply domain and a clock power supply for supplying power to a clock power supply domain, the digital power supply domain comprises a first linear voltage regulator, and the clock power supply domain comprises a second linear voltage regulator. Power supply output ends of the analog power supply, the digital power supply and the clock power supply are respectively connected with a power supply detection circuit; the power supply detection circuit is used for outputting a power supply establishment signal; the digital power domain comprises a second AND gate unit, and the clock power domain comprises a third AND gate unit; wherein the second AND gate unit is used for enabling the first linear voltage regulator to start; and the third AND gate unit is used for enabling the second linear voltage regulator to start. The problem that in the prior art, the LDO of the digital power domain and the LDO of the clock power domain are likely to be different in voltage building time in the power-on starting process, and consequently overvoltage of a low-voltage device is caused is solved, and the reliability of a digital-to-analog converter chip is improved.

Techniques facilitating error mitigation for quantum computing devices. In one example, a system can comprise a process that executes computer executable components stored in memory. The computer executable components comprise: an approximation component; a budget component; and an optimization component. The approximation component can generate an approximate decomposition of a quantum gate. The budget component can set a budget value (Cbudget) for a C-factor that is a metric for increase in variance of quasi-probability sampling. The optimization component can determine an optimal decomposition for the quantum gate as a function of Cbudget.

The invention designs and provides a plurality of all-digital in-memory computing circuits based on ferroelectric transistors, and belongs to the field of integrated circuits. According to the invention, a plurality of all-digital in-memory computing circuits based on ferroelectric transistors are designed, weight data can be stored in the computing circuits to carry out all Boolean logic operations based on FEFET logic gate structures, and the all-digital in-memory computing circuit has important significance for breaking through a memory wall and a power consumption wall of a Von. Noiemann architecture. According to the FEFET in-memory calculation unit provided by the invention, relatively fixed weight data can be stored in a calculation circuit, so that the repeated transmission of the weight data is reduced, and the power consumption can be greatly reduced; meanwhile, due to full-digital calculation, multi-bit calculation precision cannot be sacrificed, the accuracy can be effectively improved, and the method is a potential technology applied to an artificial intelligence chip and an AI neural network.

Embodiments are directed to electronic fuse devices and systems. One such electronic fuse includes current sensing circuitry that senses a current in a conductor coupled between a power supply and a load, and generates a current sensing signal indicative of the sensed current. I2t circuitry receives the current sensing signal and determines whether the sensed current exceeds an I2t curve of the conductor. The electronic fuse further includes at least one of external MOSFET temperature sensing circuitry that senses a temperature of an external MOSFET coupled to the conductor, low current bypass circuitry that supplies a reduced current to the load in a low power consumption mode during which the external MOSFET is in a non-conductive state, or desaturation sensing circuitry that senses a drain-source voltage of the external MOSFET.

The super capacitor charging module in the multi-path power supply standby power logic circuit for the novel Internet of Things meter comprises a resistor module, a diode D1 and a capacitor C1, wherein the resistor module, the diode D1 and the capacitor C1 are connected in series and are formed by connecting resistors R1 and R2 in parallel; the input ends of the resistors R1 and R2 which are connected in parallel are connected with + 5.2 V; one end of the capacitor C1 is grounded, and the other end is respectively connected with the diodes D1 and D2; + 5.2 V is respectively connected with the clock battery power supply AVBAT network and the VIN end of the voltage stabilizer U1 through a diode D3, and the output end of the diode D3 is also grounded through a capacitor C6; one path of network battery current ABATT is grounded through a capacitor C2 and a resistor R4 which are connected in parallel, and the other path of network battery current ABATT is connected with a resistor R3; the output end of the resistor R3 is respectively connected with diodes D4 and D6 and a resistor R5; the output end of the diode D4 is connected to the output end of the diode D3; the resistor R5 is connected with a power supply E1, and the power supply E1 is connected with a capacitor C3 in parallel; the output end of the diode D6 is connected with the output end of a diode D5; the structure is compact and use is convenient.

A circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.

The invention discloses a multi-tube parallel power device phase shift type current sharing and crosstalk suppression drive circuit which is composed of a crosstalk suppression unit, a current balancing unit, a control response unit and a function switching unit. Wherein the crosstalk suppression unit generates a control signal for suppressing the crosstalk voltage of the parallel power device and shields the interference of the current balancing unit; the current balancing unit generates a control signal for balancing the dynamic current of the parallel power device and shields the interference of the crosstalk suppression unit; the control response unit is used for realizing crosstalk active clamping or current active equalization; and the mode switching unit realizes automatic switching of a crosstalk suppression function or a current equalization function according to configuration. Parallel device grid driving signal feedback is introduced, crosstalk voltage active clamping and dynamic current active balancing are achieved through a logic circuit, and the parallel expansibility is high; an exclusive-OR gate is adopted to accurately identify synchronous or asynchronous information of driving signals of the parallel devices, and various different gate sequential modes in parallel application of the hybrid devices can be compatible.

The invention provides a chip and a trimming control circuit and a trimming control method thereof, and the trimming control circuit comprises a trimming position generation unit which latches a trimming mode control signal according to a power-on signal so as to generate a trimming enable signal, and counts received trimming clock signals according to the trimming enable signal and a counting enable signal, a trimming position control signal is correspondingly output in each period of counting the trimming clock signal; and a fuse is connected between each trimming control unit and the power supply end, and whether the fuse is fused or not is controlled according to the trimming mode control signal, the corresponding trimming position control signal and the general control signal. According to the method and the device, wrong trimming caused by writing of wrong trimming codes can be avoided, so that the yield and the manufacturing cost of the chip are improved.

A monotonic capacitor digital-to-analog converter (CDAC) is provided. The CDAC includes a converter array comprising a plurality of CDAC units, wherein each CDAC unit comprises a logic unit, a switch, and a capacitor, and wherein each logic unit comprises a first input, a second input, and a third input. The CDAC further includes a first set of control lines, and each of the first set of control lines is connected to the first inputs of the logic units of the CDAC units in a corresponding column of the converter array. The CDAC further includes a second set of control lines, and each of the second set of control lines is connected to the second inputs of the logic units of the CDAC units in a corresponding row of the converter array, but is disconnected from the second input of the logic unit of a CDAC unit in the corresponding row and the last column of the converter array. Each of the second set of control lines is further connected to the third inputs of the logic units of the CDAC units in a row of the converter array adjacent to the corresponding row.

A circuit for driving digital-to-analog converter (DAC) comprising a serializer (110, 210) configured to combine multiple signals to one input signal to drive a forward inverter (311) coupled to a first node (A) with a first impedance in serial configuration and a first capacitance (C1) in shunt configuration. The circuit includes a chain of inverters (321, 322) coupled in series to transfer the input signal from the first node (A) to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter (425) between the third node and the first node (A) to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node (A). A second feedback inverter (425) can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter (425) is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

To reduce programming noise for matrix values stored in a memory array for use in an in-array vector-matrix multiplication, such as for a neural network, the matrix is partitioned into a linear combination of matrices that will preserve the output after the combination, with the small value component matrices being normalize to the lager, full range of values before being programmed into the memory arrays. After multiplying each matrix of the combination with the vector by applying a set of bias values, the outputs are rescaled to undo the normalization before adding the individual outputs back together for the final output. This re-scaling causes the effective noise of small weights to be reduced, providing large noise tolerance for these small weight values.

A system includes: an inverter configured to convert DC power to AC power, wherein the inverter includes: a power module including: a first substrate, a second substrate including a source plane and a gate plane separated from the source plane by a full trench, the source plane including a step trench, and the gate plane including an electrical connection through the second substrate to a gate input connection of the power module, a semiconductor die disposed between the first substrate and the second substrate, the step trench formed in a portion of the source plane corresponding to an edge of the semiconductor die, and the semiconductor die including a gate connected to the gate plane, and a sinter element disposed between the semiconductor die and the second substrate to connect the semiconductor die to the second substrate; a battery; and a motor.

Disclosed is a quantum circuit for implementing multi-controlled NOT gates with N control qubits. A quantum circuit for implementing multi-controlled NOT gates with N control qubits according to one embodiment of the present disclosure may include a first auxiliary circuit that corresponds to one or more initial layers of a plurality of layers and performs a controlled NOT operation on a target qubit based on an Nth control qubit from among the N control qubits and a first auxiliary qubit initialized to a |+> state, a quantum gate group that corresponds to the plurality of layers and performs controlled NOT operation on the first auxiliary qubit based on first to (N−1)th control qubits, and a second auxiliary circuit that corresponds one or more last layers of the plurality of layers and performs controlled NOT operation on the target qubit based on the Nth control qubit and the first auxiliary qubit.

Memory systems and memory dies are provided. The memory system of the present disclosure comprises a plurality of memory dies. The plurality of memory dies are stacked within the memory system. The plurality of memory dies respectively comprises a plurality of numbering circuits. The plurality of numbering circuits are coupled in series as a string. A current stage numbering circuit in the string comprises a plurality of sub-circuits. The plurality of sub-circuits are configured to respectively generate bits of a current stage number signal directly using bits of a previous stage number signal from a previous stage numbering circuit.

The embodiment of the invention provides a bus holding circuit and a bus holder. The bus holding circuit comprises a bus holding module, a configuration module and an anti-backflow module, the bus holding module comprises a pull-up unit and a pull-down unit, the anti-backflow module comprises an input unit and an output unit, the configuration module is used for responding to the voltage of the input end of the bus holding circuit and controlling the pull-up unit or the pull-down unit to be conducted, and the bus holding module is used for locking the voltage state of the input end of the bus holding circuit; the first end of the input unit is connected with the input end of the bus holding circuit, the control end of the input unit is connected with the control end of the output unit, and the output unit is used for mirroring the current of the input unit when the voltage of the input end of the bus holding circuit is greater than a first voltage or the first voltage is powered down. According to the scheme, the applicability of the bus holding circuit to different processes can be expanded.