600 results about "Class-D amplifier" patented technology

A class AD audio amplifier system (10) with DC output detection logic (26) is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which includes a pulse-width-modulator (PWM) (24). The DC detection logic (26) includes a sigma-delta modulator (60) and a digital low-pass filter (62) that monitors the PWM output signals from the PWM modulators (24). The sigma-delta modulator (60) operates at a first clock frequency, while the low-pass filter (62) operates at a much lower clock frequency, so that AC audio components, PWM harmonics, and sigma-delta quantization error is suppressed from the DC detection. The modulated filtered signal is compared against a threshold level (THRSH) to determine whether the amplitude of a DC component at the PWM output is sufficiently high to constitute a fault. If so, a fault detection signal (DC_DET) is issued, and the PWM modulators (24) are disabled to prevent unsafe conditions in the system (10).

A class AD audio amplifier system (10) with improved recovery from clipping events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52−) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. Clip detection logic (26) is provided to detect clipping at the output of the channel (20), preferably by detecting successive edges of the reference waveform without an intervening edge of a PWM output signal. In response to detecting clipping, a first integrator (30; 45) is reset to remove residuals and to eliminate the first integrator (30; 45) from the loop filter of the modulator (24). A saturation level circuit (35) applies a clamping voltage, preferably in both clipping and non-clipping situations, to a second integrator (36; 47). As a result, the loop filter is prevented from entering extreme conditions during clipping, which greatly reduces the clipping recovery time.

A class D amplifier uses a summation of two or more PWM output stages to achieve an increased dynamic range and improved linearity for any given clock operating speed. The amplifier accepts a digital data stream as its input, such as from a compact disk, or other compatible media, at a data rate, Fa, that could be 44.1 kHz, 96 kHz, or any other rate appropriate for audio data. In the preferred embodiment, the input audio data resolution, N bits, would be split into two data samples, of J and K.Internal switching frequency, Fs, switches the PWM with an over sampling factor M, where Fs=M*Fa. The time resolution of the PWM is determined by a precision oscillator that operates at Fc=Fs*(max(J,K)-log2(M)+1).The J most significant bits would be routed to a power PWM stage operated at a DC voltage of VHI. The K least significant bits are routed to a finesse PWM stage operated at a DC voltage of VLO.The ratio of VLO to VHI will be appropriate for the ratio of K and J so the summation of the power PWM stage and the finesse PWM stage will provide the full range of N bits. This summation is accomplished with a low pass filter and time-division multiplexing of the two PWM stages.A micro controller (MCU) is used to apply a sample packet distribution algorithm to provide more resolution by reducing quantization noise in the audio band of interest. The MCU is also used to calibrate the VLO or VHI, or to calibrate the PWM timing of the two PWM stages to achieve appropriate performance.

An interleaved soft switching bridge power converter comprises switching poles operated in an interleaved manner so as to substantially reduce turn-on switching losses and diode reverse-recovery losses in the switching pole elements. Switching poles are arranged into bridge circuits that are operated so as to provide a desired voltage, current and / or power waveform to a load. By reducing switching turn on and diode reverse recovery losses, soft switching power converters of the invention may operate efficiently at higher switching frequencies. Soft switching power converters of the invention are well suited to high power and high voltage applications such as plasma processing, active rectifiers, distributed generation, motor drive inverters and class D power amplifiers.

The invention is directed to an amplifier circuit based on the principle of a class D amplifier. To avoid unwanted convolution effects and to improve the power supply rejection ratio, provision is made for the amplitude of the ramp signal used for pulse width modulation to track proportionally the supply voltage for the amplifier circuit. For this purpose, the ramp signal generator has an amplitude control input suitably connected to supply and reference potentials. This ensures a constant duty ratio which is independent of the supply voltage. The present circuit may be used, for example, as a DC / DC converter or as an audio amplifier.

The present invention relates to bias control of a power amplification circuit of a mobile device for improving the efficiency and the linearity properties of the power amplifier. In one embodiment, the power amplifier improves these properties by receiving a voltage control signal to bias a supplemental amplifier so that the power amplifier operates in a Doherty mode in a low output power range and in a non-Doherty mode in a high output power range. In the non-Doherty mode, the supplemental amplifier is biased as a class AB amplifier via the received voltage control signal to satisfy the non-linear operational requirements of the power amplifier in the high output power range. The power amplifier generates the voltage control signal based upon power levels of signals received from a remote base station.

The present invention relates to a class D audio amplifier comprising a pulse width modulator, an adjustable loop filter and a feedback loop. The pulse width modulator generates a first set of pulse width modulated control signals at an adjustable modulation frequency for respective switch control terminals of a first output driver. A controller of the class D audio amplifier is configured to control frequency response characteristics of the adjustable loop filter based on a frequency setting of the adjustable modulation frequency.

A class-D amplifier includes: an operational amplifier and capacitors, which constitute an integrator for integrating a difference between a plus-sided input signal and a minus-sided input signal which constitute analog input signals; delay circuits for delaying a phase of a triangular wave by a desirable very small angle; resistors, which constitute a synthesizing circuit for synthesizing an output of the integrator, the triangular wave, and outputs of the delay circuits with each other; comparators for comparing outputs of the synthesizing circuit with each other; AND circuits which constitute a buffer for inputting outputs of the comparators; and resistors feeding back an output of the buffer to an input side of the integrator.

A class-D amplifier circuit (30; 30′) providing improved open-loop error for base-band frequencies, such as the audio band, is disclosed. The amplifier circuit (30; 30′) includes a comparator (35) for generating a pulse-width-modulated output signal that is applied to an output power stage (37). An LC filter (32) is at the output of the power stage (37). The amplifier circuit (30; 30′) includes a loop filter having multiple feedback loop paths, with at least one feedback loop path coupled to the output of the power stage (37), and optionally, at least one feedback loop path coupled to the output of the LC filter (32). The transfer function (Hmae(s)) of the loop filter has a real part that has a much steeper slope (on the order of 80 dB / decade) at frequencies above the pulse-width-modulation switching frequency than the slope of its magnitude characteristic at frequencies below this switching frequency.