172results about "Amplifier modifications to raise efficiency" patented technology

A radio frequency (RF) power amplifier based on transformer matching is provided. The RF power amplifier includes: a first-stage amplification circuit configured with an input terminal and an output terminal, wherein the output terminal of the first-stage amplification circuit is configured to be connected to one terminal of a main coil of a first transformer; the first transformer configured to include the main coil and a secondary coil, wherein one terminal of the secondary coil is grounded and the other terminal of the secondary coil is connected to a medium-low power mode input terminal of a power switch; the second-stage amplification circuit configured with an input terminal for receiving the amplified RF signal from the first-stage amplification circuit, wherein an output terminal of the second-stage amplification circuit is configured to be connected to a high power mode input terminal of the power switch.

A Doherty amplifier according to the present disclosure comprises a main amplifier, an auxiliary amplifier, a distribution circuit that distributes signals to the main amplifier and the auxiliary amplifier, and a phase compensation circuit. The main amplifier has a first input matching circuit and a plurality of main amplification stages. The auxiliary amplifier has a second input matching circuit and a plurality of auxiliary amplification stages. The distribution circuit has a first line connected to the first input matching circuit and a second line connected to the second input matching circuit. The electrical length of the first line is such that the input impedance of the first line is higher than the characteristic impedance of the first line and the imaginary component is less than 10% of the real component when a small signal is input. The electrical length of the second line is such that the input impedance of the second line is higher than the characteristic impedance of the second line and the imaginary component is less than 10% of the real component when a small signal is input. The phase compensation circuit is provided in an inter-stage matching circuit of the plurality of main amplification stages or the plurality of auxiliary amplification stages.

This application discloses a differential transmitter circuit, chip, and electronic device. The differential transmitter circuit includes: a single-slip differential drive enhancement circuit, including a single-ended digital input terminal (IN) and a first differential output terminal (IN_P, IN_N), used to convert the input single-ended digital signal into a pair of differential signals; a differential drive circuit, connected to the first differential output terminal (IN_P, IN_N), including a second differential output terminal (OUT_P, OUT_N), used to convert the differential signals into differential output voltages; wherein, the single-slip differential drive enhancement circuit includes a transmission gate (Tran) and an inverter, used to generate the differential signals with a phase difference of 180° and timing matching. The embodiments of this application aim to solve the technical problems of slow response speed, poor common-mode stability, high power consumption, and insufficient noise suppression capability in the prior art when transmitter circuits are used in LVDS interface applications.

An RF amplifier includes a transistor die, an impedance matching circuit, and a baseband termination circuit. The impedance matching circuit includes a first inductive element connected between a transistor terminal and a first node, a second inductive element connected between the first node and an RF input / output, and a first capacitance connected between the first node and a ground reference node. The baseband termination circuit includes a multiple-cell resonator and an envelope capacitor coupled in series between the first node and the ground reference node. The multiple-cell resonator includes at least 4 resonator cells. Each resonator cell includes an RF isolation inductor and an RF isolation capacitor coupled in parallel between the first node and the envelope capacitor, which form a parallel resonant circuit in proximity to a center operating frequency of the RF amplifier. The baseband termination circuit also includes one or more envelope resistors.

A distributed power management apparatus is provided. The distributed power management apparatus includes an envelope tracking (ET) integrated circuit (ETIC) and a distributed ETIC separated from the ETIC. The ETIC is configured to generate a number of ET voltages for a number of power amplifier circuits and the distributed ETIC is configured to generate a distributed ET voltage(s) for a distributed power amplifier circuit(s). In a non-limiting example, the number of power amplifier circuits and the distributed power amplifier circuit(s) can be disposed on opposite sides (e.g., top and bottom) of a wireless device. As such, in embodiments disclosed herein, the ETIC is provided closer to the power amplifier circuits and the distributed ETIC is provided closer to the distributed power amplifier circuit(s). By providing the ETIC and the distributed ETIC closer to the respective power amplifier circuits, it is possible to reduce trace inductance and unwanted signal distortion.

Embodiments of a compensation circuit for a power amplifier (PA) and a method of PA compensation are disclosed. In an embodiment, a compensation circuit for a power amplifier (PA) includes an envelope detector configured to measure an input power of the PA and a bias offset generator configured to apply a voltage offset in response to the input power of the PA to generate bias voltages that are applied to back gates of transistor devices of the PA for distortion compensation and second harmonic (HD2) compensation of the PA.

A power amplifier (100) includes an input end (RFIN), an output end (RFOUT), a first amplification circuit (PA1), a second amplification circuit (PA3), a bias circuit (BIAS3), a current detection circuit (110), and a first protection circuit (120). The first amplification circuit (PA1) includes a first signal input end (IN1) coupled to the input end (RFIN) and a first signal output end (OUT1). The bias circuit (BIAS3) outputs a bias current (IBIAS3) to the second amplification circuit (PA3). The current detection circuit (110) generates a digital control signal (VOCP) according to the bias current (IBIAS3). The first protection circuit (120) selectively reduces the radio frequency signal (RF) input to the first signal input end (IN1) according to the digital control signal (VOCP).

The application discloses a dynamic biasing circuit and method for improving the slew rate of an operational amplifier, which comprises PMOS tubes PM1-PM9, NMOS tubes NM1-NM3, resistors R11, R12, R2, R31 and R32, and detects the step jump of the operational amplifier; the greater the step jump, the greater the differential mode value, the greater the tail current, the greater the working current of the main operational amplifier, the faster the establishment, and the greater the SR; when the step jump is small or no jump, the static current is very small. The dynamic biasing circuit of the application has the advantages of simple structure, rapid response, easy integration and no influence on other performances of the operational amplifier, can efficiently detect the jump of the input signal and instantaneously provide additional driving current, so that the large signal transient response speed of the operational amplifier is fundamentally improved without sacrificing the static power consumption.

This invention provides an amplifier with improved bias tracking performance based on a DSP chip. It includes a file acquisition module that directly acquires the audio file to be played via an interface. The audio file is pre-input into the DSP for standard waveform analysis, which speeds up processing and reduces latency during actual playback. During actual playback, the actual played energy is compared with the pre-calculated energy to determine if it matches the pre-designed output. If it matches, the pre-designed output is used directly; otherwise, it is further input into a model for processing, ensuring operational stability and safety.

The present disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate, and a class-F amplifier (500) according to an embodiment of the present disclosure may comprise: an input matching network (IMN) (510) including an input harmonic tuning network (511) and an input fundamental matching network (512); a power amplifier (PA) (520) electrically connected to the input matching network (510); and a class-F output matching network (F-OMN) (530) electrically connected to the power amplifier (520).

An amplifying circuit (10) comprises: electric power amplifiers (11 and 12); a combining circuit (14) that is connected to an output end of the electric power amplifier (11) and an output end of the electric power amplifier (12); and a first series circuit that is composed of a first switch and a capacitor (171) that are connected in series to each other. The first series circuit is connected between the ground and a connection node (n1) on a path that connects the output end of the electric power amplifier (12) and the combining circuit (14).

According to embodiments, an electronic device is provided. The electronic device may include: a processor; a radio frequency (RF) transceiver; a radio frequency front end (RFFE) module connected to the RF transceiver; an antenna connected to the RFFE module; a battery configured to provide a first voltage; and a power supply circuit configured to supply a second voltage for a power amplifier (PA) on the basis of the first voltage. The RFFE module may include a control circuit for controlling the PA bias in the RFFE module and at least one switch in the RFFE module, and a switching circuit for the control circuit.

The application provides a high-selectivity and simple-structure filter power amplifier and radio frequency integrated circuit, and relates to the field of power semiconductor devices.The application provides stable gate and drain bias voltages for the power amplifier transistor through a gate DC bias network and a drain DC bias network, and guarantees stable operation of the device.The input end and the output end impedance matching network are symmetrically arranged around the power amplifier transistor, both of which contain the same filter impedance transformer, and the layout is compact and simple, without additional independent filter module, effectively simplifying the circuit structure and improving the miniaturization level.Further, the filter impedance transformer is formed by cascading two λ / 4 parallel coupled microstrip lines and is matched with a λ / 2 open microstrip line, and based on the transmission line impedance transformation principle, the filter impedance transformer realizes fundamental real impedance matching, reduces signal transmission loss, forms transmission zero points in the stop band, and significantly improves the frequency selectivity.The overall circuit has high integration, excellent performance, and good engineering application and promotion value.

A particular aspect of the present disclosure comprises a first amplifier (402-1), a first power supply having an output coupled to the supply input of the first amplifier (402-1) and configured to supply a first power to the supply input of the first amplifier (402-1), a second amplifier (402-n), a second power supply having an output coupled to the supply input of the second amplifier (402-n) and configured to supply a second power to the supply input of the second amplifier (402-n), and a third amplifier (406) having a supply input coupled to the first and second power supplies, wherein the first and second power supplies are further configured to supply a third power to the supply input of the third amplifier, This applies to amplification circuits (400) that include the following.

A packaged amplifier device includes a device input terminal, first and second device output terminals, a power amplifier, a power splitter circuit, and first and second impedance matching circuits coupled to a package body. The power amplifier includes a transistor, a transistor input terminal electrically coupled to the device input terminal, and a transistor output terminal. The power splitter circuit includes a splitter input terminal electrically coupled to the transistor output terminal, a first splitter output terminal, and a second splitter output terminal. The first impedance matching circuit is directly connected to the first splitter output terminal and to the first device output terminal, and the second impedance matching circuit is directly connected to the second splitter output terminal and to the second device output terminal. A multiple-stage, multiple-path power amplifier includes the packaged amplifier device and additional amplifier transistors coupled to the first and second device output terminals.

An amplifier includes a transistor, an input circuit coupled between an amplifier input and a transistor input terminal, and an output circuit coupled between a transistor output and a transistor output terminal. The input circuit includes an input-side harmonic termination circuit having a first inductor and a first capacitor connected in series between the transistor input terminal and ground. The output circuit includes a second inductor, an output-side harmonic termination circuit, and a parallel inductor network. The second inductor is coupled between the transistor output terminal and the amplifier output. The output-side harmonic termination circuit includes a third inductor and a second capacitor connected in series between the amplifier output and ground. The parallel inductor network includes a fourth inductor and a third capacitor connected in series between the amplifier output and ground. The input-side and output-side harmonic termination circuits resonate at harmonic frequencies of the amplifier's operating fundamental frequency.

This application provides an operational amplifier, a chip, and an electronic device, and relates to the field of integrated circuit technologies. The operational amplifier includes a first power voltage end, a second power voltage end, a first-stage operational amplification circuit, and a second-stage operational amplification circuit. The first power voltage end is configured to receive a first power voltage signal, the second power voltage end is configured to receive a second power voltage signal, and a voltage value of the first power voltage signal is greater than a voltage value of the second power voltage signal. The first-stage operational amplification circuit is configured to: receive an input signal via a signal input end, and amplify the input signal under enabling control of the first power voltage signal, to generate a first drive signal. The second-stage operational amplification circuit is configured to: generate an output signal based on the first drive signal under enabling control of the second power voltage signal, and output the output signal via a signal output end. The operational amplifier has performance like low noise, low power consumption, high rate, and small area, and can be used in a chip.

This disclosure provides systems, methods, and devices for wireless communications that support multiple antenna operation. In a first aspect, an apparatus for wireless communications includes an amplifier module comprising a first input node, a second input node, a first output node, a second output node, and a third output node, with the amplifier comprising a first processing path configured to couple the first input node to the first output node; and a second processing path configured to couple the second input node to the second output node in a first mode and to couple the second input node to the third output node in a second mode. Other aspects and features are also claimed and described.

A power amplifier circuit is provided which has a configuration including a distributor circuit adding a phase difference to an input signal for distribution, amplifier circuits amplifying the distributed signals, and a combining circuit combining the signals with reduction of the phase difference, and that enables the distortion characteristics and efficiency to be improved.

A dynamic amplifier includes a power supply circuit and first to fourth transistors. The power supply circuit is configured to provide power voltages. The first transistor is configured to be biased by a first auxiliary signal and to receive a first power voltage in the power voltages. The second transistor is configured to be biased by a second auxiliary signal and to receive the first power voltage. The third transistor is configured to receive the power voltages and generate a first output signal according to a first input signal. The fourth transistor is configured to receive the power voltages and generate a second output signal according to a second input signal, in which the third transistor is configured to receive the first power voltage via the first transistor, and the fourth transistor is configured to receive the first power voltage via the second transistor.

This invention discloses a method for improving the stability and gain of a millimeter-wave differential amplifier core. The stability and gain improvement comprises common-mode rejection enhancement and differential-mode gain enhancement. The millimeter-wave differential amplifier core includes a common-emitter amplifier circuit composed of a first transistor and a second transistor, and a common-base amplifier circuit composed of a third transistor and a fourth transistor. A first bias resistor and a second bias resistor are connected in series between the two bases of the first and second transistors. A third bias resistor and a fourth bias resistor are connected in series between the two bases of the third and fourth transistors. The emitter of the third transistor is connected to the collector of the first transistor, and the emitter of the fourth transistor is connected to the collector of the second transistor. A bridging capacitor is also connected between the two bases of the third and fourth transistors. This invention significantly improves the differential-mode gain characteristics of the millimeter-wave band amplifier core while simultaneously enhancing common-mode rejection by combining series capacitors with common-mode gain reduction.

A bias compensation circuit that receives a detection signal from a detection circuit is provided. The detection circuit is configured to detect a radio frequency signal in an amplifier circuit. The bias compensation circuit includes a conversion circuit and a bias circuit. The conversion circuit is coupled to the detection circuit, and is used to adjust a phase or an amplitude of the detection signal to generate an injection signal, wherein the injection signal is a current signal. The bias circuit is coupled to the conversion circuit, and is used to generate a bias signal to the amplifier circuit based on the injection signal, wherein the bias signal varies with the detection signal.

The application relates to a silicon-based millimeter wave broadband compact double-drive high-efficiency Doherty power amplifier, belonging to the technical field of radio frequency integrated circuits, comprising an input quadrature coupler, a main and auxiliary two power amplifier paths and a broadband load modulation output network; wherein the power amplifier path adopts a differential common source and common gate unit with cross-coupling capacitance and a double-mode drive topology to improve the gain and efficiency of the millimeter wave frequency band; the output network adopts a slow wave transmission line structure combined with a cascade coupling line pair to realize broadband active load modulation and absorb transistor parasitic capacitance, and simultaneously optimize the chip area. Thus, the problem that the efficiency and bandwidth are difficult to be considered simultaneously due to the limited load modulation bandwidth and the decreased transistor gain of the traditional silicon-based millimeter wave Doherty power amplifier is solved.

A semiconductor die includes a transistor including a source region, a drain region, a channel between the source region and the drain region, and a gate structure overlying the channel. The gate structure is configured to control a conductivity of the channel vis an electrical voltage applied thereto. The semiconductor die includes a first gate terminal electrically connected to the gate structure and a first harmonic filter inductor formed in a body of the semiconductor die. The first harmonic filter inductor is electrically connected to the first gate terminal. The semiconductor die includes a first harmonic filter capacitor formed in the body of the semiconductor die. The first harmonic filter capacitor includes a first capacitor plate electrically connected to the first harmonic filter inductor and a second capacitor plate connected to a ground reference node.

The application discloses an operational amplifier. The output stage of the operational amplifier comprises: a first output transistor and a second output transistor connected in series, a common node of the two providing an output voltage of the operational amplifier; a first mirror transistor of the first output transistor; a first current limiting structure for limiting a first mirror current flowing through the first mirror transistor; a second mirror transistor of the second output transistor; and a second current limiting structure for limiting a second mirror current flowing through the second mirror transistor. The limitation of the static current of the output transistor can be realized, so that the abnormal increase of the static current in the output transistor is effectively inhibited, and the static power consumption of the operational amplifier is reduced.