36results about How to "Minimum bandwidth" patented technology

The present invention relates to a switch for processing data units, such as IP data packets. The switch can be implemented as a router that includes a plurality of input ports, a plurality of output ports and a switch fabric capable of establishing logical pathways to interconnect a certain input port with a certain output port. A characterizing element of the router is its ability to control bandwidth usage on a basis of a logical pathway. This prevents congestion to occur in the switch fabric and also at the level of the output ports. For every active logical pathway the router sets-up a bandwidth control mechanism including at least one queue to hold data units received at an input port. The bandwidth control mechanism performs an accounting operation to determine the average bandwidth usage and if less than a threshold requests for releasing data units in the switch fabric are sent to the switch fabric controller. When the threshold is exceeded the bandwidth control mechanism stops sending requests for service to the switch fabric controller. The system also supports priorities. Instead of stopping the issuance of signals requesting release of data packets the priority level of the queue (reflected in a priority field in the signal requesting release of a data packet) changes from HI to LO. The switch fabric controller is designed to recognize priority requests and will accept LO priority requests only when there are no other HI priority requests pending. The present invention also provides a data transport device which includes a plurality of nodes interconnected by a physical link that establishes two ring-shaped paths on which data is transported on opposite directions. Each node is capable of sending a control message to the upstream node to advise the upstream node of the data carrying requirements of the node at which the message has originated. The upstream node can then throttle the introduction of data in the paths to preserve capacity that can be used by the downstream nodes.

A bus arbitration section and a resource control section are interposed between a shared resource and a plurality of bus masters. The minimum number of receivable access permissions within a given period is set as bus arbitration information for each of the bus masters. If two or more of the bus masters issue access requests at the same time, the bus arbitration section preferentially gives access permission to a bus master which gained access permission a number of times less than a set value in the bus arbitration information within the given period, out of the two or more access bus masters.

An EDC generating circuit includes a memory unit, an EDC generating circuit, a header generator and an EDC correcting circuit. The EDC generating circuit, which is coupled to the memory unit, is used for generating a first EDC according to at least one main data, and for storing the first EDC to the memory unit. The header generator, which is coupled to the memory unit, is used for generating a header according to header information. The EDC correcting circuit, which is coupled to the memory unit, is used for reading the first EDC from the memory unit and for correcting the first EDC according to the header to generate a second EDC.