4491 results about "Clock synchronization" patented technology

A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.

A pipeline inspection and defect mapping system includes a pig having an inertial measurement unit and a pipeline inspection unit for recording pig location and defect detection events, each record time-stamped by a highly precise onboard clock. The system also includes several magloggers at precisely known locations along the pipeline, each containing a fluxgate magnetometer for detecting the passage of the pig along the pipeline and further containing a highly precise clock synchronized with the clock in the pig. The locations of the various magloggers are known in a north/east/down coordinate system through a differential global positioning satellite process. Finally, a postprocessing off-line computer system receives downloaded maglogger, inertial measurement, and odometer data and through the use of several Kalman filters, derives the location of the detected defects in the north/east/down coordinate frame. Consequently, a task of identifying sites for repair activity is much simplified.

A system and method for synchronizing a local clock to a reference clock using a linear model of the error between the local clock and the reference clock is disclosed. In one embodiment, a direct smoothing process is used in conjunction with the linear model to estimate a frequency offset by which the frequency of an oscillator of the local clock is adjusted. Also disclosed herein is a phased-lock loop (PLL) adapted to synchronize a local clock with a reference clock using the direct smoothing process, as well as a system implementing the PLL for timing the playout of data received from a transmitter.

Timing synchronization between base stations of uncoordinated communication networks includes obtaining timing synchronization information from one base station, and adjusting a clock of the other station in response to the synchronization information. The timing synchronization information can be identified from a strongest synchronization signal from nearby uncoordinated base stations. The timing synchronization can accommodate clock offsets and frequency offsets.

A centralized base station system based on ATCA, comprising a main base station subsystem and one or more remote radio frequency subsystems, the main base station subsystem comprising: one or more shelves based on ATCA platform, each shelf comprising at least one control switch module of ATCA board form; one or more base station controller interface module; a signaling module; one or more baseband processing modules; one or more remote radio frequency interface modules; a first switch network comprising first switch network shelf back board BASE interface link, a control switch module and a first network switch unit; a second switch network comprising a shelf back board FABRIC interface link, a control switch module and a second network switch unit; a clock synchronization network comprising a shelf back board clock synchronization bus, a control switch module and a clock unit; and a signal transmission network, wherein the second network switch unit and the clock unit are further connected to the first network switch unit, one of the control switch modules of all the shelves is the main control module.

Embodiments of the invention enable the synchronization of clocks across packet switched networks, such as the Internet, sufficient to drive a jitter buffer and other quality-of-service related buffering. Packet time stamps referenced to a local clock create a phase offset signal. A shortest-delay offset generator uses a moving-window filter to select the samples of the phase offset signal having the shortest network propagation delay within the window. This shortest network propagation delay filter minimizes the effect of network jitter under the assumption that queuing delays account for most of the network jitter. The addition of this filtered phase offset signal to a free-running local clock creates a time reference that is synchronized to the remote clock at the source thus allowing for the transport of audio, video, and other time-sensitive real-time signals with minimal latency.

A method is provided for synchronizing the playback of a digital audio broadcast on a plurality of network output devices using a microphone near a source, embedded control codes, and the audio patterns from the network output devices. An optional, additional manual adjustment method relies on a graphical user interface for adjustment and audible pulses from the devices which are to be synchronized. Synchronization of the audio is accomplished with clock synchronization of the network output devices. The digital audio broadcast from multiple receivers does not present to a listener any audible delay or echo effect.

Systems and methods are provided that facilitate distributed TDMA communication amongst nodes in an ad hoc wireless network without the need for centralized management and control. A wireless communication device includes a MAC layer that is configured to synchronize its local clock from a beacon frame that is sent by another node in the ad hoc network. After synchronizing its clock to the ad hoc network, the device identifies a timeslot for transmission. When the timeslot arrives, the device senses the channel to determine if there is traffic and if there is no traffic, the device reserves the timeslot by transmitting. In this fashion, a plurality of timeslots can be divided amongst the devices in the ad hoc wireless network for optimized collision free communication using distributed TDMA. This distributed TDMA communication can also be applied across multiple channels in a wireless network to significantly increase bandwidth and quality-of-service.

A method of writing product servo sectors to a disk of a disk drive is disclosed. A plurality of spiral tracks are written to the disk, wherein each spiral track comprises a high frequency signal interrupted at a predetermined interval by a sync mark. During the product servo writing process, the sync marks in the spiral tracks are read to generate a coarse timing recovery measurement, and the high frequency signal in the spiral tracks is read to generate a fine timing recovery measurement. The coarse and fine timing recovery measurements are processed to synchronize a servo write clock used to write the product servo sectors to the disk. In one embodiment the control circuitry within the disk drive synchronizes the servo write clock by reading the spiral tracks, and in an alternative embodiment an external product servo writer synchronizes the servo write clock by reading the spiral tracks.

System and method for synchronizing clocks and maintaining packet timing relationships in a wireless communications system. A preferred embodiment further comprises periodically synchronizing local clocks at a transmitter and a receiver to a clock reference, adding a timestamp to each application packet at a transmitter of a wireless network, setting the timestamp to a value of a local time at the transmitter plus a link delay, buffering a received packet at a receiver, and releasing the buffered packet to an application level when a value of a local time at the receiver equals the timestamp value in the packet. This can help to ensure that the timing relationships between data packets present at a transmitter is maintained at a receiver, regardless of transport delays (waiting, transmission and processing) incurred by the data packets.

A semiconductor integrated circuit and a memory device capable of selecting power-down exit speed and power-save modes and method thereof are provided. The memory device includes a command decoder for generating a power-down signal in response to a power-down command, a mode register (MRS) for storing power-down exit information, a clock synchronization circuit such as a DLL or PLL circuit for generating an internal clock signal synchronized with an external clock signal, and a controller for controlling the DLL or PLL circuit. At power-down exit of the memory device, the power-down exit information can be selected between a fast wakeup time and a slow wakeup time.

A system for managing the simultaneous operation of a plurality of radio modems in a single wireless communication device (WCD). The multiradio control may be integrated into the WCD as a subsystem responsible for scheduling wireless communications by temporarily enabling or disabling the plurality of radio modems within the device. The multiradio control system may comprise a multiradio controller (MRC) and a plurality dedicated radio interfaces. Further, clock synchronization protection between the multiradio system controller, other modems and wireless communication devices with whom the wireless device is communicating may further be implemented as a protective measure to ensure a valid clock synchronization between all devices internal and external to the primary wireless device.

A method and apparatus are provided to achieve frequency synchronization between a first clock at a first node and a second clock at a second node of a packet-carrying communications network. At the first node: a property of packet transmission through the network between the first node and the second node is measured; and the measurement of the property is sent to the second node. At the second node, the same property of packet transmission through the network between the first node and the second node is measured. The measurement of the property made at the first node and the measurement of the property made at the second node are used to synchronize the frequency of the second clock with respect to the first clock.

A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device comprises a register to store a value which is representative of a delay time after which the memory device responds to a read request and clock receiver circuitry to receive first and second external clock signals. The memory device also includes an output driver(s) to output data on a bus, in response to a read request and in accordance with the delay time, wherein a first portion of the data is output synchronously with respect to the first external clock signal and a second portion of the data is output synchronously with respect to the second external clock signal. The memory device may include a delay locked loop to generate internal clock signal(s) using the external clock signal(s). The output drivers output data on the bus in response to the internal clock signal(s). The memory device may include input receiver circuitry, coupled to the bus, the receive the read request, wherein the read request is sampled from the bus synchronously with respect to the first external clock signal.

There are provided an apparatus for performing uplink synchronization in a multiple component carrier system and a method thereof. The method includes determining whether a timing advance value for adjusting uplink timing of a secondary serving cell is valid, entering a transmission holding mode in which the secondary serving cell holds uplink transmission, and determining a releasing condition of releasing the transmission holding mode is satisfied. The timing advance value is secured and the validity of the timing advance value is determined so that it is possible to prevent uplink interference from being generated due to a difference in timing advance values and to prevent capability from deteriorating due to the uplink interference.

A method for synchronizing network elements to a global clock derived from the GPS clock acquired by a plurality of base stations. The global clock is distributed to controllers of various networks, and from there to network access devices. The network access devices further distribute the global clock to various wire-line and local wireless networks and from there, to the users served by these networks. The user equipment is enabled with a simple clock discipliner that adjusts the local clock to the global clock, resulting in a reliable synchronization across the converged communication networks.

In a multiprocessor system that includes a plurality of processor modules, each one of which includes its own internal clock, one of the plurality of processor modules is designated as a master processor module having a master internal clock. Each other processor module is designated as a slave processor module having a slave processor module internal clock. Each slave processor module synchronizes its internal clock with the master internal clock.

A centralized clock distribution mechanism for synchronous TDM communications traffic transported over asynchronous networks such as Ethernet networks. The centralized clocking mechanism of the present invention distributes a high accuracy central clock source to a plurality of CES modules over an Ethernet network. Clock synchronization information based on a high quality clock reference source is distributed to circuit emulation service (CES) modules in the network. CES modules receive the clock synchronization information and use it to reconstruct a local clock. A plurality of clock distributors provide clock redundancy whereby each CES module selects the best clock source to use in reconstructing the local clock.