195 results about "Clock offset" patented technology

The invention discloses a cross-device clock correction method supporting accurate synchronization of meters, and aims to improve the data time consistency among multiple meter devices and meet the requirements of high-precision electric power measurement and event analysis. The method comprises the following steps: acquiring a network time protocol timestamp and a first sampling time sequence in a reference meter, generating a clock reference signal, and broadcasting the clock reference signal to a corrected meter; comparing the corrected meter with a local second sampling time sequence, and calculating a clock skew coarse value vector; further performing wavelet decomposition on the offset coarse value, extracting to form a drift feature vector, fusing the drift feature vector with a historical template, and calculating a unified correction parameter set by using a Bayesian recursion method; and generating a correction pulse sequence carrying a delay residual compensation code based on the parameter set, sending the correction pulse sequence to a corrected meter, calling an interpolation compensation function to construct a piecewise polynomial drift compensation table, and finally realizing dynamic correction and cross-device accurate synchronization of a local real-time clock.

The invention discloses a power distribution network distributed measurement synchronization method and device based on Beidou satellite time service, and belongs to the technical field of power distribution network measurement, and the method comprises the steps: obtaining a Beidou satellite signal, calibrating a local clock source, and generating a standard time reference; when it is continuously monitored that the Beidou satellite signal quality parameter is lower than a quality threshold value, clock working environment parameters of a local clock source are collected, and a short-term clock offset predicted value is generated in combination with a standard time reference; generating topology correction according to the topology connection relation of the power distribution network; and fusing the short-term clock offset predicted value and the topology correction quantity to generate a dynamic compensation time reference, performing time marking on the acquired electrical quantity measurement data of the power distribution network, and generating synchronous measurement data with a timestamp. According to the technical scheme, when the Beidou signal is lost, the local clock drift predicted value and the adjacent node topology correction amount are fused to generate the dynamic compensation time reference, so that the measurement data synchronization precision and robustness of the power distribution network in a complex environment can be remarkably improved.

The invention provides a software ecological migration method and system based on intelligent analysis. Wherein a compatibility evaluation database is deployed in a target architecture, an instruction set mapping rule is preset, and migration risk data is generated through semantic verification; dynamically allocating resources through a heterogeneous virtualization scheduling engine, calling a hardware acceleration unit translation defect instruction, and generating virtualization equipment simulation parameters based on the migration risk data; deploying protocol conversion middleware, dynamically analyzing and reconstructing a network protocol data packet, and combining instruction execution delay data to adjust analysis granularity; in cross-architecture transmission, instruction conversion defects are injected into control logic, timing sequence errors are corrected through clock offset compensation, and corrected data are transmitted back to update instruction mapping rules. According to the technical scheme provided by the invention, the data leakage risk is reduced, and zero shutdown in the migration process is ensured.

The invention discloses a clock tree synthesis method and system based on clustering, and the method comprises the steps: carrying out the preliminary grouping of registers through employing a K-means clustering method, generating the position of a first-stage buffer under the condition that the maximum fan-out number limitation constraint, the maximum RC constraint and the position overlapping constraint are satisfied, and generating a second-stage buffer based on the position, and then constructing a subsequent clock tree by adopting a DME algorithm. The problem of clock signal distribution in large-scale integrated circuit design is solved, clock delay, clock skew and the number of buffers can be reduced, and the comprehensive quality of the clock tree is improved.

The invention discloses a cross-platform distributed synchronous simulation method adopting RoCEv2, and relates to the technical field of communication simulation, and the method comprises the following steps: configuring parameter information of a switch and nodes, and constructing a heterogeneous distributed network of a RoCEv2 enhanced network protocol; deploying a master node global logic time reference, calibrating a slave node clock, starting a sliding window to continuously monitor offset, dynamically detecting clock offset to trigger adjustment, optimizing a time step length in combination with an ECN mark, and dynamically compensating the clock offset of the heterogeneous platform; sequencing events according to logic timestamps to generate DAG topology, and preloading high-frequency events; event data are transmitted through cross-node RDMA, and the main node is sorted and scheduled according to a logic timestamp, so that cross-platform distributed parallel simulation and consistency verification are realized. The method can improve the processing efficiency and fault-tolerant capability of the communication simulation system on large-scale simulation, and can be widely applied to the technical field of communication simulation.

The invention discloses a behavior-driven twinborn prediction method, and relates to the technical field of intelligent information processing and prediction modeling, and the method comprises the following steps: building a unified event time baseline, collecting nanosecond clock offset information of each data source, building a cross time sequence suspicion chart, recognizing time synchronization abnormal nodes, and forming a credible time anchor point set; and based on the trusted time anchor point set, executing anti-fact playback, reconstructing a historical evolution process of behavior data, generating a time offset vector set, and constructing a corresponding time sequence offset spectrum. According to the method, through construction of a unified time baseline, trusted anchor points, anti-fact replay, causal topology and time reversal control, time sequence dislocation identification, calibration and false trajectory elimination of multi-source behavior data are realized, a dynamic self-healing closed-loop prediction mechanism is established, and the twin system prediction accuracy and stability are improved.

The invention relates to the technical field of GNSS (Global Navigation Satellite System) navigation and positioning, in particular to a GNSS real-time precise single-point positioning ambiguity fixing method for a complex environment. The method comprises the steps of obtaining and processing data, obtaining a precision satellite orbit and a precision satellite clock error from original observation data, broadcast ephemeris and an SSR correction number which are originally obtained in sequence, obtaining original frequency point non-difference floating point ambiguity, obtaining fixed integer inter-satellite single-difference wide-lane ambiguity, and obtaining floating point inter-satellite single-difference narrow-lane ambiguity. And finally, selecting the complete set ambiguity according to the precision index of the floating point narrow lane ambiguity, and carrying out iteration to obtain an ambiguity subset meeting the optimal aperture check rule. Through the method, the ambiguity fixing reliability can be further improved, and the convergence time is shortened.

The invention discloses a time calibration method and system for a time synchronization network, and relates to the technical field of communication, and the method comprises the steps: installing a clock on each node in the network; time calibration of a master clock is realized by receiving signals of at least two navigation satellites and calculating a time difference between the satellites; message exchange is carried out between the master clock and the slave clock through a network; calculating network delay and clock offset between the master clock and the slave clock; constructing a transparent clock model, recording delay time passing through each node in a message, and performing compensation when network delay is calculated; dynamically selecting a path with lower network delay to perform message exchange between the master clock and the slave clock; and optimizing the clock skew between the master clock and the slave clock. The error calculation module and the error optimization module are arranged to eliminate the uncertainty of most of network delay and message exchange, so that the time synchronization precision is improved, and the long-term stability of synchronization is improved.

The invention relates to the technical field of on-line monitoring and control, in particular to a sapphire annealing furnace operation state monitoring and controlling method, which specifically comprises the following steps: performing feature matching processing on power supply ripple data to obtain a clock offset compensation value, and performing timestamp synchronization on the power supply ripple data and temperature controller data through the clock offset compensation value; calculating to obtain residual clock offset of the distributed temperature controller, establishing a first-round monitoring model, and performing first-round evaluation on the operation state of the annealing furnace; carrying out reconstruction treatment on the sapphire substrate contact stress field, and carrying out secondary evaluation on the operation state of the annealing furnace; and dynamically adjusting control parameters of the annealing furnace according to the first-round evaluation result and the second-round evaluation result. The problems of power supply fluctuation, clock drift and thermal stress monitoring failure caused by aging of the annealing furnace in the prior art are solved.

The invention provides a real-time synchronous control method and system based on an EtherMAC bus, and the method comprises the steps: obtaining an original transmission frame sequence in a bus transmission channel through a monitoring unit; calculating a path topology priority factor and a clock offset compensation value according to a preset topological structure rule; obtaining a to-be-transmitted data frame sequence based on a calculation result, and adjusting a phase synchronization pulse in the monitoring unit to obtain an adjusted phase synchronization pulse; performing redundancy check on the to-be-transmitted data frame sequence to generate a check state code; when the value reaches a preset error threshold value, extracting a to-be-marked frame from the to-be-transmitted data frame sequence, and generating a synchronization signal set containing a high-reliability identifier; generating a real-time synchronization control instruction for driving the execution terminal based on the phase synchronization pulse and the adjusted phase synchronization pulse; according to the technical scheme provided by the invention, real-time monitoring, frame reconstruction and clock synchronization adjustment of data transmission are realized, and high-precision synchronization response of terminal control is improved.

The invention discloses a high-resolution peak value positioning method based on multi-pulse superposition and offset clock cooperation, and belongs to the technical field of laser radar ranging. Aiming at the problems that a traditional laser radar depends on a high-sampling-rate ADC, so that hardware cost is high, power consumption is large, and sampling errors are likely to be caused by echo jitter, the method does not need to replace an existing ADC, and the technical breakthrough is achieved through the following core steps that firstly, the basic sampling rate X Hz and the target equivalent sampling rate improvement multiple N of the ADC are determined; laser pulses are emitted to a target object for N times, during Kth emission, ADC sampling is started by delaying (K-1) / (X * N) seconds, and N groups of echo data with time sequence offset are obtained; performing cross combination on the N groups of data, and constructing an N-time equivalent high-sampling-rate data sequence; repeating the sampling and combining process for S times, and performing alignment superposition and averaging on S groups of data to suppress echo jitter and noise; and estimating initial parameters (amplitude, mean value and standard deviation) of a Gaussian model based on the superposed data, optimizing the parameters through an LM nonlinear optimization algorithm, and finally taking the optimized mean value as a high-precision peak position of an echo signal to realize accurate measurement of the laser flight time. Under the condition of low-sampling-rate hardware, through the collaborative design of clock skew and multi-pulse superposition, the physical limitation of the sampling rate is broken through, low cost, low power consumption and high ranging precision are taken into account, and the method is adaptive to multi-scene application of automatic driving, industrial ranging and the like.

Disclosed are techniques for wireless communication. In an aspect, an initiator device may transmit a ranging initiation message and a ranging final message to a plurality of responder devices. The initiator device may determine a target relative clock offset between a target responder device of a first subset of the plurality of responder devices and the initiator device based on one or more reference responder devices of a second subset of the plurality of responder devices, the first subset of the plurality of responder devices having successful reception of either the ranging initiation message or the ranging final message, and the second subset of the plurality of responder devices having successful reception of the ranging initiation message and the ranging final message. The initiator device may determine a time of flight based on one or more time of flight measurements and the target relative clock offset.

The invention relates to the technical field of digital audio signal processing, and discloses an audio synchronization multipoint PTS correction method and system, a storage medium and a device, and the method comprises the steps: setting PTS calibration points at a plurality of key nodes on an audio processing link of a master device and a slave device, and carrying out the systematic initialization of an initial PTS value of each calibration point; a clock synchronization mechanism between the master device and the slave device is established, and dynamic calibration of a slave device clock is achieved by periodically interacting time synchronization signals and calculating clock offset; performing multi-stage dynamic adjustment and compensation on the PTS value of the corresponding calibration point according to the network transmission delay fluctuation of the audio frame and the received actual coding duration and time deviation; the filling state and the PTS deviation value of the playing buffer area are monitored in real time, audio output synchronization between the master device and the slave device is maintained through a playing speed fine tuning strategy, optimization is carried out aiming at a lossy coding scene, and the limitation of a traditional single-point synchronization method is effectively solved.

The invention provides a high-precision time synchronization method, system and device for a wireless environment and a medium. The method comprises the steps that a slave node searches and is connected to an AP, a message request is sent, the AP responds to message confirmation, and the slave node joins in a time synchronization domain; the slave node sends a delay measurement request message to the AP, and records the message sending time t1 at the same time; the AP receives the message and obtains the receiving time t2, marks the timestamp with the message ID and updates the timestamp in the memory; the AP loads timestamp data of the AP into a broadcast frame and periodically sends the timestamp data to all STAs, obtains broadcast frame sending time t3 and sends the broadcast frame sending time t3 at the same time; the slave node in the time synchronization domain receives the broadcast frame, records the receiving time t4, and obtains the arrival time t2 corresponding to the ID of the message sent by the slave node; and based on t1, t2, t3 and t4, calculating a link delay and a clock offset between the AP and the slave node and calculating an adjacent rate ratio so as to carry out time synchronization error correction. According to the invention, high-precision time synchronization of a large-scale wireless network can be efficiently realized.

The invention discloses a bridge expansion joint acoustic monitoring method based on a beam forming microphone array, and the method comprises the steps: synchronously collecting acoustic signals through multiple channels, and achieving the high-precision signal alignment through clock offset compensation; the noise analysis module is started by combining a pre-triggering signal of a vehicle passing through the detection unit, the optimal microphone distance is dynamically determined according to sound field coherence and a signal-to-noise ratio maximization model, and a stepping motor drives a movable microphone to achieve real-time adjustment. On the basis, a spatial filtering weight is generated by adopting a self-adaptive beam forming algorithm, and directional enhancement and interference suppression of the expansion joint sound source are realized. Through collaborative optimization of a hardware structure and a signal processing method, the sensitivity and accuracy of acoustic monitoring of the bridge expansion joint are effectively improved, the abnormal sound source recognition capability can be remarkably enhanced, the environmental noise interference is reduced, and the method is suitable for intelligent monitoring and diagnosis of the long-term service state of the bridge expansion joint.

The invention relates to the technical field of clock synchronization, in particular to a clock synchronization method of a master station system based on EtherCAT, which comprises the following steps: when a master station periodically sends time synchronization frames to all slave stations, collecting slave station feedback time data, respectively calculating a clock offset value between master time and slave time, and simultaneously, calculating a clock offset value between the master time and the slave time; constructing a master-slave offset time feature matrix according to the collected multi-periodic data, extracting initial static offset, an offset fluctuation trend and offset collaboration features among multiple slave stations from the constructed master-slave offset time feature matrix, and determining an initial estimation set according to the extracted features; constructing a master-slave offset prediction set based on the initial estimation set, and performing master-slave clock offset adaptive compensation correction based on the determined master-slave offset prediction set; according to the method, the initial offset estimation set is constructed, the offset trend estimation function is introduced, secondary fitting of the offset sequence of each slave station node is achieved, and it is ensured that the prediction precision is remarkably improved through an error comparison mechanism.

The invention discloses an urban trunk network-oriented reconfigurable quantum communication route synchronization system, which relates to the technical field of quantum communication and comprises a quantum channel state sensing module, a clock offset prediction and registration module, a reconfigurable route planning engine, an entangled state registration and regulation module, a synchronization instruction scheduling module and an optimization module. According to the system, de-coherence time, entanglement fidelity and synchronous offset risk of a quantum link are sensed in real time, a quantum link feasibility scoring graph is generated in combination with a graph neural network, and an optimal entanglement forwarding path is output according to the quantum link feasibility scoring graph; meanwhile, the width and rhythm of a transmission window are dynamically adjusted based on task priorities and network loads, and cross-node high-precision synchronization and resource coordination are achieved; a routing and synchronization strategy can be continuously optimized by introducing a communication performance evaluation model and a feedback learning mechanism; according to the invention, the stability of the quantum communication system in a complex urban network environment is significantly improved.

The invention discloses a frequency standard remote calibration method and system based on an NTP protocol. The method comprises the following steps: S1, an NTP protocol server reads a first frequency standard signal meeting a precision requirement as a reference frequency signal and initializes local time; the calibration device reads a calibrated second frequency standard signal as a reference frequency signal, counts time according to a second frequency nominal value and completes initialization; s2, the calibration equipment performs message transmission with a server through an NTP protocol transceiving module, records transceiving timestamps, calculates clock skew and adjusts local time to complete synchronization; s3, the calibration device repeatedly transmits the message according to a preset period, calculates clock skew and network round-trip delay round by round, and obtains a multi-tuple sample; and S4, removing abnormal samples by network round-trip delay, performing linear fitting on reserved samples, and taking a negative value of a fitting slope as a relative frequency deviation of a second frequency standard. According to the invention, remote calibration of the frequency standard is carried out by using the NTP, and compared with satellite and optical fiber remote calibration technologies, the cost required by calibration can be greatly reduced.

The invention provides a chip time sequence analysis method and device, and the method comprises the steps: determining the second data path time delay between the corresponding ports of interconnected modules according to the first data path time delay of the corresponding port of each module and the interconnection relation information between the modules under the condition that a plurality of modules are in a target stable state, the interconnection module comprises two modules which are directly connected in the modules; and determining convergence information of the top time sequence of the interconnection modules according to the clock period, the trigger establishment time, the clock uncertainty, the clock skew between the interconnection modules and the second data path time delay. According to the method and the device, the time sequence between the interconnected modules can be quickly analyzed before the top-layer time sequence analysis is executed, and the time sequence analysis efficiency of the top layer of the chip is improved without waiting for all the modules to complete a physical implementation process.

The embodiment of the invention discloses a chip calibration method and device, a storage medium and electronic equipment, relates to the technical field of communication, and aims to solve the problem of performance reduction caused by time interleaving errors of a chip of a time interleaving architecture in the prior art. According to the method, firstly, the error calculation of the whole link is carried out by directly collecting the digital result output by the ADC, then optimization iteration is carried out in the simulation domain according to the calculated time interleaving error, the numerical value of the corresponding sub-ADC channel register is adjusted, the register is updated in a register control code mode, and the time interleaving error of the whole link is calculated. The offset error, the gain error and the clock offset between the sub-ADC channels are corrected, and finally the chip is calibrated, so that the performance of the chip is improved.

The invention discloses a time sequence synchronization method and system for data fusion of a multi-modal wearable sensor, a terminal and a storage medium. The method comprises the following steps: acquiring an absolute timestamp as a global clock source; taking the global clock source as a master clock of a precision time protocol, configuring the plurality of wearable sensors as slave clocks, and executing multiple rounds of message interaction between the master clock and the slave clocks through the precision time protocol to obtain a timestamp corresponding to each round of interaction; and calculating the current path time delay and the current clock offset according to the corresponding timestamps, carrying out iterative judgment on the current path time delay and the current clock offset according to a preset path time delay threshold value and a preset clock offset threshold value, and determining whether to correct the local clock according to the current clock offset according to an iterative judgment result. The slave clock and the global clock source achieve time sequence synchronization; and after time synchronization is achieved, phase alignment is carried out on the periodic data sampling tasks of the multiple wearable sensors. According to the invention, the time sequence synchronization precision is obviously improved.

The invention provides a multi-terminal clock synchronization method, system and device and a medium, and relates to the technical field of wireless communication, and the method comprises the following steps: a master device sends a synchronization request packet to an ith slave device at a first sending moment; the ith slave device receives the synchronization request packet at the first receiving moment and sends a synchronization response packet to the master device at the second sending moment; the master device receives a synchronization response packet at a second receiving moment, and determines a first receiving moment and a second sending moment according to the synchronization response packet; determining a transmission delay parameter and a clock offset parameter according to the first sending moment, the second sending moment, the first receiving moment and the second receiving moment, and sending the transmission delay parameter and the clock offset parameter to the ith slave device; and the ith slave device adjusts a local timer according to the transmission delay parameter and the clock offset parameter, so that clock synchronization between the ith slave device and the master device is realized. According to the invention, high-precision clock synchronization between multiple slave devices and the master device is realized.

A method includes operating an activation agent to access a clock value and at least one original object. The activation agent communicates said clock value and said at least one original object to an object activation service. The object activation service is operated to generate keying information and expiration criteria for the at least one original object. The keying information includes a clock offset and an async reset value. The object activation service communicates the keying information and the expiration criteria to the activation agent.

The invention provides a time synchronization method executed by slave equipment, and the method comprises the steps: receiving a time synchronization packet from master equipment, and obtaining the packet transmitting time of the master equipment and the packet receiving time of the slave equipment; calculating a clock offset value between the slave device and the master device based on the packet transmitting time of the master device, the packet receiving time of the slave device and the path delay calibration value, and correcting a local clock of the slave device; wherein the path time delay calibration value is related to the distance between the master device and the slave device. The method can correct the clock skew between the master device and the slave device in real time, and improves the time synchronization precision.

Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command / address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

The invention relates to the technical field of power system monitoring, in particular to an electricity stealing identification method and system based on multi-source data, electronic equipment and a medium. The method comprises the following steps: acquiring a running data stream and a local timestamp to obtain a plurality of groups of time sequence data sets; extracting an electrical quantity sudden change event or a non-commanding switch action event in each group of time sequence data set; constructing a multi-constraint model based on the topological connection relationship of the power line, the Kirchhoff's law and the energy conservation law; iteratively calculating the clock offset of each monitoring device relative to the system logic time; and inversely solving node current unbalance and loop power unbalance so as to output a judgment result of an electricity stealing event. Through the mode, the technical problem of cyclic dependence between event causal inference and timestamp calibration under the condition of multi-source asynchronous monitoring data in the prior art is solved, and the reliability, the accuracy and the automation level of electricity stealing behavior analysis are improved.

The invention provides a base station clock information synchronization method and system based on artificial intelligence and related equipment, and relates to the technical field of communication. The method comprises the following steps: acquiring clock state data and / or network performance data of each operator base station in a first time period; fusing the clock state data and / or network performance data of each operator base station in the first time period, and constructing a cross-operator base station clock synchronization feature matrix; the cross-operator base station clock synchronization feature matrix is input into a pre-trained clock skew prediction model, base station clock skew trend information of each operator base station in a second time period is output, and the second time period is a time period after the first time period; and according to the base station clock offset trend information of each operator base station in the second time period, executing a clock information synchronization operation on each operator base station. According to the invention, the service quality of the co-construction and sharing network can be effectively improved, and the reduction of service experience caused by asynchronous base station clocks is reduced.

The invention discloses a time sequence optimization method of a clock tree and a computer readable storage medium, and relates to the technical field of clock tree synthesis and time sequence optimization. The method comprises the steps that a to-be-processed time sequence path is obtained, time sequence optimization is conducted on the to-be-processed time sequence path from the to-be-processed time sequence path, and time sequence optimization comprises the steps that a register with the minimum time sequence margin is determined as a to-be-processed register; determining a target fan-in end timing margin according to the plurality of fan-in end timing margins of the to-be-processed register; and / or determining a target fan-out end timing margin according to the plurality of fan-out end timing margins of the register to be processed; calculating a clock offset according to the target fan-in end timing margin and / or the target fan-out end timing margin; adjusting the time sequence margin of each fan-in end of the register to be processed and / or the time sequence margin of each fan-out end of the register to be processed according to the clock offset; and updating the to-be-processed time sequence path until a set ending condition is met.

A method for determining a state parameter of a global navigation satellite system receiver and an apparatus, in particular its absolute position, determining being based on—a measured information including a pseudorange, a carrier phase and / or a Doppler frequency measurement, —broadcast information on the satellite orbits and clock offsets, and—high accuracy correction information of a satellite positions, clock offsets, code and / or phase biases, the method comprising: —determining a satellite position estimate and a clock offset estimate based on the broadcast information, —determining a corrected satellite position and a corrected clock offset based on the satellite position estimate and the clock offset estimate by using the high accuracy information, in particular the high accuracy correction information of the satellite position and the clock offset.

The invention relates to a time synchronization device, and the device comprises an FPGA chip which is used for dividing the clock frequency of a received initial clock synchronization signal into a first clock frequency point and a second clock frequency point; the clock chip comprises a first phase-locked loop and a second phase-locked loop, and the first phase-locked loop is used for obtaining a system clock according to the first clock frequency point and sending the system clock to the second phase-locked loop; the second phase-locked loop is used for acquiring the PTP clock offset frequency according to the system clock and sending the PTP clock offset frequency to the FPGA chip; the FPGA chip comprises a pulse generator, and the pulse generator is used for generating a pulse signal per second and adjusting the phase of the pulse signal per second according to the PTP clock offset frequency, so that the phase is consistent with the pulse phase per second of the initial clock synchronization signal, and time synchronization is completed. According to the application, clock synchronization of the application equipment and the upstream equipment is realized by utilizing the FPGA chip and the clock chip.