This invention provides an
improved method,
system, and
computer program for performing
matrix multiplication computer instructions. [Solution] The method is a processor having a
control register and a vector register whose length is indicated in the
control register, in which a matrix operation A × B = C is performed, where A is an M ×
K matrix with elements of a first bit width, B is a K × N matrix with elements of a second bit width, and C is an M × N matrix with elements of a third bit width. The instruction has three parameters that
encode the type of multiplication to be performed and indicate which vector register to sequentially store the elements of each matrix in. The method also obtains the length from the
control register,
decodes the instruction to obtain the multiplication type, determines the first and second bit widths according to the multiplication type, determines the values of M, N, and K according to the length and the first and second bit widths, and performs
matrix multiplication considering the three parameters, the first and second bit widths, and the values of M, N, and K.