305 results about "Matrix multiplication" patented technology

A simulation system and method for implementing a model based on an iterative neural network, the system comprising: a simulation vector-matrix multiplication circuit that encodes a weight matrix of the model based on the iterative neural network; and an analog non-linear circuit that encodes a non-linear function arranged in a feedback loop configured to return an output signal from the non-linear circuit as input to the vector-matrix multiplication circuit, wherein the system is configured to output a solution vector of values of the model based on the iterative neural network upon convergence of the system.

The invention provides an operation method of an attention mechanism in a chip, the chip, electronic equipment, a storage medium and a program product. In a forward stage of attention model training, forward calculation is performed on a query matrix, a key matrix and a value matrix in each thread of a calculation engine based on a first instruction pipeline to obtain a forward output matrix, in algorithm implementation, matrix multiplication is executed by calling a matrix multiplication unit through a first thread and a third thread, and a forward output matrix is obtained. The vector calculation is processed by a second thread calling vector calculation unit; in a reverse phase, performing reverse calculation on the query matrix, the key matrix, the value matrix and the output gradient matrix in each thread based on a second instruction pipeline to obtain a target gradient matrix; the matrix multiplication unit is called in the first thread and the third thread to execute matrix multiplication, the vector calculation unit is called in the second thread to execute vector calculation, and the data carrying unit is called in the idle first thread or the third thread to obtain all matrixes. According to the invention, the operation performance of the chip can be improved.

A video coder is configured to receive a first block of video data to be coded using intra prediction, and code the first block of a video data using neural network-based intra prediction model, wherein the neural network-based intra prediction uses a model that includes one or more of: dense matrix multiplications, decoupled training and inference, fusion of normalization layers into matrix multiplication, or rectified linear activations.

The invention provides a quantum circuit system based on an AES cryptosystem and an encryption method. The quantum circuit system based on the AES cryptosystem comprises a byte replacement module which adopts a pre-optimized S-box query circuit to realize non-linear byte replacement; the row shift module completes in-row byte cyclic shift through quantum bit exchange operation; the column confusion module realizes a matrix multiplication circuit based on finite field operation, and a quantum circuit of the column confusion module is generated by a depth-first matrix decomposition algorithm; and the round key adding module realizes XOR operation of a round key and a state by using a CNOT gate array, and a key required by the round key adding module is dynamically generated through a key expansion circuit. And a compact Z-shaped architecture is adopted to optimize time sequence scheduling and resource allocation of each module. On the premise of keeping the quantum bit resource usage amount equivalent to that of an original Z-shaped architecture, the quantum circuit depth is remarkably reduced, and higher fidelity and shorter execution time can be realized on NISQ equipment.

The embodiment of the invention provides a matrix multiplication calculation method and device based on a mercuric chloride chip, equipment and a medium. The method comprises the following steps: acquiring matrix multiplication description information through a plurality of vector calculation kernels, and supplementing a first matrix and a second matrix contained in the matrix multiplication description information to obtain a target first matrix and a target second matrix; obtaining a plurality of first matrix blocks and a plurality of second matrix blocks; for a matrix block pair formed by each first matrix block and the corresponding second matrix block, performing calculation through a matrix calculation kernel to obtain a matrix calculation sub-result; performing vector calculation on the scalar coefficient and the matrix calculation sub-result through the correspondingly distributed vector calculation core to obtain a vector calculation sub-result of each matrix block pair; and fusing a plurality of vector calculation sub-results obtained by calculation based on the plurality of vector calculation cores to obtain a matrix multiplication calculation result corresponding to the matrix multiplication description information. Therefore, the efficiency and accuracy of matrix multiplication calculation can be improved.

Apparatuses and methods for multi-register block-wise matrix multiplication are disclosed. An example processor executes an instruction having an operation object field to indicate that a multi-register cross product matrix multiplication is to be performed with a first plurality of submatrices and a second plurality of submatrices to generate a third plurality of submatrices. An execution circuit executes the instruction to generate each of the third plurality of submatrices in a corresponding vector register of a third plurality of vector registers by multiplying a submatrix in a corresponding vector register of the first plurality of vector registers with a submatrix in a corresponding vector register of the second plurality of vector registers.

Disclosed are systems and techniques for performing matrix multiply operations on an expressive sparse matrix representation with limited metadata. The techniques include receiving a sparse matrix, metadata corresponding to the sparse matrix, and a matrix operand. The sparse matrix contains a first number (N) of elements to retain from a dense matrix which comprises at least a second number (M) of elements. The metadata corresponding to the sparse matrix is based on a third number (P) of positions and a format determined during compression of the dense matrix. The techniques include selecting, by one or more selection circuits, a subset of elements of the matrix operand based on the metadata corresponding to the sparse matrix and performing one or more matrix multiply operations on the sparse matrix and the subset of elements of the matrix operand.

Systems and techniques for providing mixed-precision matrix multiplication in multi-chiplet processors recognize different precision formats of matrices to be multiplied based on, e.g., parameters provided with instructions or start and end memory locations of the matrices. A plurality of different multiplication chains are provided for different formats such that mixed-precision matrix multiplication can be performed using multiplication chains configured to handle multiplication of different precision formats. The multiplication chains are automatically selected based on the precision formats of the matrices to be multiplied, enabling programmers to utilize the chains without having to directly access the individual multiplication chains.

An RNN operator computing method, device, equipment, computer program product and medium are provided. The method is for an RNN operator. First, sequence data containing a plurality of time step input matrices is acquired, and the input matrices are subjected to single matrix-matrix multiplication operation with a layer input weight matrix, thereby generating, at one time, intermediate result matrices corresponding to all time steps for gated calculation. Subsequently, based on a binary semaphore mechanism, the production completion state of the batch of intermediate result matrices is synchronized among a plurality of parallel computing units of a chip. Once the production is confirmed to be completed, each computing unit performs iterative update calculation of the hidden space state in time step order using the ready intermediate result matrices. In the iteration process, the production state of the latest hidden space state is also synchronized between adjacent time step computing units through the binary semaphore mechanism, to ensure the correctness of the time sequence dependency, and finally the hidden space state output corresponding to the entire input sequence is obtained.

Matrix multiplication operations can be implemented, at least in part, on one or more tensor cores of a parallel processing unit. An efficiency of the matrix multiplication operations can be improved in cases where one of the input operands or the output operand of the matrix multiplication operation is a square matrix having a triangular data pattern. In such cases, the number of computations performed by the tensor cores of the parallel processing unit can be reduced by dropping computations and / or masking out elements of the square matrix input operand on one side of the main diagonal of the square matrix. In other cases where the output operand exhibits the triangular data pattern, computations can be dropped or masked out for the invalid side of the main diagonal of the square matrix. In an embodiment, a library implementing the matrix multiplication operations is provided.

The application provides a model quantification method, device and equipment and storage medium, the method comprises: using integer algorithm to execute a plurality of operators of transformer model for image processing, the plurality of operators of the transformer model comprises linear operator and nonlinear operator, wherein the linear operator comprises matrix multiplication operator, the matrix multiplication operator adopts symmetric quantization to quantize floating point value to integer value;The nonlinear operator comprises an activation function operator and a layer normalization operator, the activation function operator adopts polynomial fitting to quantize floating point value to integer value, and the layer normalization operator adopts the mean and standard deviation of input data in the channel dimension to quantize floating point value to integer value.The transformer operator is quantified, so that the inference work of the transformer model for natural language is based on integer operation, so that it can be truly deployed on FPAG chip for practical application.

The application provides an operation method of an attention mechanism in a chip, a chip, an electronic device, a storage medium and a program product; in a forward stage of attention model training, based on a first instruction flow, a query matrix, a key matrix and a value matrix are calculated forward in each thread of a calculation engine to obtain a forward output matrix; in the algorithm implementation, matrix multiplication is executed by a matrix multiplication unit called by a first thread and a third thread, and vector calculation is processed by a vector calculation unit called by a second thread; in a reverse stage, based on a second instruction flow, the query matrix, the key matrix, the value matrix and an output gradient matrix are calculated reversely in each thread to obtain a target gradient matrix; the matrix multiplication unit is called in the first thread and the third thread to execute matrix multiplication, the vector calculation unit is called in the second thread to execute vector calculation, and the data carrying unit is called in the idle first thread or third thread to obtain each matrix. Through the application, the operation performance of the chip can be improved.

Dimension control in tensor multiplication includes obtaining first and second input tensors for matrix multiplication, obtaining a dimension control indicator that indicates a first dimension for the first input tensor to use as a common dimension for the matrix multiplication and indicates a second dimension for the second input tensor to use as the common dimension for the matrix multiplication, and performing the matrix multiplication to obtain one or more results, where performing the matrix multiplication includes selecting at least one vector of the first input tensor based on the first dimension indicated by the dimension control indicator and selecting at least one vector of the second input tensor based on the second dimension indicated by the dimension control indicator.

The embodiment of the invention provides an inference operation method and related equipment and system. According to the embodiment of the invention, when the large model is quantized, the learned reversible matrix H is inserted at the matrix multiplication operation position in the large model so as to suppress the abnormal value in activation, and the quantization difficulty of activation is overcome by utilizing the effect that the reversible matrix has a relatively good abnormal value smoothing effect; and the input and weight of the matrix multiplication operation are transformed once by using the learned reversible matrix so as to ensure the invariance of the calculation. In the embodiment of the invention, the reversible matrix fused into the large model is learnable, can adapt to large model quantization, realizes error minimization before and after model quantization, and can improve the model precision after model quantization.

The application belongs to the technical field of integrated circuits, and discloses a circuit structure for one-step solution of linear equations based on a memristor array, wherein the linear equations are Ax=b, and in the circuit, a first memristor array matrix operation core realizes mapping of the matrix A, takes a negative value of a first operation voltage vector as a bit line voltage, performs a matrix multiplication operation, reads a word line current as a first operation current vector after the operation, a bias mapping module maps b into a bias current vector, a current superposition module superimposes the first operation current vector and the bias current vector to generate a superimposed current vector, and converts the superimposed current vector into a second operation voltage vector through a transimpedance amplifier module, a second memristor array matrix operation core realizes mapping of the matrix A, takes the second operation voltage vector as a bit line voltage, performs a matrix multiplication operation, reads a word line current, and performs an integral operation on the word line current through an integrator module to obtain an updated first operation voltage vector. T The above hardware circuit can realize solution of the linear equations.

The invention provides a distributed computing method and system and related equipment. The method comprises the steps that a management node issues a fusion operator to a computing node; the fusion operator comprises two matrixes and an instruction for realizing matrix multiplication operation of the two matrixes; a plurality of matrix calculation units in the calculation node respectively execute part of the two matrix multiplication operations according to the fusion operator to obtain part of calculation results of the matrix multiplication operations; and executing a communication task to synchronize the partial calculation result. A management node only needs to send a fusion operator to a calculation node, the calculation node can complete calculation of a matrix multiplication according to the fusion operator, and the management node does not need to split the matrix multiplication operation into a plurality of subtasks for calculation and communication and then send the subtasks to the calculation node in sequence. The phenomenon that computing node resources are idle due to management node splitting and task issuing can be avoided, and the utilization rate of the resources and the efficiency of the distributed computing system are improved.

A text segmentation and sensitive word detection method based on matrix multiplication, comprising the following steps: obtaining an original text string and a sensitive word library; constructing a deterministic finite state automaton tree diagram of sensitive words according to the sensitive word library; converting the original text string into a text character two-dimensional matrix and recording the length of the text character two-dimensional matrix; constructing a matching two-dimensional matrix according to a horizontal matching rule, a vertical matching rule, an oblique matching rule and an inverse oblique matching rule, the length of the matching two-dimensional matrix being the same as that of the text character two-dimensional matrix; performing dot multiplication processing on the text character two-dimensional matrix and the matching two-dimensional matrix to obtain a corresponding result matrix; generating a corresponding matching text string according to the result matrix, and matching with the deterministic finite state automaton tree diagram to determine whether there is a sensitive word. The application supports interval text character information detection, improves the sensitive word detection accuracy and detection efficiency.

The invention discloses an RMFE-based distributed matrix multiplication implementation method. The method comprises the following steps: initializing parameters, constructing an RMFE function, splitting a to-be-processed matrix sequence into sequence vectors, sequentially carrying out phi function operation, obtaining a matrix distributed multiplication result through distributed matrix multiplication, and recovering through psi function operation to obtain a multiplication result of a to-be-processed matrix. According to the method, a distributed multiplication problem of a plurality of matrixes on a small domain / Galois ring is converted into a distributed multiplication problem of a single matrix on a large domain / Galois ring, and the calculation overhead on an expansion domain is allocated to the plurality of matrixes, so that the communication overhead required by distributed matrix multiplication is effectively reduced; the method has important application value for a high-speed communication system.

A device, method, and hybrid computing architecture for a Symbolic Photonic Logic Gate (SPLG) system that performs data processing primarily in the optical domain. The system comprises a photonic substrate, including silicon-photonics, indium phosphide, or similar optically active materials, patterned with optical waveguides and interferometric structures configured to implement logic operations through controlled optical interference, phase modulation, or non-linear optical effects. The SPLG system is configured to execute Boolean and symbolic logic functions without requiring intermediate optical-to-electrical signal conversion. In operation, information is encoded into one or more optical parameters including phase, polarization, wavelength, or amplitude, and processed within a Symbolic Optical Core optimized for linear algebraic operations such as matrix multiplication and vector transformation. The architecture further comprises an electronic control layer configured to initialize, configure, and monitor the photonic logic elements while allowing the majority of computational operations to occur within the optical domain, thereby reducing electrical interconnect congestion and resistive heating relative to fully electronic processors.

The invention provides a data processing method and system and related equipment, a plurality of computing nodes of a distributed computing system are used for completing matrix multiplication operation of a first matrix and a second matrix, and each computing node in the plurality of computing nodes comprises n data blocks in the first matrix and partial data of the second matrix; the first computing node at least executes m times of communication subtasks and (m + 1) times of computing subtasks to achieve matrix multiplication of the first matrix and the second matrix. Wherein the first computing node executes the ith communication subtask, and obtains at least one data block from at least one computing node; the first computing node can execute the ith computing sub-task in parallel, and matrix multiplication operation of a plurality of data blocks in the first computing node and partial data of the second matrix is achieved. When matrix multiplication needs to be completed through multiple times of calculation and multiple times of communication, parallel calculation and communication can be achieved through the method, the utilization rate of calculation resources and communication resources in a system is increased, and the calculation efficiency is improved.

A hardware accelerator is provided, including a data acquisition module and a matrix multiplication computation module. The data acquisition module acquires a first matrix forming a first data queue in a first dimension and a second dimension, and a second matrix forming a second data queue in the first dimension and a third dimension. The matrix multiplication computation module includes a three-dimensional array including a plurality of processing elements. Positions of the processing elements are determined based on first dimension values, second dimension values and third dimension values of the processing elements. The processing elements obtain corresponding first data from the first data queue based on the first dimension values and the second dimension values, obtain corresponding second data from the second data queue based on the first dimension values and the third dimension values, and perform matrix multiplication calculation based on the first data and the second data.

The application relates to a QR decomposition-based matrix-vector multiplication implementation method based on a vector processor, and the QR decomposition algorithm is a vsip_cqrd_f function in a VSIP library, the VSIP library is a vector, signal and image processing library launched by a GE intelligent platform, and is an open standard application programming interface specially provided for developers who need to use intensive signal and image processing. The technical scheme of the application mainly comprises the following steps: step one, judging whether input matrix C needs transposition conjugate processing and whether the matrix C is on the left or right in matrix multiplication, so as to enter different branch processing; step two, pre-processing the A matrix; step three, adopting different processing schemes according to the quantity size to realize matrix-vector multiplication operation. The application is designed and realized for the QR decomposition-based matrix-vector multiplication in the light of the advantages of the vector processor, such as large storage space, on-chip cache and efficient and fast data transmission, and can play a great advantage in complex matrix operation.

The embodiment of the invention provides a kernel selection method and device during general matrix multiplication operation, equipment and a storage medium, and belongs to the technical field of computers. The method comprises the following steps: acquiring general matrix multiplication problem size data; preprocessing the general matrix multiplication problem size data to obtain general matrix multiplication problem size features; based on a pre-trained problem size encoder, mapping the general matrix multiplication problem size feature into a problem size embedded vector of a preset dimension; taking the problem size embedded vector as a query vector, and performing nearest neighbor vector search in a pre-configured vector database to obtain a kernel configuration feature with the highest similarity; and outputting the kernel configuration feature as a selection result. The method is used for improving the kernel selection efficiency and precision during the operation of the general matrix multiplication.

The application provides a large model inference optimization method, system, medium, terminal and program product for Ascend processors. The method comprises: comparing the automatically detected version with a built-in compatibility table; if the versions do not match, automatically loading a runtime patch or calling a backup library; if the versions match, processing a user request based on a preset hybrid scheduling mechanism; dynamically selecting a MindIE inference framework or a vLLM inference framework based on a runtime adaptation layer according to the user request parameters; converting large model weights into low-bit weights and compensating based on an error compensation matrix; identifying subgraphs and fusing operators for a model graph according to the computing characteristics of the Ascend processor, and rearranging intermediate tensors according to the 512B memory access alignment rule of the Ascend processor; performing pipelined overlap processing on the matrix multiplication calculation of the current token and the full aggregation operation based on an asynchronous execution flow; and performing inference and generating an inference result according to the user request. The application can improve the efficiency and reliability of large model inference.

Disclosed embodiments relate to an accelerator for sparse-dense matrix instructions. In one example, a processor to execute a sparse-dense matrix multiplication instruction, includes fetch circuitry to fetch the sparse-dense matrix multiplication instruction having fields to specify an opcode, a dense output matrix, a dense source matrix, and a sparse source matrix having a sparsity of non-zero elements, the sparsity being less than one, decode circuitry to decode the fetched sparse-dense matrix multiplication instruction, execution circuitry to execute the decoded sparse-dense matrix multiplication instruction to, for each non-zero element at row M and column K of the specified sparse source matrix generate a product of the non-zero element and each corresponding dense element at row K and column N of the specified dense source matrix, and generate an accumulated sum of each generated product and a previous value of a corresponding output element at row M and column N of the specified dense output matrix.

The present disclosure relates to a method of performing matrix multiplication on a processing unit. The processing unit comprises processing threads, each thread being associated with a multi-value reading register and a multi-value processing register, wherein a capacity of the multi-value processing register is smaller than a capacity of the multi-value reading register. The method comprising: obtaining address data identifying a first matrix input and a second matrix input; transforming at least a portion of the second matrix input to obtain a transformed second matrix input, comprising redistributing a plurality of adjacent linear arrays of the second matrix input to form a single linear array in the transformed second matrix input; obtaining a first matrix subunit from the first matrix input and a transformed second matrix subunit from the transformed second matrix input; and obtaining, using a multi-value reading register, a linear array, R, from the single linear array of the transformed second matrix subunit. The method further comprises, at a thread of the processing unit: obtaining a plurality of values from the first matrix subunit; and for each value in the linear array R, multiplying the value with a corresponding value from the plurality of values of the first matrix subunit and accumulating the results of the multiplying in a linear array P, stored in a multi-value processing register associated with the thread, wherein the accumulated results form at least a portion of an output matrix.

Disclosed is an operation method for executing an addition operation on quantized matrices. This operation method comprises the steps in which: an NPU matrix multiplication unit executes a matrix multiplication operation on a first matrix and a second matrix, wherein the first matrix has a size of R0*2C0 and is obtained by concatenating a first input tensor and a second input tensor, each of which is composed of quantized values and has a size of R0*C0, and the second matrix is obtained by concatenating a first diagonal matrix having a size of C0*C0 and having all main diagonal element values equal to integer N1 and a second diagonal matrix having a size of C0*C0 and having all main diagonal element values equal to integer N2; and an NPU vector processing unit calculates elements of a non-quantized tensor obtainable by adding the second input tensor to the first input tensor, by adding real number B to a product of real number R and a third matrix calculated by the matrix multiplication operation.

The invention belongs to the technical field of ship electric power, and discloses a method and a system for quickly deducing a damaged state of a ship electric power system, and the method comprises the steps: carrying out the modeling of a tree-shaped Bayesian network; and quickly calculating the joint probability of the outage combination. According to the method, a rapid inference algorithm of linear complexity is provided by combining a tree operation structure of a power system, and the exponential complexity O (2n) of a traditional method is reduced to the linear polynomial complexity O (n). The method is realized by calculating the joint probability of the outage combination in a recursion mode: matrix multiplication operation is only required to be performed on each node once, and the total operation times and the node number n are in a linear relation. For an 86-node ship power system, the deduced time consumption is reduced from several hours of a traditional method to less than 0.75 second, and the efficiency is improved by more than 10000 times.

Apparatuses, systems, and methods to perform matrix multiplication. In at least one embodiment, a matrix multiplication is performed based on an indication of whether information to be used by part of the matrix multiplication has been loaded.

The application discloses an information processing method and device, a storage medium and an electronic device, and applies to the field of maps. The method comprises the following steps: acquiring a group of pre-input matrices and post-input matrices, wherein the group of pre-input matrices comprises a plurality of pre-input matrices; when it is detected that the matrix multiplication operation needs to be performed on each pre-input matrix in the group of pre-input matrices and the post-input matrix respectively to obtain a first group of output matrices, and the row merging operation needs to be performed on the first group of output matrices to obtain a first target output matrix, performing the row merging operation on the group of pre-input matrices to obtain a target pre-input matrix; and performing the matrix multiplication operation on the target pre-input matrix and the post-input matrix in a target processing device to obtain the first target output matrix. The application solves the technical problem of low utilization rate of operation resources caused by insufficient operation amount of each resource call in the related art information processing method.