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1543 results about "Quadrilateral" patented technology

In Euclidean plane geometry, a quadrilateral is a polygon with four edges (or sides) and four vertices or corners. Sometimes, the term quadrangle is used, by analogy with triangle, and sometimes tetragon for consistency with pentagon (5-sided), hexagon (6-sided) and so on. The word "quadrilateral" is derived from the Latin words quadri, a variant of four, and latus, meaning "side". Quadrilaterals are simple (not self-intersecting) or complex (self-intersecting), also called crossed.

Hexagonal architecture

InactiveUS6407434B1Reduce total wirelength interconnect congestionReduce the numberTransistorSemiconductor/solid-state device detailsCapacitanceElectrical conductor
Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
Owner:BELL SEMICON LLC

Website display emulating a display of an application program

InactiveUS6973627B1Duplicate other application-like functionalityDigital data information retrievalSpecial data processing applicationsWeb siteWeb browser
A website display configured to emulate the look and feel of an application program is created using a border webpage and a content webpage. The border webpage comprises a table having a plurality of border cells surrounding a center cell. The center cell includes an inline frame configured for displaying the content webpage. The border cells each display a corresponding border image. The border images combine to form a border around the inline frame. The border surrounding the inline frame is preferably a four-sided border. The table and its cells are invisible when the border webpage is displayed. When a navigation command is received for accessing and displaying a second content webpage, the second content webpage is displayed in the inline frame in place of the first content webpage, while the border webpage remains static. A resize command for resizing the display area of the web browser, causes the display area and the border webpage and the content webpage to be proportionately resized. Preferably, scroll bars are suppressed by not allowing the display area to be resized below a minimum point at which scroll bars would normally be displayed. Each border image displayed in the border cells of the table may comprise repeated images that are tiled. Tiling the border images in this manner avoid distortion when the border images are resized. In response to resizing the border cells, the repeated images are retiled accordingly.
Owner:AUTOMATED LOGIC CORP

Methods, apparatus and computer program products for automatically generating nurbs models of triangulated surfaces using homeomorphisms

Embodiments automatically generate an accurate network of watertight NURBS patches from polygonal models of objects while automatically detecting and preserving character lines thereon. These embodiments generate from an initial triangulation of the surface, a hierarchy of progressively coarser triangulations of the surface by performing a sequence of edge contractions using a greedy algorithm that selects edge contractions by their numerical properties. Operations are also performed to connect the triangulations in the hierarchy using homeomorphisms that preserve the topology of the initial triangulation in the coarsest triangulation. A desired quadrangulation of the surface can then be generated by homeomorphically mapping edges of a coarsest triangulation in the hierarchy back to the initial triangulation. This quadrangulation is topologically consistent with the initial triangulation and is defined by a plurality of quadrangular patches. These quadrangular patches are linked together by a (U, V) mesh that is guaranteed to be continuous at patch boundaries. A grid is then preferably fit to each of the quadrangles in the resulting quadrangulation by decomposing each of the quadrangles into k2 smaller quadrangles. A watertight NURBS model may be generated from the resulting quadrangulation.
Owner:3D SYST INC

Compression of three-dimensional geometry data representing a regularly tiled surface portion of a graphical object

Methods and systems for compressing and decompressing 3-D geometry data which includes regularly tiled surface portions. One compression method includes representing a surface portion as a "vertex raster", which comprises specifying an extent value and encoding the vertex parameter values of vertices within the surface portion. The extent of the surface portion specifies the arrangement of vertices within the surface portion, and allows the vertices to be properly assembled into drawing primitives during decompression. The encoded vertex parameter values may be encoded globally (by setting initial values and corresponding delta values), locally (on a per-vertex basis), or using a combination of these techniques. Absolute, delta encoding, or delta-delta encoding may be utilized for these parameter values. Vertex parameters which may be encoded in this manner include position, color, normals, z-displacement values, texture map coordinates, and surface material properties. Additionally, connectivity information may also be encoded using this compression method by specifying quad split bits and half-resolution edges. Quad split bits are used to tessellate a quadrilateral formed by neighboring vertices of a surface portion according to the direction of the strongest color change. Half-resolution edges are utilized to gradually shift from an area of high resolution to an adjacent surface portion represented in lower resolution. For graphical objects which include a plurality of adjacent surface portions, a step command is disclosed which allows data from one surface portion to be advantageously reused. Decompression of a vertex raster representation may comprise decoding the extent value, global parameter values, and a per-vertex stream of local parameter values.
Owner:ORACLE INT CORP
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