67 results about "Dram memory" patented technology

The invention discloses a storage cluster, a system, a data processing method, equipment, a medium and a product, and relates to the technical field of data storage. A plurality of devices are arranged in a controller unit, a switch unit and an extended memory unit; a plurality of switches of the switch unit are correspondingly connected with a plurality of extended memories of the extended memory unit, and copy data of a plurality of controllers are respectively stored in the extended memories. The technical problem that the high availability of a storage system is poor due to the fact that the expansibility of the number of controllers and the number of data copies is poor is solved, and the purposes that memory cache data of the controllers are decoupled from DRAM memories in the controllers to external extended memories, deployment operation is simplified, N-1 controllers are allowed to fail at the same time, and the reliability of the controllers is improved are achieved. The data access processing can be completed under the condition that the M-1 switches simultaneously fail and / or the extended memories corresponding to the P-1 data copies fail, so that the technical effect of high availability of the storage system is improved.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) repairing, in particular to a DRAM failure unit repairing method based on SOC (System On Chip) driving mapping adjustment. The method comprises the following steps: detecting a physical address of a failed CELL unit in a DRAM particle through test equipment, and generating repair mapping data; recording the repair mapping data on the surfaces of the DRAM particles in a two-dimensional code form and storing the repair mapping data in a nonvolatile memory; loading the repair mapping data to a driving program when the SOC is started; and synchronously modifying the address mapping relationship between the MMU and the IOMMU through a driving program, and redirecting the access to the invalid physical address to the standby physical address. By modifying MMU and IOMMU mapping on a driving layer at the same time, unified address remapping of access paths of CPU and DMA equipment is achieved, DRAM particles containing failure units can be used in a capacity reduction mode, PCBA cost is greatly reduced, hardware modification is not needed, and implementation is flexible.

The disclosed embodiments are related to storing critical data in a memory device such as Flash or DRAM memory device. In one embodiment, a device comprising a plurality of parallel processors is disclosed, the plurality of parallel processors configured to: perform a search and match operation, the search and match operation loading a plurality of synaptic identifier bit strings and a plurality of spike identifier bit strings, the search and match operation further generating a plurality of bitmasks; perform a synaptic integration phase, the synaptic integration phase generating a plurality of synaptic current vectors based on the plurality of bitmasks, the synaptic current vectors associated with respective synthetic neurons; solve a neural membrane equation for each of the synthetic neurons; and update membrane potentials associated with the synthetic neurons, the membrane potentials stored in a memory device.

The invention relates to a storage processing method and device based on a capacitance-free DRAM (Dynamic Random Access Memory), and the method comprises the steps: preparing a corresponding writing transistor and a corresponding reading transistor through a preset oxide semiconductor and a silicon transistor; based on a preset heterogeneous integration strategy, vertically stacking the write transistor on the read transistor to establish a capacitance-free DRAM memory unit; the method comprises the following steps: establishing a heterogeneous integrated capacitance-free DRAM memory macro based on a pre-established storage unit peripheral circuit and a capacitance-free DRAM memory unit, and establishing a corresponding in-memory processing architecture according to the heterogeneous integrated capacitance-free DRAM memory macro and a pre-established convolution kernel logic circuit, so as to execute corresponding storage operation through the in-memory processing architecture. Therefore, the technical problems that in the prior art, a DRAM memory processing framework is high in process cost, incompatible in preparation process, high in circuit complexity, poor in memory processing speed and the like are solved.

A machine learning legal natural language generation computing system for developing a pre-trained and instruction fine-tuned MLLNLG generative language model that aligns with human instructions and preferences using causal language modeling for next-token prediction. The training method employs a scaled version of RoPE to compress token position indices, to manage longer sequences beyond the computing hardware devices (GPU's) DRAM memory capacity. This system is optimized for various legal NLP and NLG tasks by receiving input tasks from users through an I / O component. The system enables efficient pre-training of a generative legal language model from scratch on a single computing hardware device (GPU), achieving an efficient MFU of 41.35 and through weight tying, the system reduces model parameters compared to LLMs, eliminating the need for multiple GPUs. Tailored for the legal domain, the model excels in processing legal jargon and demonstrates advanced reasoning capabilities, outperforming existing models in summarization tasks.

Memory devices, memory systems, and methods of operation thereof are disclosed in which a memory device reads data from one or more cells of a memory array of the memory device different from one or more write-only mode registers of the memory device in response to receiving a mode register read (MRR) command for the write-only mode registers. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. A status information mode can be optionally enabled or disabled. The memory device can include a DDR5 DRAM memory device.

A memory controller with adaptive precharge scheduling is described herein. In one aspect, the memory controller includes a refresh scheduler configured to send refresh commands to DRAM banks of a dynamic random access memory (DRAM) memory system, the DRAM memory system including DRAM banks arranged in a set of DRAM banks, each set of DRAM banks including one or more DRAM banks. The memory controller includes an adaptive precharge scheduler configured to determine a priority score for each DRAM bank group based on a set of parameters, and select and close a particular DRAM bank group based on the priority score for each DRAM bank group, and send a precharge command to at least one DRAM bank of the particular DRAM group so that each DRAM bank in the DRAM bank group can be refreshed by the refresh scheduler.

The application relates to a method and device for constructing a back-compatible capacitorless DRAM storage circuit macro, wherein the method comprises the following steps: constructing a multi-layer capacitorless DRAM storage circuit macro according to a full back-compatible channel material meeting preset preparation requirements; constructing a peripheral circuit based on a back-compatible vertical complementary field effect transistor; constructing a complete multi-layer back-compatible capacitorless DRAM storage circuit macro according to each layer of capacitorless DRAM storage circuit macro and the corresponding peripheral circuit, and stacking the complete multi-layer back-compatible capacitorless DRAM storage circuit macro on a target silicon-based circuit based on an interlayer via, so as to obtain a monolithic three-dimensional integrated full back-compatible capacitorless DRAM storage circuit macro. Therefore, the problems that the capacitorless DRAM storage circuit macro based on a silicon-based chip manufacturing process has a relatively short overall storage retention time, frequent refreshing and relatively high power consumption due to the relatively high leakage of a silicon transistor, is not conducive to actual application, and a storage peripheral circuit occupies a relatively large area in the entire circuit macro are solved.

This application provides a multi-core parallel encryption / decryption device. Through a configured encryption / decryption micro-engine, multiple data packets to be encrypted / decrypted, stored in DRAM memory, are distributed to multiple encryption / decryption control modules within the micro-engine. Each encryption / decryption control module calls a DMA controller to copy each data packet to SRAM memory and calls a specific encryption / decryption hardware circuit core to perform encryption / decryption operations on the messages within each data packet. This achieves parallel operation on each data packet, with each operation remaining independent and non-interfering with others, significantly improving the execution efficiency of encryption / decryption operations. It solves the problem in existing technologies where smart network cards (NICs) have limited computing power due to using a single hardware encryption / decryption circuit, making it difficult to achieve the performance indicators of high-speed networks. This helps smart NICs quickly process high-volume real-time services.

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, including: a first base, the first base includes a bit line, a transistor, and a first contact structure that are stacked; and a second base, bonded with the first base, the second base includes a second contact structure and a capacitor that are stacked, and the second contact structure is in contact with the first contact structure in an aligned manner; the first contact structure has a first surface facing the second base and a second surface opposite to the first surface, and an area of the first surface is larger than an area of the second surface; and the second contact structure has a third surface facing the first base and a fourth surface opposite to the third surface, and an area of the third surface is larger than an area of the fourth surface.

This disclosure relates to the semiconductor field and proposes a memory and electronic device. The memory includes an array driving circuit, a memory cell array, a feedback cell array, and an output unit. The memory cell array includes memory cells, and the feedback cell array includes feedback units. The array driving circuit controls the memory cells to enter a data readout phase. The memory cells are used to read stored data to the corresponding feedback unit and output unit when entering the data readout phase. The feedback unit is used to rewrite the read data back into the memory cell. The output unit is used to output the data read from the memory cell. The memory of this disclosure adds a feedback unit to the 2TOC DRAM memory cell, and enhances the anti-interference capability and data retention capability of the floating memory node by using the feedback unit to rewrite the read data back into the memory cell during the data readout phase, thereby improving readout stability and non-volatile memory characteristics.

The invention provides an HBM cache system based on a validity mask and a data processing method of the HBM cache system. The system comprises an HBM cache, an LLC cache, a DRAM memory and a validity mask memory. The HBM cache is connected with the LLC cache and the DRAM memory; taking the HBM cache as a cache of a DRAM (Dynamic Random Access Memory), and caching data from the DRAM; the HBM cache is connected with the validity mask memory. And when the LLC cache is subjected to read missing, write missing or write-back data, the LLC cache mainly reads and writes data from the HBM cache, and then the HBM cache reads and writes data from the DRAM. According to the method, the HBM serves as a cache of the DRAM, caches data from the DRAM and is used for quickly responding to data access requests from the LLC cache, most of the data access requests of the LLC cache are met in the HBM cache, reading and writing of the low-speed and high-delay DRAM are reduced, the advantages of high bandwidth and low delay of the HBM are fully played, the delay of data access is reduced, and the data access efficiency is improved. The system performance is effectively improved, and the storage wall problem can be effectively and economically relieved.

The present invention discloses a forward gradient regression accelerator based on non-volatile memory and an operation method. The forward gradient regression accelerator includes a control module, an in-memory processing module and an operation module. The control module includes a DRAM memory for storing operation data and transmitting corresponding instructions and data to the in-memory processing module and the operation module. The in-memory processing module includes a non-volatile memory array for calculating the cosine similarity between the residual vector and the regression variable for forward gradient regression and transmitting the operation result to the control module. The operation module is used to receive the instructions and data from the control module, complete the data mapping operation and update the regression coefficient and the residual vector. The present invention uses a non-volatile memory array to perform large-scale matrix-vector multiplication operations in a 0(1) manner, and cooperates with the DRAM memory to perform a numerical iterative algorithm with backup data. While achieving accelerated solution to the forward gradient regression problem, it can ensure calculation accuracy.

Embodiments of the disclosure relate to methods for molybdenum gapfill. Additional embodiments provide a method of forming a molybdenum gapfill without substantial voids. Some embodiments of the disclosure are relevant for higher aspect ratio features including DRAM memory cells.

Embodiments of the present application provide a memory access method and device, and relate to the technical field of computers. The method comprises: receiving a memory access request carrying a first virtual page address; obtaining a first page table entry according to the first virtual page address, the first page table entry being a page table entry in a page table with a virtual page address of the first virtual page address; obtaining a storage state identifier used to indicate a storage location of a physical page corresponding to the first page table entry; when the storage state identifier is a first identifier or a second identifier, the first identifier indicating that the physical page corresponding to the first page table entry is stored in a DRAM, and the second identifier indicating that the physical page corresponding to the first page table entry is stored in a PMEM, determining a first physical page according to a physical page address of the first page table entry, and accessing the first physical page; the DRAM and the PMEM are parallel physical memory space supporting application use. Embodiments of the present application are used to avoid waste of DRAM memory space, thereby providing greater total physical memory space.

Embodiments of the present disclosure relate to a method for molybdenum gap filling. Additional embodiments provide a method for forming molybdenum gap fills that are void-free. Some embodiments of the present disclosure relate to higher aspect ratio features including DRAM memory cells.

This invention provides a method, system, device, and storage medium for testing DRAM memory cells. The method includes: writing preset test data into all memory cells of the DRAM to be tested, wherein the memory cells are grouped into memory cell groups according to a preset burst length; creating an access array, accessing the memory cell groups, and obtaining the row and column addresses of the memory cell groups; reading the current test data of the corresponding memory cell group according to the row and column addresses, and comparing it with the preset test data of the memory cell group; if the comparison results are consistent, the memory cell group is determined to have been accessed; obtaining the four adjacent row and column addresses on the diagonal according to the row and column addresses, and determining whether the corresponding adjacent memory cell groups have been accessed according to the adjacent row and column addresses; if all adjacent memory cell groups have been accessed, the test is determined to have passed. This invention can cover test blind spots and detect chip defects that are difficult to find, improve fault coverage, and enhance product quality.

The invention discloses a memory device access control method, a program product, a device and a medium, and relates to the technical field of computers, comprising: respectively configuring a first memory address space and a second memory address space for a dynamic random access memory medium and a flash memory medium of a memory device; dividing the dynamic random access memory medium into a first storage area and a second storage area; the first storage area is mapped to a first memory address space for a host to access and store preset high-access-demand data, and the second storage area is a cache of the flash memory medium and is used for temporarily storing preset low-access-demand data and nonvolatile data; and routing the memory access request to the corresponding storage area. According to the method and the device, the problems that the cost is obviously increased and the nonvolatile characteristic is not supported due to capacity improvement of CXL-DRAM memory extension equipment are solved, and the problems that the access speed of CXL-SSD solid-state storage equipment is slower than that of the CXL-DRAM, and the speed depends on the memory capacity of the equipment side are solved.

This invention discloses a method and system for mitigating write interference in non-volatile memory based on block selection. It stores the model and metadata required for block selection on traditional DRAM memory, utilizes the characteristics of write interference to process and classify old data, and selects appropriate write locations for new data to be written to reduce write interference errors. A write interference tendency vector extraction technique can abstract the maximum number of write interference errors when each bit of old data is written. An old data block classification technique uses a clustering algorithm to group old data blocks with similar write interference tendencies into the same category. A write category selection technique first extracts an attack vector for new data based on whether each bit will cause a write interference error during writing, and then uses the attack vector to select the old data category. An intra-category write location selection technique uses a hash algorithm to select the most suitable write location for new data to further reduce write interference errors.

When reading and writing DRAM (dynamic random-access memory), the latency and bandwidth is often unpredictable with large variations. One reason is because all the DRAM memory banks require periodic refreshes and maintenance cycles that interrupt these accesses. DRAM refresh and maintenance cycles are synchronized with the read / write accesses in a mutually exclusive manner, hence, preventing the accesses from being interfered with by a refresh or maintenance cycle resulting in predictable latency and bandwidth performance during read / write operations.

Memory device architectures including integrated static random access memory based tag circuitry and dynamic random access memory cells are discussed related to improving density and device performance Such memory device architectures include vertically aligned dynamic random access memory cells and memory tag circuitry aligned and implemented within the same monolithic integrated circuit die or on stacked interconnected monolithic integrated circuit dies.

The application discloses a storage cluster, a system, a data processing method, equipment, a medium and a product, relates to the technical field of data storage, and solves the technical problem of poor high availability of a storage system caused by poor scalability of the number of controllers and the number of data copies by controlling the number of devices in the controller unit, the switch unit and the extension memory unit, respectively, and respectively corresponding redundant devices existing in each unit, a plurality of switches of the switch unit being connected to a plurality of extension memories of the extension memory unit, and each of the plurality of extension memories storing copy data of a plurality of controllers. The memory cache data of the controller is decoupled from the DRAM memory inside the controller to the external extension memory, the deployment operation is simplified, and the data access processing can be completed in the case that N-1 controllers fail simultaneously, M-1 switches fail simultaneously and / or P-1 extension memories corresponding to the data copies fail, thereby improving the technical effect of the high availability of the storage system.

Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

This invention discloses an image compression method, system, and apparatus for LED display control systems, belonging to the field of image compression. The method includes the following steps: hardware decoding of the HDMI or DVI video interface input signal to parse the original RGB image data stream; caching a complete image frame data in DRAM memory; performing overall compression encoding on the complete image frame data; packaging the image data after overall compression encoding into Ethernet frame data according to two-dimensional information; parsing the compressed image data from the Ethernet frame data; performing partitioned decompression decoding on the parsed image data; and caching the partitioned decompression decoding image frame data in DRAM memory. This invention employs an intra-frame compression transmission technology based on discrete wavelet transform, using overall compression at the encoding end and partitioned decompression at the decoding end, enabling decompression of compressed images at a very low cost.

The application relates to the technical field of integrated circuit testing, and discloses a full-automatic DRAM memory unit read-write function test method and system, which comprises the following steps: collecting a silk-screen image of a to-be-tested chip, identifying the silk-screen image by using a ResNet neural network to obtain silk-screen information; reading a read-write function test method matched with the silk-screen information from a preset database according to the silk-screen information, and transmitting the read-write function test method to an ATE device; electrically connecting the ATE device with the to-be-tested chip, and performing read-write function test on the to-be-tested chip by the ATE device according to the received read-write function test method. The application realizes the automation of DRAM memory unit read-write function test work, effectively improves the read-write function test work efficiency, and ensures a high read-write function test accuracy.

Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

The present application relates to the technical field of DRAM memory repair, in particular to a DRAM failure unit repair method based on SOC driving mapping adjustment.The present application detects the physical address of the failure CELL unit in the DRAM grain through a test device, generates repair mapping data, records the repair mapping data in the form of a two-dimensional code on the surface of the DRAM grain and stores the repair mapping data to a non-volatile memory, loads the repair mapping data to a driving program when the SOC starts, synchronously modifies the address mapping relationship of the MMU and the IOMMU through the driving program, and redirects the access to the failure physical address to a backup physical address.The present application simultaneously modifies the MMU and the IOMMU mapping at the driving level, realizes the unified address remapping of the CPU and the DMA device access path, makes the DRAM grain containing the failure unit be used in a reduced capacity, greatly reduces the PCBA cost, and does not need to be modified in hardware, and is flexible to implement.

This invention relates to the field of DRAM circuit design technology, specifically to a sensitive amplifier, readout circuit, and module based on bit-line switches and capacitive coupling. The invention discloses a DRAM sensitive amplifier based on bit-line switches and capacitive coupling, comprising: nine NMOS transistors N1-N9, two PMOS transistors P1-P2, and two capacitors Cc1-Cc2. This invention designs a Selective Sensing Amplifier (SCSA) and, with corresponding control logic, incorporates a pre-charge phase, offset calibration phase, charge sharing phase, pre-sensing phase, and main sensing phase during DRAM memory cell readout. This ensures that the bit line BLT or BLB potential changes correctly, guaranteeing the SCSA readout amplification function. Compared to traditional DRAM sensitive amplifiers, the SCSA provided by this invention achieves a significant reduction in offset voltage and effectively increases sensing margin with only a small increase in the number of components.

The disclosed embodiments are related to storing critical data in a memory device such as Flash or DRAM memory device. In one embodiment, a device comprising a plurality of parallel processors is disclosed, the plurality of parallel processors configured to: perform a search and match operation, the search and match operation loading a plurality of synaptic identifier bit strings and a plurality of spike identifier bit strings, the search and match operation further generating a plurality of bitmasks; perform a synaptic integration phase, the synaptic integration phase generating a plurality of synaptic current vectors based on the plurality of bitmasks, the synaptic current vectors associated with respective synthetic neurons; solve a neural membrane equation for each of the synthetic neurons; and update membrane potentials associated with the synthetic neurons, the membrane potentials stored in a memory device.

The application discloses a single-core processing core and a control method thereof, a many-core communication architecture and a chip. Each single-core processing core has an on-chip network interface and a memory access interface for external data transmission, and inter-core data transmission is performed through the on-chip network interface. The single-core processing core has a computing engine, a control unit, a data exchange unit, a parameter RAM, an NI unit, a DMA unit, a queue transmission unit, a weight gradient transmission unit, a data exchange bus and a control bus. The queue transmission unit is used for realizing hardware queue expansion and acceleration between front and back. The weight gradient transmission unit is used for providing transmission acceleration for frequent reading and writing of weight gradient DRAM memory of a deep neural network. The weight gradient is stored in the DRAM memory to accelerate gradient reading and writing access of the weight gradient calculation. Based on this, the embodiment of the application can improve the transmission performance and energy efficiency of inter-core communication and reduce the DNN training data transmission delay.