42 results about "Dram memory" patented technology

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) repairing, in particular to a DRAM failure unit repairing method based on SOC (System On Chip) driving mapping adjustment. The method comprises the following steps: detecting a physical address of a failed CELL unit in a DRAM particle through test equipment, and generating repair mapping data; recording the repair mapping data on the surfaces of the DRAM particles in a two-dimensional code form and storing the repair mapping data in a nonvolatile memory; loading the repair mapping data to a driving program when the SOC is started; and synchronously modifying the address mapping relationship between the MMU and the IOMMU through a driving program, and redirecting the access to the invalid physical address to the standby physical address. By modifying MMU and IOMMU mapping on a driving layer at the same time, unified address remapping of access paths of CPU and DMA equipment is achieved, DRAM particles containing failure units can be used in a capacity reduction mode, PCBA cost is greatly reduced, hardware modification is not needed, and implementation is flexible.

A machine learning legal natural language generation computing system for developing a pre-trained and instruction fine-tuned MLLNLG generative language model that aligns with human instructions and preferences using causal language modeling for next-token prediction. The training method employs a scaled version of RoPE to compress token position indices, to manage longer sequences beyond the computing hardware devices (GPU's) DRAM memory capacity. This system is optimized for various legal NLP and NLG tasks by receiving input tasks from users through an I / O component. The system enables efficient pre-training of a generative legal language model from scratch on a single computing hardware device (GPU), achieving an efficient MFU of 41.35 and through weight tying, the system reduces model parameters compared to LLMs, eliminating the need for multiple GPUs. Tailored for the legal domain, the model excels in processing legal jargon and demonstrates advanced reasoning capabilities, outperforming existing models in summarization tasks.

Memory devices, memory systems, and methods of operation thereof are disclosed in which a memory device reads data from one or more cells of a memory array of the memory device different from one or more write-only mode registers of the memory device in response to receiving a mode register read (MRR) command for the write-only mode registers. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. A status information mode can be optionally enabled or disabled. The memory device can include a DDR5 DRAM memory device.

A memory controller with adaptive precharge scheduling is described herein. In one aspect, the memory controller includes a refresh scheduler configured to send refresh commands to DRAM banks of a dynamic random access memory (DRAM) memory system, the DRAM memory system including DRAM banks arranged in a set of DRAM banks, each set of DRAM banks including one or more DRAM banks. The memory controller includes an adaptive precharge scheduler configured to determine a priority score for each DRAM bank group based on a set of parameters, and select and close a particular DRAM bank group based on the priority score for each DRAM bank group, and send a precharge command to at least one DRAM bank of the particular DRAM group so that each DRAM bank in the DRAM bank group can be refreshed by the refresh scheduler.

The application relates to a method and device for constructing a back-compatible capacitorless DRAM storage circuit macro, wherein the method comprises the following steps: constructing a multi-layer capacitorless DRAM storage circuit macro according to a full back-compatible channel material meeting preset preparation requirements; constructing a peripheral circuit based on a back-compatible vertical complementary field effect transistor; constructing a complete multi-layer back-compatible capacitorless DRAM storage circuit macro according to each layer of capacitorless DRAM storage circuit macro and the corresponding peripheral circuit, and stacking the complete multi-layer back-compatible capacitorless DRAM storage circuit macro on a target silicon-based circuit based on an interlayer via, so as to obtain a monolithic three-dimensional integrated full back-compatible capacitorless DRAM storage circuit macro. Therefore, the problems that the capacitorless DRAM storage circuit macro based on a silicon-based chip manufacturing process has a relatively short overall storage retention time, frequent refreshing and relatively high power consumption due to the relatively high leakage of a silicon transistor, is not conducive to actual application, and a storage peripheral circuit occupies a relatively large area in the entire circuit macro are solved.

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, including: a first base, the first base includes a bit line, a transistor, and a first contact structure that are stacked; and a second base, bonded with the first base, the second base includes a second contact structure and a capacitor that are stacked, and the second contact structure is in contact with the first contact structure in an aligned manner; the first contact structure has a first surface facing the second base and a second surface opposite to the first surface, and an area of the first surface is larger than an area of the second surface; and the second contact structure has a third surface facing the first base and a fourth surface opposite to the third surface, and an area of the third surface is larger than an area of the fourth surface.

This disclosure relates to the semiconductor field and proposes a memory and electronic device. The memory includes an array driving circuit, a memory cell array, a feedback cell array, and an output unit. The memory cell array includes memory cells, and the feedback cell array includes feedback units. The array driving circuit controls the memory cells to enter a data readout phase. The memory cells are used to read stored data to the corresponding feedback unit and output unit when entering the data readout phase. The feedback unit is used to rewrite the read data back into the memory cell. The output unit is used to output the data read from the memory cell. The memory of this disclosure adds a feedback unit to the 2TOC DRAM memory cell, and enhances the anti-interference capability and data retention capability of the floating memory node by using the feedback unit to rewrite the read data back into the memory cell during the data readout phase, thereby improving readout stability and non-volatile memory characteristics.

Embodiments of the disclosure relate to methods for molybdenum gapfill. Additional embodiments provide a method of forming a molybdenum gapfill without substantial voids. Some embodiments of the disclosure are relevant for higher aspect ratio features including DRAM memory cells.

This invention provides a method, system, device, and storage medium for testing DRAM memory cells. The method includes: writing preset test data into all memory cells of the DRAM to be tested, wherein the memory cells are grouped into memory cell groups according to a preset burst length; creating an access array, accessing the memory cell groups, and obtaining the row and column addresses of the memory cell groups; reading the current test data of the corresponding memory cell group according to the row and column addresses, and comparing it with the preset test data of the memory cell group; if the comparison results are consistent, the memory cell group is determined to have been accessed; obtaining the four adjacent row and column addresses on the diagonal according to the row and column addresses, and determining whether the corresponding adjacent memory cell groups have been accessed according to the adjacent row and column addresses; if all adjacent memory cell groups have been accessed, the test is determined to have passed. This invention can cover test blind spots and detect chip defects that are difficult to find, improve fault coverage, and enhance product quality.

The invention discloses a memory device access control method, a program product, a device and a medium, and relates to the technical field of computers, comprising: respectively configuring a first memory address space and a second memory address space for a dynamic random access memory medium and a flash memory medium of a memory device; dividing the dynamic random access memory medium into a first storage area and a second storage area; the first storage area is mapped to a first memory address space for a host to access and store preset high-access-demand data, and the second storage area is a cache of the flash memory medium and is used for temporarily storing preset low-access-demand data and nonvolatile data; and routing the memory access request to the corresponding storage area. According to the method and the device, the problems that the cost is obviously increased and the nonvolatile characteristic is not supported due to capacity improvement of CXL-DRAM memory extension equipment are solved, and the problems that the access speed of CXL-SSD solid-state storage equipment is slower than that of the CXL-DRAM, and the speed depends on the memory capacity of the equipment side are solved.

This invention discloses a method and system for mitigating write interference in non-volatile memory based on block selection. It stores the model and metadata required for block selection on traditional DRAM memory, utilizes the characteristics of write interference to process and classify old data, and selects appropriate write locations for new data to be written to reduce write interference errors. A write interference tendency vector extraction technique can abstract the maximum number of write interference errors when each bit of old data is written. An old data block classification technique uses a clustering algorithm to group old data blocks with similar write interference tendencies into the same category. A write category selection technique first extracts an attack vector for new data based on whether each bit will cause a write interference error during writing, and then uses the attack vector to select the old data category. An intra-category write location selection technique uses a hash algorithm to select the most suitable write location for new data to further reduce write interference errors.

Memory device architectures including integrated static random access memory based tag circuitry and dynamic random access memory cells are discussed related to improving density and device performance Such memory device architectures include vertically aligned dynamic random access memory cells and memory tag circuitry aligned and implemented within the same monolithic integrated circuit die or on stacked interconnected monolithic integrated circuit dies.

Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

This invention discloses an image compression method, system, and apparatus for LED display control systems, belonging to the field of image compression. The method includes the following steps: hardware decoding of the HDMI or DVI video interface input signal to parse the original RGB image data stream; caching a complete image frame data in DRAM memory; performing overall compression encoding on the complete image frame data; packaging the image data after overall compression encoding into Ethernet frame data according to two-dimensional information; parsing the compressed image data from the Ethernet frame data; performing partitioned decompression decoding on the parsed image data; and caching the partitioned decompression decoding image frame data in DRAM memory. This invention employs an intra-frame compression transmission technology based on discrete wavelet transform, using overall compression at the encoding end and partitioned decompression at the decoding end, enabling decompression of compressed images at a very low cost.

The application relates to the technical field of integrated circuit testing, and discloses a full-automatic DRAM memory unit read-write function test method and system, which comprises the following steps: collecting a silk-screen image of a to-be-tested chip, identifying the silk-screen image by using a ResNet neural network to obtain silk-screen information; reading a read-write function test method matched with the silk-screen information from a preset database according to the silk-screen information, and transmitting the read-write function test method to an ATE device; electrically connecting the ATE device with the to-be-tested chip, and performing read-write function test on the to-be-tested chip by the ATE device according to the received read-write function test method. The application realizes the automation of DRAM memory unit read-write function test work, effectively improves the read-write function test work efficiency, and ensures a high read-write function test accuracy.

Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

The present application relates to the technical field of DRAM memory repair, in particular to a DRAM failure unit repair method based on SOC driving mapping adjustment.The present application detects the physical address of the failure CELL unit in the DRAM grain through a test device, generates repair mapping data, records the repair mapping data in the form of a two-dimensional code on the surface of the DRAM grain and stores the repair mapping data to a non-volatile memory, loads the repair mapping data to a driving program when the SOC starts, synchronously modifies the address mapping relationship of the MMU and the IOMMU through the driving program, and redirects the access to the failure physical address to a backup physical address.The present application simultaneously modifies the MMU and the IOMMU mapping at the driving level, realizes the unified address remapping of the CPU and the DMA device access path, makes the DRAM grain containing the failure unit be used in a reduced capacity, greatly reduces the PCBA cost, and does not need to be modified in hardware, and is flexible to implement.

This invention relates to the field of DRAM circuit design technology, specifically to a sensitive amplifier, readout circuit, and module based on bit-line switches and capacitive coupling. The invention discloses a DRAM sensitive amplifier based on bit-line switches and capacitive coupling, comprising: nine NMOS transistors N1-N9, two PMOS transistors P1-P2, and two capacitors Cc1-Cc2. This invention designs a Selective Sensing Amplifier (SCSA) and, with corresponding control logic, incorporates a pre-charge phase, offset calibration phase, charge sharing phase, pre-sensing phase, and main sensing phase during DRAM memory cell readout. This ensures that the bit line BLT or BLB potential changes correctly, guaranteeing the SCSA readout amplification function. Compared to traditional DRAM sensitive amplifiers, the SCSA provided by this invention achieves a significant reduction in offset voltage and effectively increases sensing margin with only a small increase in the number of components.

The application discloses a single-core processing core and a control method thereof, a many-core communication architecture and a chip. Each single-core processing core has an on-chip network interface and a memory access interface for external data transmission, and inter-core data transmission is performed through the on-chip network interface. The single-core processing core has a computing engine, a control unit, a data exchange unit, a parameter RAM, an NI unit, a DMA unit, a queue transmission unit, a weight gradient transmission unit, a data exchange bus and a control bus. The queue transmission unit is used for realizing hardware queue expansion and acceleration between front and back. The weight gradient transmission unit is used for providing transmission acceleration for frequent reading and writing of weight gradient DRAM memory of a deep neural network. The weight gradient is stored in the DRAM memory to accelerate gradient reading and writing access of the weight gradient calculation. Based on this, the embodiment of the application can improve the transmission performance and energy efficiency of inter-core communication and reduce the DNN training data transmission delay.

This invention discloses a PDMS-based hybrid block copolymer, its preparation method, and its applications. The structural formula of the PDMS-based hybrid block copolymer of this invention is as follows: [Formula omitted for brevity], where R1 and R2 are independently selected from H, C1 to C1. 12 The alkyl, benzyl, or alkyl group is used, R3 is selected from H or phenyl, m is an integer from 6 to 56, n is an integer from 16 to 128, and t is an integer from 0 to 5. The PDMS-based hybrid block copolymer of this invention has advantages such as uniform chemical composition, precise controllable degree of polymerization and chemical composition, well-defined block linkage structure, and high self-assembly driving force. It can self-assemble into a periodic ordered structure with ultra-high resolution and ultra-high controllability, making it suitable for the manufacture of advanced semiconductor devices such as DRAM memory and 3D NAND flash memory in advanced technology nodes.

The invention provides a DRAM (Dynamic Random Access Memory) storage unit structure and a preparation method thereof. The DRAM storage unit structure comprises a substrate, a word line, a bit line, a plurality of vertical channel transistors and capacitor units positioned below the vertical channel transistors, the capacitor unit is located on the substrate and vertically extends into the substrate; a source region, a gate region and a drain region of the vertical channel transistor are sequentially arranged from top to bottom, and the capacitor unit is connected below the drain region; the word line is connected with the gate regions of the at least two vertical channel transistors, and the bit line is connected with the source regions of the at least two vertical channel transistors. According to the invention, the fringe effect is reduced to the greatest extent, subsequent integration with peripheral circuits is facilitated, and the overall performance of the device is improved.

A multi-cycle path circuit includes a logic circuit, a memory, and an on-chip clock controller. The multi-cycle path circuit is configured to operate in a functional mode in which the logic circuit controls reading and / or writing of the memory, and in a full-speed test mode in which the logic circuit controls reading and / or writing of the memory. The invention uses a clock pulse shaping circuit to control a functional mode clock gating element and a clock divider to establish a multi-cycle phase relationship between a clock into the logic and a secondary cache DRAM memory timing path. It also ensures that the clock path into and out of the secondary cache DRAM is the same in the functional mode and the full-speed test mode to avoid hold and set timing conflicts between these modes.

The invention relates to a vector data storage and retrieval technology, and provides a document vector caching method based on a persistent memory and a weight aiming at the problems of performance and capacity limitation, low cache hit rate, low resource utilization rate and inadaptability to importance difference of an existing vector caching strategy. Document vectors are cached, a DRAM is used for caching the document vectors with high weights, a persistent memory is used for caching the document vectors and document slices, meanwhile, a vector weight calculation model is constructed for admission and update replacement of vector caching, a persistence and recovery mechanism is achieved, and the cache state is automatically recovered after a system is restarted. Efficient and intelligent vector cache management is achieved, the cache hit rate and the system response speed are improved, and the method is suitable for a high-concurrency and low-delay AI application environment.

A memory device according to an embodiment is configured to perform a gather operation or a scatter operation. The memory device includes at least one memory bank, and the memory bank comprises: a cell array including a plurality of DRAM memory cells; an offset buffer in which read target addresses or write target addresses transmitted from a host are stored; a data buffer in which read data read from the cell array according to the read target addresses or write data to be stored at the write target addresses are stored; and a controller configured to execute a read command or a write command for the cell array when a number of read target addresses or a number of write target addresses in the offset buffer corresponds to a threshold.

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.

The present disclosure relates to an information detection method and device, electronic equipment and computer readable storage medium, and belongs to the technical field of semiconductor production and manufacturing, and can be applied to the scene of detecting the authenticity of SPD information in a DRAM memory bank. The method comprises: obtaining a to-be-detected memory, and determining a memory parameter corresponding to the to-be-detected memory; the memory parameter is obtained based on at least one of an operation code and a test vector; obtaining a chip record parameter from a detection chip corresponding to the to-be-detected memory; comparing the memory parameter and the chip record parameter for consistency to obtain a comparison result, so as to determine the authenticity of the chip record parameter according to the comparison result. The present disclosure can detect whether the SPD information in the DRAM memory bank is real.

The invention relates to a pixel structure, a driving method of the pixel structure, a display device and a control method of the display device. The pixel structure comprises a storage unit which comprises a 2T0C-DRAM (Dynamic Random Access Memory), and the 2T0C-DRAM is used for storing gray data of a pixel frame; the signal generation unit is electrically connected with the storage unit and is used for generating a PWM control signal according to the gray scale data and a clock signal; the display unit comprises a light emitting diode and a driving transistor connected with the light emitting diode in series, and the signal generation unit is electrically connected with a driving grid electrode of the driving transistor so as to adjust light emitting parameters of the light emitting diode through the PWM control signal. According to the invention, ultrahigh pixel density can be realized, the display resolution is improved, the requirement of near-to-eye display for high PPI (gt, 5000 PPI) is met, and the liquid crystal display panel is completely compatible with a TFT substrate process of a Micro-LED display panel, so that the production cost is reduced, and the product yield is improved.

Instead of allocating unused resources, offload work from the host, and move to just-in-time, low capacity DRAM memory allocation. The host does a read and receives the location of the data in the response. This will offload the host from managing physical region page (PRP) lists. The data storage device counts the number of bytes that have been read by the host (per flash memory unit (FMU)), and the data storage device can release the buffer as soon as all the data has been read. The data storage device knows automatically when a buffer should be allocated / de-allocated just-in-time.

The application discloses a kind of DRAM memory grain test method, equipment and medium, it is related to storage reliability detection technical field, including: the array structure parameter of the DRAM memory grain to be measured is collected, and array structure parameter is carried out physical address mapping, generates test control sequence;Read-write verification is carried out to test control sequence, obtains exception log set, using space-time diagram evolution method, the error repeatedly appearing in exception log set is carried out time correlation analysis, generates time correlation sequence;Through failure coupling inference method, failure distribution set is combined with repeated trigger feature and is comprehensively judged, obtains grain health portrait, and according to grain health portrait executes directional verification test, constructs verification record data, and verification record data is merged and analyzed, generates fault determination scheme.The application improves complex failure behavior analysis capability and fault determination accuracy.

Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task. In response to determining that the performance capability is adequate, the controller changes a mode of operation of the memory system so that one or more resources of the second memory device are used to service the task.