29 results about "Memory access pattern" patented technology

A method for compiling a computational graph, and a related product. The method comprises: acquiring a computational graph to be compiled that is expressed by a second intermediate representation, performing forward inference of a shape, and on the basis of the forward inference and tensor data splitting information, obtaining complete shape information; using the complete shape information to determine whether the tensor data splitting information needs to be adjusted; on the basis of a determination result, determining the tensor data splitting information that meets requirements; on the basis of the tensor data splitting information that meets the requirements, performing memory access pattern derivation on operators in the computational graph; on the basis of a derived memory access pattern, determining address-domain-related parameters of instructions involved in loops in code logic of the computational graph; performing pipeline scheduling on the instructions in the loops; and on the basis of the address-domain-related parameters of the instructions involved in the loops and a pipeline scheduling result of the instructions, compiling the computational graph, so as to obtain a binary file recognizable by an intelligent processor.

The embodiment of the application discloses a kind of identification methods of pointer chasing memory access mode, the execution trajectory of binary instruction generated when target program runs is obtained by binary instrumentation, the execution trajectory of binary instruction is statically analyzed to obtain five-level consistency query result, address dependency relationship category and context stability category are obtained by dynamic analysis, on this basis, value flow causality verification is executed, address dependency relationship category, five-level consistency query result, value flow verification causality result and context stability category are successively combined to carry out multilevel determination, the final determination result of each binary instruction is generated, and whether the binary instruction is pointer chasing memory access mode is confirmed according to the final determination result, without source code, pointer chasing memory access mode can be accurately identified, and multi-level confidence determination is provided, which can be directly applied to commercial software, third-party library and legacy system etc. Source code unavailable scene.

The invention discloses a GPU dynamic memory resource management method and system based on time sequence historical analysis. According to the method, a CUDAAPI function during running of a deep learning model is intercepted, and an execution history table containing a kernel execution sequence, a memory block size and an address is generated. By comparing two latest execution history tables, calculating a consistency ratio to judge whether a memory access mode is stable or not, so that a memory prefetch strategy is started; and when the GPU memory is insufficient, the memory blocks are exchanged to the CPU memory based on an expelling strategy of reference counting, so that sufficient GPU memory can be available during kernel execution. The system comprises a memory extraction module, a prefetching module and a dynamic decision module, supports dynamic asynchronous memory exchange, and optimizes GPU memory utilization efficiency. The method is suitable for deep learning model training in a GPU memory resource limited environment, a larger-scale deep learning model and training batches can be supported on the GPU with the same configuration, memory waste is reduced, and operation performance is improved.

A system on chip includes an accelerator configured to generate a demand request for demand data corresponding to a neural network operation based on instructions received from a host processor, and to generate a prefetch request for prefetch data based on a memory access pattern predicted from the neural network operation; a memory controller configured to read the demand data from a memory based on the demand request, and read the prefetch data from the memory based on the prefetch request; and a system cache configured to store at least one of prefetch data and demand data read from the memory as read data, where the accelerator is configured to perform the neural network operation on the read data received from the system cache.

The invention provides a method for efficiently and parallelly generating a 10 billion-level unstructured grid at a ten-thousand-core level, which adopts an MPI parallel architecture to realize ten-thousand-core-level calculation, and averagely distributes calculation tasks to each process through a dynamic load balancing technology; a hierarchical communication and memory access mode is designed, grid data are stored in a plurality of process memories in a distributed mode, and limitation of a single-machine memory is effectively overcome; developing a self-adaptive interface matching algorithm, performing local reconstruction on an unmatched grid region, and ensuring that the requirement of local grid quality is met; global grid number reconstruction and boundary condition analysis algorithms are optimized, and a dynamic block hash table technology is adopted to efficiently process 10 billion-level grid matching. According to the method, the technical bottleneck of generation of the complex geometry 10 billion-scale unstructured grids is broken through, efficient generation of the 10 billion-scale unstructured grids is achieved on a domestic supercomputing platform, tests show that generation of 3 billion unit grids can be completed within several hours, and the speed is increased by more than one magnitude compared with a traditional method.

A processing device identifies a repeated memory access pattern in a memory access stream of a memory subsystem, the repeated memory access pattern having a memory access pattern frequency, and determines an accumulated value associated with the repeated memory access pattern. The processing device further determines whether the accumulated value satisfies a threshold criterion associated with the memory access pattern frequency, and responsive to determining that the accumulated value satisfies the threshold criterion, causes a delay period to be introduced to the memory access stream to break the repeated memory access pattern.

The application relates to an equivalent connection query method and device for a ciphertext database, which comprises the following steps: constructing indexes corresponding to a plurality of tables; wherein the indexes comprise encrypted inverted index tables, and the inverted index tables are generated from original tables; uploading the encrypted indexes and a multi-set Bloom filter to a server; wherein the multi-set Bloom filter is obtained according to all values of inserted connection attribute columns; sending an equivalent connection query request of a user to the server, so that the server returns corresponding equivalent connection query results to the user. Compared with the prior art, the multi-set Bloom filter has shorter solving time and higher efficiency, and can hide the relationship between sets in a table and a Bloom filter, thereby hiding external memory access modes, significantly improving the throughput of data processing, reducing the number of interactions with a trusted execution environment, and effectively solving the problem of large communication overhead.

The invention relates to a power embedded kernel micro-architecture optimization method for a low-carbon mobile terminal, and the method comprises the following steps: S1, obtaining multi-source energy consumption and scene data, carrying out the preprocessing, and obtaining a standardized time series data stream; s2, performing joint feature engineering and scene label generation based on the standardized time sequence data stream, and obtaining a feature vector matrix with a scene label; s3, performing short-term prediction on the load, the temperature, the energy consumption and the QoE based on a short-term prediction model according to the feature vector matrix with the scene label; s4, on the basis of prediction, solving an energy efficiency optimal control quantity meeting a preset constraint, and obtaining a resource scheduling decision and a system configuration parameter; and S5, based on the resource scheduling decision and the system configuration parameters, optimizing the memory access mode and the cache strategy based on the graph neural network, and obtaining a dynamic memory partitioning scheme, a cache replacement strategy and a prefetching decision. The energy consumption of the mobile terminal can be obviously reduced.

The invention discloses a dense matrix and sparse matrix efficient coupling parallel method. The method comprises the following steps: S1, carrying out feature analysis on an input dense matrix and sparse matrix; s2, carrying out adaptive partitioning on the dense matrix and the sparse matrix; s3, creating a uniform matrix descriptor for each matrix block; s4, constructing a calculation dependency graph; s5, executing parallel computing; according to the dense matrix and sparse matrix efficient coupling parallel method, through data rearrangement of self-adaptive hybrid storage and cache perception, the cache hit rate is greatly increased, the bottleneck of memory access mode conflicts in hybrid calculation is overcome, and meanwhile, based on an accurate prediction model and dynamic scheduling, the performance data in the running process are collected. The method has the advantages that combined optimization of computing load and communication is achieved, high load balance and resource utilization rate under large-scale parallel are guaranteed, redundant format conversion overhead is almost eliminated by the aid of unified descriptors and inert conversion strategies, a computing pipeline is smoother, and overall performance is improved remarkably.

Various examples are provided related to cache miss classification. In one example, a method for classification of cache misses includes detecting a susceptible instruction of a program with frequent cache misses based upon performance monitoring units (PMU) based coarse grain sampling; collecting a memory access pattern of the susceptible instruction using breakpoint-based fine-grain sampling; and classifying a type of cache miss associated with the susceptible instruction. The type of cache miss can be classified as a capacity miss, a conflict miss, or a coherence miss using the memory access pattern of the susceptible instruction.

The invention discloses a processor performance test method, device and equipment and a storage medium, and relates to the technical field of performance test.The processor performance test method comprises the steps that a performance test program is compiled into a machine instruction, the machine instruction is divided into a plurality of instruction blocks, and all the instruction blocks are marked according to target labels; the target label comprises an instruction type and a memory access mode; the instruction type comprises a floating point calculation type and an integer calculation type; obtaining performance data of each kernel when the processor executes the task; the performance data comprises a core utilization rate, a cache hit rate, memory delay and inter-core communication delay; distributing the instruction block to a target kernel of the processor based on the target label and the performance data, so that the target kernel executes the instruction block to obtain corresponding test data; and recording the test data, and determining a performance test result of the processor according to the test data. Therefore, the effectiveness of the performance test can be improved.

The invention relates to the technical field of computer compilation, in particular to an automatic vector sliding instruction generation device and method.The sliding mode detection module is used for conducting memory access mode analysis on a loop body in a source code and recognizing a sliding window access mode of continuous offset; the sliding vectorization generation module is used for generating a vector sliding operation node according to the output of the sliding mode detection module; the intermediate representation extension module is used for displaying the inserted vector sliding operation node in the intermediate representation of the compiler; the rear-end mode matching module is used for matching a specific vector sliding machine instruction of a target platform RISC-V according to the sliding operation semantics represented by the vector sliding operation node; and the assembly generation and optimization module is used for generating a final machine instruction sequence and optimizing the instruction sequence containing the vector sliding machine instruction. According to the method, the sliding window access mode in the scalar code can be automatically identified, and the RISC-V vector sliding instruction is generated, so that the memory access and instruction overhead is remarkably reduced.

The application relates to a memory test method and device, electronic equipment and a storage medium. The method comprises the following steps: in response to a memory test request, extracting a target service scenario corresponding to a memory module in a to-be-tested device from the memory test request; determining a test environment description parameter according to the target service scenario, wherein the test environment description parameter represents a target memory access mode and load pressure condition corresponding to the memory module; and obtaining a first memory test result of the memory module in a test environment corresponding to the test environment description parameter. The application improves the pertinence of memory testing and the accuracy of memory test results. The embodiments of the application can be applied to various scenes such as cloud technology, artificial intelligence, intelligent transportation and intelligent entertainment.

A computer system implements a unified framework integrating an adaptive elastic funnel (AEF) with a convergent intelligence fabric (CIF) for multi-agent AI collaboration. The system provides a multi-layer key-value subsystem for sharing computations across GPU partitions, applying hybrid placement strategies for dynamic memory management. It unifies physical GPU sub-allocation and virtual GPU time-slicing through a common abstraction layer while maintaining isolation through policy-based multi-tenancy. A predictive resource orchestration system forecasts computational needs, while speculative data scheduling proactively manages memory access patterns. The architecture includes risk-based scheduling for uncertain workloads, test-time compute scaling, and federated learning for edge collaboration. This framework delivers computational efficiency, security, and adaptive intelligence in high-dimensional environments while supporting incremental adoption through modular interfaces.

A static random-access memory (SRAM) device with enhanced flexibility and power efficiency includes two memory cores with different bit widths and a control section that receives a partial word signal. This signal allows independent control of each memory core, enabling or disabling them selectively. The SRAM device further includes a decoder circuit and multiple word line drivers, which can be independently enabled or disabled for each memory core based on the partial word signal. The word line drivers are organized into two sets, each coupled to the word lines of a respective memory core. Power control circuits selectively provide power to each set of drivers according to the partial word signal. This architecture allows for more granular control over memory access and power consumption, potentially improving the device's overall efficiency and performance in applications requiring variable memory access patterns.

This application relates to the field of computer technology and discloses a resource optimization and scheduling device for a distributed computer system, including a signal acquisition module, a feature calculation module, a resource control module, and a task scheduling module. The signal acquisition module reads memory bandwidth consumption data and generates a digital signal sequence; the feature calculation module converts the sequence into a frequency domain signal and calculates a high-frequency energy ratio index; the resource control module performs static configuration and dynamic gating based on this index, adjusting the number of cache paths and bandwidth threshold in the static logic, and triggering a hardware time-division gating mechanism when the bus is saturated to generate a pulse-width modulation signal to switch the high-bandwidth priority of the task; the task scheduling module calculates an orthogonal cost score based on the frequency domain features to select deployment nodes. This invention effectively identifies memory access patterns and avoids bus conflicts through frequency domain analysis and hardware time-division gating, solving the resource contention problem at the microarchitecture level.

A system comprises an array of reconfigurable units including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs), and a compiler configured to receive a tensor including a plurality of memory access patterns of a first type (read) and a second type (write) located in a logical memory of the compiler. Each memory access pattern includes a memory access particular to that type. The compiler is configured to create a plurality of duplicates of the tensor and assign one or more contexts of any type to the duplicate tensors, such that no two contexts of the same type are in the same duplicate tensor.

The invention relates to an embedded virtualized memory dynamic allocation method and system, and belongs to the field of embedded systems. According to the method, the access characteristic parameters of the first type of memory region and the second type of memory region are clearly distinguished by collecting the hardware topology information of the physical memory, the partitions are divided based on the access characteristic consistency principle, it is ensured that the performance characteristics of each partition are stable and controllable, the virtual machine can use memory resources matched with the self requirement according to the requirement, and the user experience is improved. The memory access mode of the virtual machine is monitored in real time, the performance demand features of the virtual machine are quantitatively analyzed in combination with a feature extraction algorithm, the matched target partition is dynamically selected, and the problem of stiffness of static distribution is solved through a dynamic adaptation mechanism. The method ensures that the actual access performance of the virtual machine is consistent with the partition characteristics.

This invention discloses a data prefetching method, product, device, and medium based on multiple memory access patterns, relating to the field of computer architecture technology. The method includes: monitoring for L2 cache memory access miss events in the processor; if the miss status register hits the event, splitting the miss address to obtain the base address of the spatial region and the offset address within the region. When the program counter pattern training table hits the base address, stride and spatiotemporal pattern training is performed on the offset address to obtain a fixed stride, space / time related access pattern. Valid memory access patterns are filtered by confidence level and stored in the corresponding LLC pattern table, with an index recorded in the prefetch pattern record table. Subsequently, based on the memory access miss event and index information, the target pattern is read from the corresponding pattern table to calculate the prefetch address, generate a request, and execute the prefetch. Through this scheme, it is possible to adapt to multiple scenarios and accurately identify memory access patterns for more precise data prefetching.

The invention discloses a hardware accelerator used for efficient vector retrieval and an efficient vector retrieval method and device, and belongs to the field of data retrieval, a vector calculation unit arranged in the hardware accelerator can realize parallel multi-vector operation, and a matrix calculation unit improves the efficiency of vector calculation and improves the efficiency of vector retrieval. And the graph data cache unit effectively solves the problem that the calculation unit is idle in the execution process of the ANNS algorithm, and the resource utilization rate is remarkably improved. Furthermore, in an efficient vector retrieval method proposed on the basis of the hardware accelerator, through a high-reachability neighbor graph construction technology, including neighbor graph generation, reverse graph edge fusion and edge rearrangement and screening based on the number of unfavorable paths, a graph structure with strong connectivity and controllable out-degree can be formed, dynamic memory allocation is reduced, and the probability of data transmission is lowered. The memory access mode is more regular and predictable, and the intelligent switching and load balancing of the computing units in the hardware accelerator are combined, so that the resource utilization is optimized, and the more uniform computing load is realized.

This disclosure describes systems, methods, and devices related to enhanced memory integration. The device may include a compute chiplet configured as a System-on-a-Chip (SoC). The device may include a logic die circuitry coupled to the compute chiplet through a high-speed link. The device may include a memory interface that connects the logic die circuitry to on-package memory. The device may include control circuitry within the logic die circuitry configured to treat the on-package memory as a memory-side cache for an off-package memory. The device may dynamically migrate memory pages between the on-package memory and the off-package memory based on memory access patterns. The device may facilitate efficient data management, optimize memory utilization, and support scalable memory architectures for improved performance.

This application provides a data packet processing method and apparatus. The method serializes the business data to be sent into a data packet format including different segment groups, so that different fields are stored in different segment groups and fields with the same calculation purpose are stored in the same segment group, thereby physically isolating fields of data with different calculation purposes. In each segment group, according to the position of the field in the column group in the metadata block structure, the field value is written to the corresponding position in the data block corresponding to the column group, so that the storage position of the field value in the data block is consistent with the position of the field in the column group in the metadata block structure. This highly matches the memory access mode of the aggregation calculation of the receiving end, so that the receiving end device does not need to perform time-consuming deserialization and data cleaning, and can accurately locate the target segment group used for data packet processing from the data packet as needed, reducing unnecessary CPU overhead, memory occupation and data copying.

The embodiment of the invention discloses a method for determining a memory access mode and an NTT / INTT accelerator based on an FPGA. The method comprises the steps that a storage array used for storing numerical points is determined according to the point number N of the numerical points to be subjected to NTT / INTT operation and a basic cardinal number R, the storage array is composed of R storage units, and each storage unit comprises D addresses; executing the target operation so as to fill different basic numerical values into the two-dimensional array; a first index of the two-dimensional array corresponds to a stage of NTT / INTT operation, and a second index corresponds to the address. Filling each position of a target array corresponding to the storage array structure with a first value and a second value, wherein the second value is obtained by expanding a basic value of an associated position in the two-dimensional array; the filled target array is used for indicating the access mode of the storage array, and the access mode comprises the step that in the stage indicated by the first value, any address is read in the round indicated by the second value at the corresponding position. In this way, RAW conflicts can be eliminated, and reading and writing of the memory space can be balanced.

Described herein is a computer memory system comprising a plurality of memory banks or other memory structures and circuitry configured to implement a hash function that produces output values that evenly distribute strided memory accesses across the plurality of memory structures. The memory banks can be cache memory banks that may include a plurality of cache lines, cache sets, or cache ways. The memory banks can also be DRAM memory banks accessed through different memory channels. The hash function facilitates the even distribution across memory structures in the face of a plurality of different strided memory access patterns.

The application provides a method for generating a hundred billion non-structured grid by a million-core high-efficiency parallel method, which realizes million-core calculation by using MPI parallel architecture, distributes the calculation task to each process by dynamic load balancing technology, designs layered communication and memory access mode, and stores the grid data in the memory of multiple processes in a distributed manner, so as to effectively overcome the limitation of single machine memory; develops a self-adaptive interface matching algorithm, locally reconstructs the non-matching grid area, and ensures that the local grid quality requirement is met; optimizes the global grid number reconstruction and boundary condition analysis algorithm, and efficiently processes the hundred billion grid matching by using dynamic block hash table technology. The application breaks through the technical bottleneck of generating a hundred billion non-structured grid of a complex geometric body, realizes the efficient generation of a hundred billion non-structured grid on a domestic supercomputing platform, and tests show that the generation of 30 billion units of grid can be completed within a few hours, which is more than one order of magnitude faster than the traditional method.

The invention provides a memory management method and system. The memory management method comprises the following steps: integrating at least two of a dynamic random access memory (DRAM), a persistent memory (PMEM) and a solid state disk (SSD) according to a CXL protocol to construct and generate a memory resource pool with different performance levels; receiving a memory resource request of the Pod through an expanded Kubernetes scheduler, and allocating memory resources crossing a plurality of performance levels for the Pod according to the memory resource request and each level state of a memory resource pool; and dynamically deploying the distribution of the Pod memory data among different performance levels of the memory resource pool based on the monitoring of the memory access mode in the Pod running process.

The invention discloses a block chain edge computing scene-oriented post-quantum signature method based on NTT optimization, and relates to the technical field of block chains, and the post-quantum signature method is characterized in that on the basis of a lattice-based post-quantum signature algorithm, a three-level NTT optimization strategy is designed for edge node resource constraints, and the edge node resource constraints are optimized; the method specifically comprises the following steps of: initializing inertia NTT based on sparse polynomial pre-calculation; a stacked incomplete NTT step in a signature generation loop; and a rapid Barrett reduction and memory access optimization step under a fixed modulus. According to the method, repeated transformation of a matrix A is eliminated through inert initialization, the number of butterfly operations is reduced through stacked incomplete NTT, modular operation overhead is reduced through rapid Barrett reduction, signature generation is integrally accelerated, the requirement for real-time calculation is reduced through sparse pre-calculation, the CPU cache pressure is reduced through a memory access mode, and the real-time calculation efficiency is improved. Therefore, the overall memory bandwidth requirement of the system during the signature period is reduced, the method is more suitable for a low-end edge SOC, and the endurance time of battery-powered edge equipment is prolonged.

The application provides a computing device and method for an image pixel processing network, the device comprising an external storage, a bus controller, an address controller, an input buffer, a weight buffer, a bias buffer, an output buffer, and q block computing units. The application proposes a novel hardware architecture which can convert various convolutions into specific deformable convolutions for calculation to flexibly support multiple types of convolution layers. The application also designs corresponding computing units and a brand-new decoupled computing process to unify diverse memory access modes and ensure the consistency of input / output layout formats.