55 results about "Memory access pattern" patented technology

The invention discloses a matrix calculation adaptive optimization method and system based on an ARM architecture. The method comprises the following steps: preprocessing to-be-processed matrix data; performing local activeness calculation and hot spot region identification on the preprocessed matrix data, and determining long-tail distribution characteristics of the matrix; calculating the optimal block size range of the matrix based on the long tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the processor information, and generating an asymmetric block scheme; based on an asymmetric partitioning scheme, establishing a mapping relation between matrix features and optimal partitioning parameters; calculating the calculation density and the memory access mode of each block based on the asymmetric block scheme and the mapping relation, and generating a task scheduling scheme; based on the task scheduling scheme, matrix calculation is executed on the processor, and a final calculation result is output. According to the method, self-adaptive blocking and heterogeneous core scheduling are realized by identifying the long tail distribution characteristics of the matrix, and the performance and energy efficiency of matrix calculation on ARM are improved.

Methods and apparatus for application aware memory patrol scrubbing techniques. The method may be performed on a computing system including one or more memory devices and running multiple applications with associated processes. The computer system may be implemented in a multi-tenant environment, where virtual instances of physical resources provided by the system are allocated to separate tenants, such as through virtualization schemes employing virtual machines or containers. Quality of Service (QoS) scrubbing logic and novel interfaces are provided to enable memory scrubbing QoS policies to be applied at the tenant, application, and / or process level. This QoS policies may include memory ranges for which specific policies are applied, as well as bandwidth allocations for performing scrubbing operations. A pattern generator is also provided for generating scrubbing patterns based on observed or predicted memory access patterns and / or predefined patterns.

The invention discloses a memory access method and device, a storage medium and a program product, and relates to the technical field of memory access, comprising: monitoring memory access information of a target memory; the memory access information comprises a missing page address sequence during memory access, an address distribution characteristic when an address conversion failure event occurs in an address conversion lookaside buffer, a cross-node access event and a virtual memory access frequency; determining corresponding target feature information; the target feature information comprises spatial locality, thermal density, access dispersion and unbalance degree data; and determining a current memory access mode based on the target feature information, and determining a target access strategy from preset memory access strategies configured with different memory page table prefetching rules to access the memory. The memory access feature information is quantified through the memory access information, the corresponding memory access mode is determined, and the corresponding memory page table prefetching rule is executed, so that the traversal delay of the multi-level page table can be reduced, and the memory access performance is improved by fully utilizing the memory bandwidth.

The invention provides an examination answer code similarity intelligent comparison and analysis method and system, and relates to the technical field of educational informationization, and the method comprises the steps: adaptively determining an optimal instrumentation position, collecting an execution path sequence and a memory access mode, and constructing a dynamic behavior feature vector; extracting static structure features and fusing the static structure features with the dynamic features; constructing a similarity measurement model by adopting a feature coding network and an adversarial discrimination network comprising three sub-networks; constructing a multi-level adversarial sample library based on a heuristic rule for adversarial training; and finally identifying and positioning the suspected plagiarism code snippets. According to the method, various plagiarism deformation strategies can be effectively identified, and the accuracy of code plagiarism detection is improved.

The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input / output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

A method for compiling a computational graph, and a related product. The method comprises: acquiring a computational graph to be compiled that is expressed by a second intermediate representation, performing forward inference of a shape, and on the basis of the forward inference and tensor data splitting information, obtaining complete shape information; using the complete shape information to determine whether the tensor data splitting information needs to be adjusted; on the basis of a determination result, determining the tensor data splitting information that meets requirements; on the basis of the tensor data splitting information that meets the requirements, performing memory access pattern derivation on operators in the computational graph; on the basis of a derived memory access pattern, determining address-domain-related parameters of instructions involved in loops in code logic of the computational graph; performing pipeline scheduling on the instructions in the loops; and on the basis of the address-domain-related parameters of the instructions involved in the loops and a pipeline scheduling result of the instructions, compiling the computational graph, so as to obtain a binary file recognizable by an intelligent processor.

The embodiment of the application discloses a kind of identification methods of pointer chasing memory access mode, the execution trajectory of binary instruction generated when target program runs is obtained by binary instrumentation, the execution trajectory of binary instruction is statically analyzed to obtain five-level consistency query result, address dependency relationship category and context stability category are obtained by dynamic analysis, on this basis, value flow causality verification is executed, address dependency relationship category, five-level consistency query result, value flow verification causality result and context stability category are successively combined to carry out multilevel determination, the final determination result of each binary instruction is generated, and whether the binary instruction is pointer chasing memory access mode is confirmed according to the final determination result, without source code, pointer chasing memory access mode can be accurately identified, and multi-level confidence determination is provided, which can be directly applied to commercial software, third-party library and legacy system etc. Source code unavailable scene.

The invention discloses a GPU dynamic memory resource management method and system based on time sequence historical analysis. According to the method, a CUDAAPI function during running of a deep learning model is intercepted, and an execution history table containing a kernel execution sequence, a memory block size and an address is generated. By comparing two latest execution history tables, calculating a consistency ratio to judge whether a memory access mode is stable or not, so that a memory prefetch strategy is started; and when the GPU memory is insufficient, the memory blocks are exchanged to the CPU memory based on an expelling strategy of reference counting, so that sufficient GPU memory can be available during kernel execution. The system comprises a memory extraction module, a prefetching module and a dynamic decision module, supports dynamic asynchronous memory exchange, and optimizes GPU memory utilization efficiency. The method is suitable for deep learning model training in a GPU memory resource limited environment, a larger-scale deep learning model and training batches can be supported on the GPU with the same configuration, memory waste is reduced, and operation performance is improved.

A system on chip includes an accelerator configured to generate a demand request for demand data corresponding to a neural network operation based on instructions received from a host processor, and to generate a prefetch request for prefetch data based on a memory access pattern predicted from the neural network operation; a memory controller configured to read the demand data from a memory based on the demand request, and read the prefetch data from the memory based on the prefetch request; and a system cache configured to store at least one of prefetch data and demand data read from the memory as read data, where the accelerator is configured to perform the neural network operation on the read data received from the system cache.

The invention relates to the technical field of remote identity authentication, in particular to a computer remote login recognition system. According to the invention, in the remote login interaction, the probability distribution of the packet size can be obtained through the statistical analysis of the packet data, and the abnormal traffic is detected through the comparison of historical data, so that the potential risk caused by large-scale data transmission or traffic mutation is prevented. By calculating the divergence value of the packet size distribution, the abnormal degree of the packet behavior can be accurately identified, and the rationality of the packet interaction mode is ensured. In combination with the analysis of the memory paging access sequence, the memory access mode is divided through the time window, and the influence of the background process is eliminated, so that the detection of the memory access abnormality is more accurate. Through application of a density distribution calculation method, environment abnormity judgment is not limited to a single data point, and the recognition capacity for process behavior mutation and remote control intervention is enhanced by combining access density changes of adjacent time windows.

The invention provides a method for efficiently and parallelly generating a 10 billion-level unstructured grid at a ten-thousand-core level, which adopts an MPI parallel architecture to realize ten-thousand-core-level calculation, and averagely distributes calculation tasks to each process through a dynamic load balancing technology; a hierarchical communication and memory access mode is designed, grid data are stored in a plurality of process memories in a distributed mode, and limitation of a single-machine memory is effectively overcome; developing a self-adaptive interface matching algorithm, performing local reconstruction on an unmatched grid region, and ensuring that the requirement of local grid quality is met; global grid number reconstruction and boundary condition analysis algorithms are optimized, and a dynamic block hash table technology is adopted to efficiently process 10 billion-level grid matching. According to the method, the technical bottleneck of generation of the complex geometry 10 billion-scale unstructured grids is broken through, efficient generation of the 10 billion-scale unstructured grids is achieved on a domestic supercomputing platform, tests show that generation of 3 billion unit grids can be completed within several hours, and the speed is increased by more than one magnitude compared with a traditional method.

The invention relates to the field of algorithms, in particular to a Viterbi algorithm searching method and device, a medium and a program product, and the method comprises the steps: respectively calculating the cost from each state at an n moment to a state 1 at an (n + 1) moment, and obtaining an optimal preorder state; calculating the cost from the state 1 at the n moment to the state 2 to k at the n + 1 moment; respectively calculating the cost from the state 2 at the n moment to the state 2 at the k to the n + 1 moment to obtain an optimal preorder state; respectively calculating the cost from the state 2 at the n moment to the state 3 at the n + 1 moment to the k; and so on, the optimal preorder state of all the states at the n + 1 moment is found. According to the search method, the number of times of search calculation is not increased, but the memory access mode and the cache efficiency are greatly improved, and an experimental structure shows that the calculation time of a new search order is reduced by 30%.

A processing device identifies a repeated memory access pattern in a memory access stream of a memory subsystem, the repeated memory access pattern having a memory access pattern frequency, and determines an accumulated value associated with the repeated memory access pattern. The processing device further determines whether the accumulated value satisfies a threshold criterion associated with the memory access pattern frequency, and responsive to determining that the accumulated value satisfies the threshold criterion, causes a delay period to be introduced to the memory access stream to break the repeated memory access pattern.

The application relates to an equivalent connection query method and device for a ciphertext database, which comprises the following steps: constructing indexes corresponding to a plurality of tables; wherein the indexes comprise encrypted inverted index tables, and the inverted index tables are generated from original tables; uploading the encrypted indexes and a multi-set Bloom filter to a server; wherein the multi-set Bloom filter is obtained according to all values of inserted connection attribute columns; sending an equivalent connection query request of a user to the server, so that the server returns corresponding equivalent connection query results to the user. Compared with the prior art, the multi-set Bloom filter has shorter solving time and higher efficiency, and can hide the relationship between sets in a table and a Bloom filter, thereby hiding external memory access modes, significantly improving the throughput of data processing, reducing the number of interactions with a trusted execution environment, and effectively solving the problem of large communication overhead.

A system comprises an array of reconfigurable units including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs), and a compiler configured to receive a tensor including a plurality of memory access patterns of a first type (read) and a second type (write) located in a logical memory of the compiler. Each memory access pattern includes a memory access particular to that type. The compiler is configured to create a plurality of duplicates of the tensor and assign one or more contexts of any type to the duplicate tensors, such that no two contexts of the same type are in the same duplicate tensor. The compiler is configured to trim the duplicate tensors to retain portions including its corresponding assigned contexts remove portions that are inconsequential to the assigned contexts and dispatch the assigned contexts from each duplicate tensor to one or more PMUs.

The invention relates to a power embedded kernel micro-architecture optimization method for a low-carbon mobile terminal, and the method comprises the following steps: S1, obtaining multi-source energy consumption and scene data, carrying out the preprocessing, and obtaining a standardized time series data stream; s2, performing joint feature engineering and scene label generation based on the standardized time sequence data stream, and obtaining a feature vector matrix with a scene label; s3, performing short-term prediction on the load, the temperature, the energy consumption and the QoE based on a short-term prediction model according to the feature vector matrix with the scene label; s4, on the basis of prediction, solving an energy efficiency optimal control quantity meeting a preset constraint, and obtaining a resource scheduling decision and a system configuration parameter; and S5, based on the resource scheduling decision and the system configuration parameters, optimizing the memory access mode and the cache strategy based on the graph neural network, and obtaining a dynamic memory partitioning scheme, a cache replacement strategy and a prefetching decision. The energy consumption of the mobile terminal can be obviously reduced.

Detailed herein are embodiments utilizing a cryptographically authenticated address bus (CAAB) protection that uses an intelligent memory design to prevent attacks on the address bus without detection and eliminate the memory bus as an observability surface for an attacker to do access pattern analysis. Embodiments detailed herein describe an intelligent memory module which has cryptographic capabilities. In some embodiments, a memory controller and an intelligent memory module exchange a key and using this key, the address (on the address bus) is encrypted and integrity protected using authenticated counter mode encryption. The memory controller on receiving a read or a write request encrypts the address (e.g., using pre-generated encrypted counters to minimize cryptographic overheads). A message authentication code (MAC) also gets generated along with the encrypted address to be able to detect modification to the encrypted address.

The invention discloses a dense matrix and sparse matrix efficient coupling parallel method. The method comprises the following steps: S1, carrying out feature analysis on an input dense matrix and sparse matrix; s2, carrying out adaptive partitioning on the dense matrix and the sparse matrix; s3, creating a uniform matrix descriptor for each matrix block; s4, constructing a calculation dependency graph; s5, executing parallel computing; according to the dense matrix and sparse matrix efficient coupling parallel method, through data rearrangement of self-adaptive hybrid storage and cache perception, the cache hit rate is greatly increased, the bottleneck of memory access mode conflicts in hybrid calculation is overcome, and meanwhile, based on an accurate prediction model and dynamic scheduling, the performance data in the running process are collected. The method has the advantages that combined optimization of computing load and communication is achieved, high load balance and resource utilization rate under large-scale parallel are guaranteed, redundant format conversion overhead is almost eliminated by the aid of unified descriptors and inert conversion strategies, a computing pipeline is smoother, and overall performance is improved remarkably.

The invention provides a memory access mode recognition device and method based on hardware implementation, and the device comprises a plurality of parallel memory access mode recognition units, each memory access mode recognition unit is implemented through independent state machine logic, and is configured to dynamically adjust a confidence value according to a memory access trace of an application program, and recognize a memory access mode of a specific type; the plurality of data storage units are connected with the plurality of memory access mode identification units, and part of the memory access mode identification units share the same data storage unit; the confidence counters are used for recording confidence values of the memory access modes by using the program counters as indexes; the control unit is used for coordinating the working time sequence of the memory access mode recognition unit, the data storage unit and the confidence counter; the memory access mode recognition unit, the data storage unit, the confidence counter and the control unit are all realized through the hardware RTL, the memory access mode recognition efficiency is remarkably improved, and hardware resource occupation is reduced.

Various examples are provided related to cache miss classification. In one example, a method for classification of cache misses includes detecting a susceptible instruction of a program with frequent cache misses based upon performance monitoring units (PMU) based coarse grain sampling; collecting a memory access pattern of the susceptible instruction using breakpoint-based fine-grain sampling; and classifying a type of cache miss associated with the susceptible instruction. The type of cache miss can be classified as a capacity miss, a conflict miss, or a coherence miss using the memory access pattern of the susceptible instruction.

The invention discloses a processor performance test method, device and equipment and a storage medium, and relates to the technical field of performance test.The processor performance test method comprises the steps that a performance test program is compiled into a machine instruction, the machine instruction is divided into a plurality of instruction blocks, and all the instruction blocks are marked according to target labels; the target label comprises an instruction type and a memory access mode; the instruction type comprises a floating point calculation type and an integer calculation type; obtaining performance data of each kernel when the processor executes the task; the performance data comprises a core utilization rate, a cache hit rate, memory delay and inter-core communication delay; distributing the instruction block to a target kernel of the processor based on the target label and the performance data, so that the target kernel executes the instruction block to obtain corresponding test data; and recording the test data, and determining a performance test result of the processor according to the test data. Therefore, the effectiveness of the performance test can be improved.

The invention provides a reasoning acceleration method and device applied to edge equipment and electronic equipment. The method comprises the following steps: dividing a weight matrix of a pre-training model into N weight sub-blocks, dividing an activation matrix of the pre-training model into M activation sub-blocks, and quantifying the weight sub-blocks in the pre-training model and the activation sub-blocks corresponding to the weight sub-blocks to obtain a target model; and if the quantization bit widths of the at least two weight sub-blocks are the same, performing quantization processing on the at least two weight sub-blocks as a whole based on the weight value quantization super-parameters corresponding to the at least two weight sub-blocks and the activation value quantization super-parameters corresponding to the activation sub-blocks corresponding to the weight sub-blocks. Weight sub-blocks with the same quantization bit width and corresponding activation sub-blocks are integrally processed, when the sub-blocks are loaded, a memory access mode is converted from random hopping to sequential reading and writing, weight values and activation values are quantized at the same time, the reasoning speed of the model is increased, and the storage space occupied by the model is reduced.

The invention relates to the technical field of computer compilation, in particular to an automatic vector sliding instruction generation device and method.The sliding mode detection module is used for conducting memory access mode analysis on a loop body in a source code and recognizing a sliding window access mode of continuous offset; the sliding vectorization generation module is used for generating a vector sliding operation node according to the output of the sliding mode detection module; the intermediate representation extension module is used for displaying the inserted vector sliding operation node in the intermediate representation of the compiler; the rear-end mode matching module is used for matching a specific vector sliding machine instruction of a target platform RISC-V according to the sliding operation semantics represented by the vector sliding operation node; and the assembly generation and optimization module is used for generating a final machine instruction sequence and optimizing the instruction sequence containing the vector sliding machine instruction. According to the method, the sliding window access mode in the scalar code can be automatically identified, and the RISC-V vector sliding instruction is generated, so that the memory access and instruction overhead is remarkably reduced.

The application relates to a memory test method and device, electronic equipment and a storage medium. The method comprises the following steps: in response to a memory test request, extracting a target service scenario corresponding to a memory module in a to-be-tested device from the memory test request; determining a test environment description parameter according to the target service scenario, wherein the test environment description parameter represents a target memory access mode and load pressure condition corresponding to the memory module; and obtaining a first memory test result of the memory module in a test environment corresponding to the test environment description parameter. The application improves the pertinence of memory testing and the accuracy of memory test results. The embodiments of the application can be applied to various scenes such as cloud technology, artificial intelligence, intelligent transportation and intelligent entertainment.

A computer system implements a unified framework integrating an adaptive elastic funnel (AEF) with a convergent intelligence fabric (CIF) for multi-agent AI collaboration. The system provides a multi-layer key-value subsystem for sharing computations across GPU partitions, applying hybrid placement strategies for dynamic memory management. It unifies physical GPU sub-allocation and virtual GPU time-slicing through a common abstraction layer while maintaining isolation through policy-based multi-tenancy. A predictive resource orchestration system forecasts computational needs, while speculative data scheduling proactively manages memory access patterns. The architecture includes risk-based scheduling for uncertain workloads, test-time compute scaling, and federated learning for edge collaboration. This framework delivers computational efficiency, security, and adaptive intelligence in high-dimensional environments while supporting incremental adoption through modular interfaces.

A static random-access memory (SRAM) device with enhanced flexibility and power efficiency includes two memory cores with different bit widths and a control section that receives a partial word signal. This signal allows independent control of each memory core, enabling or disabling them selectively. The SRAM device further includes a decoder circuit and multiple word line drivers, which can be independently enabled or disabled for each memory core based on the partial word signal. The word line drivers are organized into two sets, each coupled to the word lines of a respective memory core. Power control circuits selectively provide power to each set of drivers according to the partial word signal. This architecture allows for more granular control over memory access and power consumption, potentially improving the device's overall efficiency and performance in applications requiring variable memory access patterns.

This application relates to the field of computer technology and discloses a resource optimization and scheduling device for a distributed computer system, including a signal acquisition module, a feature calculation module, a resource control module, and a task scheduling module. The signal acquisition module reads memory bandwidth consumption data and generates a digital signal sequence; the feature calculation module converts the sequence into a frequency domain signal and calculates a high-frequency energy ratio index; the resource control module performs static configuration and dynamic gating based on this index, adjusting the number of cache paths and bandwidth threshold in the static logic, and triggering a hardware time-division gating mechanism when the bus is saturated to generate a pulse-width modulation signal to switch the high-bandwidth priority of the task; the task scheduling module calculates an orthogonal cost score based on the frequency domain features to select deployment nodes. This invention effectively identifies memory access patterns and avoids bus conflicts through frequency domain analysis and hardware time-division gating, solving the resource contention problem at the microarchitecture level.

A system comprises an array of reconfigurable units including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs), and a compiler configured to receive a tensor including a plurality of memory access patterns of a first type (read) and a second type (write) located in a logical memory of the compiler. Each memory access pattern includes a memory access particular to that type. The compiler is configured to create a plurality of duplicates of the tensor and assign one or more contexts of any type to the duplicate tensors, such that no two contexts of the same type are in the same duplicate tensor.

The present invention discloses a data-oriented particle system task design and scheduling method and device, including: creating a particle system prototype for each particle system, which includes a data area and a task area. The data area declares the attributes represented by the particles as components, and the task area declares all the tasks executed by the particle system. Moreover, the tasks in the task area have an execution sequence relationship, and each task operates on at least one component; after performing dependency parsing on the tasks in different task stages in each task area and generating a directed acyclic task dependency graph, it is added to multiple global task blocks divided by task stages. The task dependency graphs within each global task block are merged into a unique directed acyclic dependency graph; after merging the unique directed acyclic dependency graphs of all global task blocks and mapping them to the GPU computing task manager, highly optimized parallel scheduling execution is achieved on the GPU, thereby optimizing the memory access pattern, improving the cache utilization rate, and further enhancing the computing efficiency of the particle system.