541 results about "Deadlock" patented technology

The invention provides a multi-transaction deadlock detection and processing method in resource-constrained equipment, which comprises the following steps of: in a transaction execution process, constructing a resource waiting graph which is used for recording a waiting relationship among transactions so as to reflect the occupation condition of shared resources by the transactions and a dependency relationship among the transactions; before a transaction is subjected to read-write operation each time, whether execution of the current transaction can cause a deadlock risk or not is judged in real time by detecting a dependency relationship between the current transaction and a target resource and combining a resource waiting graph; and when a deadlock risk is detected, deadlock avoidance strategies of priority processing, transaction rollback, transaction retry and exception processing are adopted to avoid deadlock. The deadlock problem occurring in the transaction parallel processing process can be effectively avoided or solved, and meanwhile the response efficiency of the application and the utilization rate of the storage space are guaranteed.

The invention discloses an information resource efficient collaborative optimization method for a distributed computer system, which belongs to the technical field of information resource optimization control and comprises the following steps: executing a transaction according to a target lock element information set, monitoring popularity information of each resource segment, generating self-adaptive lock granularity decision information of each resource segment, and executing dynamic adjustment of lock granularity. And obtaining load sensing optimization parameters to complete lock competition optimization, and completing real-time iterative updating of lock element information and strategies. According to the method, the problems of resource competition and deadlock in the distributed system can be effectively solved, and the system performance and the resource utilization efficiency are improved. Transaction pre-allocation resources are reasonably allocated, the deadlock risk is reduced, lock granularity is dynamically adjusted according to resource segmentation popularity, lock competition optimization is completed based on load awareness optimization parameters, an adjustment result and the optimization parameters are synchronized to a distributed lock management library for real-time iteration updating, and it is ensured that a system always operates with an optimal strategy; and the distributed computer system efficiently and stably processes information resources in a cooperative manner.

The technology described herein is directed towards an artificial intelligence scheduler for real-time task execution systems, including an implementation based on a recurrent learning model. In one implementation, the model incorporates a deep Q-network and proximal policy optimization to learn efficient scheduling policies for real-time systems. The scheduler can optimize for various real-time system aspects, including avoiding deadlocks, minimizing blocking, avoiding priority inversion, and reducing starvation. The artificial intelligence scheduler learns from actual system experience data to regularly improve scheduling policies and / or adapt to changing system requirements.

The invention relates to the technical field of constructional engineering informatization management, and discloses a constructional engineering full-period collaborative management and risk prediction system, which comprises a resource token definition module, a resource token generation module, a resource management module and a risk prediction module, and is characterized in that physical elements are mapped into discrete resource tokens configured with unit time delay charge rates; the process transactional modeling module is used for packaging the process into an atomic transaction unit containing a request and a release instruction; the discrete event rehearsal simulation engine executes circulation in the virtual time axis and records the hanging duration; the deadlock detection module monitors the occupancy topology in real time to identify a loop waiting closed loop; according to the dynamic priority arbitration logic, an accumulated lag weight value is calculated according to the product of the rate and the duration, resources are forcibly allocated accordingly to eliminate deadlock, the dynamic arbitration algorithm based on the time value gradient is constructed, the physical lag cost is converted into the calculation weight, and the capacity of the system for automatically converging to the optimal solution under complex constraints is improved.

The invention relates to the technical field of storage, and particularly discloses a solid-state electronic disk soft destruction method, device and system, which are mainly used for solving the systematic vulnerability problems of key metadata single-point failure, power-on deadlock, single recovery strategy, insufficient core component redundancy protection and the like of the existing solid-state electronic disk in an extreme application scene. The method comprises the following steps: monitoring metadata integrity, PCIe links and power-on progress in real time by anomaly perception, and generating an abnormal data packet; the decision arbitration generates an instruction packet according to an abnormal matching recovery strategy; and the execution layer dispatches hardware to complete repairing or clearing operation and feeds back a result. According to the scheme, the deep fault of the solid-state electronic disk can be intelligently sensed, accurately arbitrated and effectively recovered without physical intervention, and the reliability, availability and safety of the solid-state electronic disk are remarkably improved.

The invention discloses a routing path determination method and device, a medium and a product, and relates to the technical field of communication. On the basis of a triangular prism network structure, when a source routing node and a target routing node are located on the same layer, the source routing node and the target routing node are determined by adopting a triangular prism side edge routing rule, a triangular prism surface routing rule and a relation of actual exclusive or results of the two routing nodes. According to the triangular prism side edge routing rule, side edge routing is preferentially carried out under the condition that the two routing nodes are not located on the same triangular prism face, the routing path is made to be short, and finally the two routing nodes move to the same triangular prism face. The routing rule of the triangular prism surface is based on the routing rule of routing along the triangular prism surface under the condition of the same surface, the flexibility and diversity of the routing path are determined according to different rules, and deadlock is avoided. And when in different layers, the system needs to jump to the same layer for routing planning, so that the reliability of communication is ensured.

The invention provides a deadlock detection method, system and equipment based on a lock template class, and a medium, and the method comprises the steps: creating a mutual exclusion lock template class, and customizing a lock type for protecting shared resources; the mutual exclusion lock template class sets a lock stack to record a lock state of a thread, and a timestamp mechanism is introduced into the mutual exclusion lock template class to detect a blocking state; constructing a lock dependency graph of the global thread by the mutual exclusion lock template class, and identifying a lock and a lock dependency relationship by adopting nodes and edges of the lock dependency graph; and presetting a check period, and identifying a deadlock cycle in the global thread by adopting a detection algorithm according to the lock stack and the lock dependency graph. According to the method, the state of the lock and the resource allocation condition of the thread are monitored in real time through the template class, the potential deadlock risk can be found in time, early warning is given out, detailed deadlock information is provided, and a developer is helped to rapidly position the deadlock problem.

The invention provides an optimization method for sharing one group of physical registers by multiple groups of logic registers, which comprises the following steps: S1, defining a shared physical register file, the step comprises a physical register structure link and a quantity constraint link, the physical register structure link comprises N vector physical registers with VLEN bit width, and the quantity constraint link comprises N vector physical registers with VLEN bit width; each vector physical register can be divided into VLEN / FLEN floating point physical registers; in order to solve the problem of hardware redundancy caused by independence of a floating point register and a vector register in an RISC-V architecture, instruction pipeline sharing of floating point and vector expansion is realized through a scheme that multiple groups of logic registers share a physical register, and the hardware redundancy is avoided. And hardware overhead is reduced.

The invention discloses a network-on-chip routing method and device, routing nodes, equipment, a medium and a product, and relates to the technical field of network-on-chip, and the method comprises the steps: firstly, screening the routing nodes through employing the input direction of a message, and limiting the selection range of the next-hop routing node; the relative position of the target routing node relative to the current routing node is determined, the routing nodes are further screened according to the relative position, and candidate routing nodes are determined; and determining a next-hop routing node according to the cache capacity and the input direction of the candidate routing node, and transmitting the message to be transmitted to the next-hop routing node to complete routing. The problem that the routing of the network-on-chip is easy to cause network message blockage or link failure of the network-on-chip can be solved. According to the method, an input direction is adopted to limit a selection range of a next-hop routing node, a relative position is adopted to determine candidate routing nodes, the next-hop routing node is determined in the candidate routing nodes based on cache capacity, and self-adaptive deadlock-free routing is realized.

The invention relates to the technical field of warehouse management, in particular to an intelligent warehouse management system based on deep learning, which constructs a space-time diagram model comprising nodes and edges by combining historical warehouse-in and warehouse-out records, AGV (Automatic Guided Vehicle) tracks and scheduling logs on the basis of spatial distribution information and channel communication relations of warehouse goods locations and function bits. And through deep space-time diagram convolution modeling, outputting a goods allocation value score and a traffic congestion probability, and identifying a goods allocation area which should be preferentially allocated by the high-frequency SKU. And a goods allocation strategy is generated through a reinforcement learning model, and excessive occupation and deadlock of channels are avoided while high-frequency goods are quickly put in and put out of a warehouse. And finally, generating an AGV scheduling instruction set through a path planning algorithm, and issuing and executing the AGV scheduling instruction set. Dynamic collaborative optimization of goods allocation planning and AGV scheduling is realized, the high-frequency goods operation efficiency is improved, meanwhile, path congestion and conflicts are effectively avoided, and the throughput rate and the operation reliability of the system are improved.

The invention discloses an intelligent manufacturing system deadlock prediction method based on Petri-Net-GCN. The method comprises the following steps: dividing an intelligent manufacturing system into a production equipment module, a production process module and a production resource module; carrying out formalized modeling on the module on the basis of a Petri network; a Petri-Net-GCN deadlock prediction model is constructed, and the Petri-Net-GCN deadlock prediction model comprises a house-to-house transition message transmission module and a transition-to-house message transmission module; performing bidirectional aggregation updating on features among nodes in the Petri net graph by using a graph neural network structure; collecting initial Tokenn distribution, an incidence matrix and a deadlock label of the intelligent manufacturing system to construct a data set, and inputting the data set into a model for training; predicting a deadlock risk in an unknown system state by using the trained model; according to the method, rapid prediction and judgment are carried out in the current state of the intelligent manufacturing system, and prior early warning information is provided for production scheduling and resource configuration.

The invention discloses a warehouse logistics resource optimization scheduling system and method based on cloud computing, and relates to the technical field of resource scheduling. Comprising the following steps: segmenting time resources by logistics equipment to generate a space-time resource matrix, and mapping each time slice into a non-homogenized token; an enterprise submits an equipment use demand, participates in auction of non-homogeneous tokens in an idle period through an intelligent contract, and the enterprise who wins the bid unlocks the equipment use right in the corresponding period; taking an auction result as a constraint condition, and performing analysis in combination with deep reinforcement learning to obtain an intelligent scheduling action; and performing statistics according to the intelligent scheduling action, calculating the allocated cost of the enterprise by adopting a Shapley value algorithm, and summarizing to obtain an enterprise cost allocation report. According to the method, the deadlock problem of a traditional A * algorithm in a high-density storage scene is overcome, the multi-AGV cooperation efficiency is remarkably improved, the storage logistics operation cost is reduced, and fine management and dynamic optimization configuration of resources are achieved.

The invention provides a chip resource management method, electronic equipment and a medium. Determining the type of the resource of the chip; configuring the chips according to the types of the resources to obtain a configuration strategy, wherein the configuration strategy comprises permission of different chips to check the resources, a thread synchronization protocol, a resource access protocol, a communication protocol between a real-time core and a non-real-time core, a resource allocation protocol and a task scheduling protocol; testing the resource running state of the chip configured with the configuration strategy; adjusting a configuration strategy according to the test result to obtain a target configuration strategy; the overall performance of the system and the utilization rate of system resources are improved. Through effective thread scheduling, competition of the threads for shared resources can be reduced, and therefore the probability of deadlock occurrence is reduced.

The invention relates to a modeling and formalized verification method for cache consistency protocol verification, and the method comprises the steps: building a protocol model which comprises a plurality of processor nodes, directory nodes and a communication mechanism through a structured modeling mode, and constructing an asynchronous message mechanism to simulate disordered concurrent communication; protocol behavior rules such as processor requests, directory responses and network receiving are defined, protocol property invariants are set, semantic constraints such as data consistency, confirmation before writing and sharing state legality are covered, model verification is carried out in a state space traversal mode, breadth-first search and a symmetry recognition mechanism are supported, and the method is suitable for the protocol behavior rules. A protocol error or deadlock state is effectively found, a traceable error path is generated, a verifier can automatically generate source codes through a compiler and operate on a host platform, and rapid verification and result output of a protocol model are achieved. The method has good protocol adaptability and model reusability, and is suitable for formalized verification of various cache consistency protocols.

The invention discloses a multi-dimensional data asynchronous calculation method and system based on a dynamic dependency graph, and relates to the field of data processing. The method comprises the following steps: constructing a metadata, logic and instance three-layer separation storage model; analyzing the reference relationship to construct a directed acyclic graph, and generating a calculation priority; monitoring data change, and executing asynchronous serialization calculation through a message queue based on priority; the associated document is automatically updated based on anchor mapping. According to the method, the calculation deadlock and the performance bottleneck of large-scale data in the Web environment are solved, logic decoupling and dynamic expansion are realized, the final consistency of the data is guaranteed, and the high-concurrency throughput and the stability are remarkably improved.

Discloses are a method for detecting a scheduling deadlock in data query. A query plan tree generated by a query statement includes a common temporary table production operator node, a common temporary table consumption operator node, and a hash join operator node. At least one right table chain in the tree is determined. Operator nodes in the right table chain are traversed from bottom to top starting from the leaf node in the right table chain, and the other operator nodes in the tree are traversed, to analyze an execution order relationship between the operator nodes traversed in the tree. When it is found based on the execution order relationship that there are two identical common temporary table consumption operator nodes in the tree that have scheduling dependency, and their upstream operators are the same common temporary table production operator, it is determined that there is a scheduling deadlock.

The invention relates to the technical field of computer networks, in particular to a shortest routing and deadlock avoiding method and device for a double-layer polygon topology, and the method comprises the steps: determining the routing type of the topology; xOR processing is carried out on the mark low bits of the source node and the target node, and a candidate node corresponding to the shortest path of the source node is determined; determining an available state of the anti-deadlock node, if the available state is idle, determining routing bypass information, and sending the routing bypass information to the source node; and determining an available state of the common node, and generating a route selection vector of the candidate node, so that the source node determines a next-hop node according to the route selection vector, sends the data packet to the next-hop node, and takes the next-hop node as a new source node. According to the method provided by the embodiment of the invention, the number of the shortest paths is expanded into all theoretical shortest paths, so that the number of the shortest paths among the nodes in the computer network topology structure is increased, the system transmission efficiency and the data throughput are improved, and meanwhile, deadlock is avoided.

The invention discloses a power grid material vehicle path planning method, and provides a space-time hierarchical modeling and cloud edge collaborative optimization architecture aiming at the problems of dynamic embargo, channel capacity fluctuation, multi-resource conflict, response lag and the like faced by power grid material dispatching in the prior art. By constructing a space-time coupled channel capacity-path planning hierarchical model, multi-commodity network flow pre-calculation and real-time vehicle path dynamic decoupling are carried out, and material distribution is optimized in combination with a space-time double-coding genetic algorithm; a multi-agent deep game decision-making mechanism is designed, channel priorities of different types of materials are dynamically balanced through reinforcement learning, and distributed conflict resolution is achieved; a block chain-based cross-domain scheduling instruction synchronization system is developed, low-delay path re-planning is realized by adopting a differential updating mechanism, and second-level updating of a scheduling scheme under an emergent road condition is supported; the on-chain evidence storage technology is introduced to guarantee instruction integrity and operation tracing, and the scheduling deadlock risk is reduced in combination with a key channel competition early warning model.

The invention relates to the technical field of embedded system testing, in particular to a method for testing functionality and stability of a core board service component, which comprises the following steps of: initializing a core board testing environment, ensuring that software and hardware parameters are consistent in a testing process, and aiming at the service component on a core board, testing the service component on the core board; the method comprises the following steps of: analyzing and generating a dependency relationship graph among components by utilizing a dependency graph model, optimizing a key dependency relationship through a deep learning model, performing functional testing on the components according to a priority based on the optimized dependency relationship graph, and testing the stability of a core board during high-concurrency and multi-task operation through multi-thread scheduling and concurrent task simulation. Abnormal, resource competition and deadlock problems are detected; and finally, in combination with an actual application scene, carrying out component hot plug, network abnormity, power-off recovery and other scene tests, and analyzing test data to generate a comprehensive test report. According to the method, the test coverage rate and efficiency are improved, and stable operation of the system under complex conditions is ensured.

The invention provides a multi-AGV conflict solving scheduling method based on a graph theory, and the method comprises the steps: planning a planning path from a starting point to a terminal point for each AGV, and issuing an actual path to the AGV for execution; defining a conflict detection range in a planned path for each AGV, calculating a conflict relationship between each AGV and other AGVs in the range, and updating a graph structure representing the conflict relationship between the AGVs according to the conflict relationship; identifying whether a cyclic conflict which cannot be solved by simply adjusting a sequence or a path exists in the conflict graph, and designing and issuing a specific unlocking path or a conflict solving strategy according to the detected deadlock; and according to the conflict resolution strategy, the planned path of the related AGV is adjusted in real time, and the adjusted path is used as an issuing path to be sent to the AGV for execution so as to deal with dynamically occurring conflicts. The method is used for solving conflicts and deadlocks in the multi-AGV scheduling process, and deadlocks are prevented from being formed in advance under the condition that information is sufficient.

The invention discloses a starting method for a pre-starting execution environment, computer equipment and a related product, and relates to the technical field of computers, the method comprises the following steps: when a first network driver triggers a target unloading process due to loading of a second network driver and the first network driver has sent a network release message in the target unloading process, starting the target unloading process; monitoring an overtime event and a network reply message event of the monitoring timer; when the timeout event is monitored and the network reply message event is not monitored, triggering the first network driver to resend the network release message; and when the retransmission times exceed a preset retransmission threshold value, forcibly terminating the target event polling operation, and transferring the network control right from the first network driver to the second network driver, so that the second network driver takes over and continues to execute the starting process based on the own network protocol stack. The technical problem of deadlock in the starting process of the pre-starting execution environment in related technologies is solved, and the technical effect of improving the starting reliability of the pre-starting execution environment is achieved.

The invention provides a scheduling method, device and equipment of a wafer manufacturing system. The method comprises the following steps: constructing a time Petri net model by adopting a Petri net model according to a wafer processing route and constraint conditions; the constraint condition is the time delay added on the transition or library; an incidence matrix of the time Petri net model is calculated, and the incidence matrix is used for calculation to obtain the number of times of emission; the emission times are emission times corresponding to each transition from the initial identifier to the target identifier under the time Petri network model; operating the time Petri net model by using the launching times in combination with the shortest process time priority strategy, and processing the deadlock problem by adopting multi-step rollback in the operation process of the time Petri net model to obtain a scheduling result of the wafer manufacturing system; wherein the shortest process time priority strategy only reserves a preset number of enabling transitions under each identifier. And the generation efficiency of the scheduling result is improved on the basis of stable operation of the wafer manufacturing system.

The embodiment of the invention provides a network-on-chip data processing method and device, computer equipment and a storage medium. The method comprises the following steps: when at least one message to be transmitted is detected, adding the message to a message queue to be transmitted; when to-be-transmitted messages in multiple propagation directions exist in the to-be-transmitted message queue, determining the state of an output port pointed by each to-be-transmitted message; when the candidate to-be-transmitted messages of which the pointing output port state is an idle state exist, selecting a target to-be-transmitted message from a plurality of candidate to-be-transmitted messages according to a preset arbitration priority for transmission; repeatedly executing the step of selecting a target to-be-transmitted message from the plurality of candidate to-be-transmitted messages according to the preset arbitration priority and transmitting the target to-be-transmitted message until the candidate to-be-transmitted message of which the pointing output port state is an idle state does not exist in the to-be-transmitted message queue; and when the to-be-transmitted message queue does not contain the to-be-transmitted message, stopping processing the to-be-transmitted message queue. Therefore, the transmission efficiency can be improved, and deadlock can be prevented.

The invention relates to the field of knowledge graph data processing, and discloses an indoor space automatic layout and rendering method and system based on a design knowledge graph, and the method comprises the steps: maintaining an entity knowledge graph containing a variation path, and discretizing a continuous geometric space into an environment topological graph; executing node mapping and resource topology handshake verification based on subgraph isomorphism; and responding to the mapping deadlock, triggering recursive topology rewriting along the variation path to reconstruct the query sub-graph, and generating a configuration instruction. According to the method, continuous geometric search is converted into discrete atlas isomorphism and attribute propagation, the high-dimensional space layout calculation complexity is reduced, the deadlock problem under the over-constraint condition is solved by utilizing a recursive variation mechanism, and the configuration efficiency is improved. And the logic leakproofness and engineering compliance of the layout scheme are ensured.

The invention discloses an industrial transfer robot path planning method based on artificial intelligence, relates to the technical field of industrial transfer robot path planning and multi-robot cooperative control, and provides a systematic breakthrough for narrow roadway passage of an industrial transfer robot through deep cooperation of the game theory and federal learning. A robot meeting scene is modeled as a limited action game, and a revenue function is designed in combination with priority weight and security constraint, so that the robot can autonomously generate a forward, yielding or keeping strategy, and bidirectional deadlock is avoided from the source; through a synchronous output mechanism of action probability distribution and a time window, the strategy performability is remarkably improved; the track layer directly generates a synchronization path on the cost graph according to the time window, and motion interruption caused by repeated sampling in a dynamic window method is avoided; even if track deviation or communication abnormity occurs, the rollback strategy can guarantee that the system recovers to be stable immediately, and continuous operation of the production line is maintained.

The invention provides an FPGA logic comprehensive optimization method based on a finite-state machine and electronic equipment, and the method comprises the steps: traversing each D trigger in a circuit netlist, and obtaining an input signal and an output signal of the D trigger; when the output signal of the D trigger belongs to the state signal of the finite-state machine, extracting the state signal of each state and storing the state signal in a state signal set according to a preset coding mode, and extracting the state transition condition of each state and storing the state transition condition in a state transition set; eliminating an unreachable state and state transition in the state signal set, and identifying a deadlock state in the state signal set; for each state signal and state transition condition of the finite-state machine, a multiplexer unit and a flip-flop unit for each state signal are generated, and a D flip-flop is deleted from the circuit netlist. According to the method, accurate and effective logic optimization can be carried out on the finite-state machine, and the number of resources after FPGA logic synthesis is reduced.

The invention relates to a processor, electronic equipment and a data communication method. Based on the invention, the communication interconnection between the processor and other processors is realized through the network switching device, and the data communication can be realized by utilizing a plurality of groups of QP receiving and transmitting channels borne on the same port cascade transmission link. Wherein the multiple groups of QP receiving and transmitting channels correspond to multiple types of interactive data involved in data communication, and the multiple types of interactive data can concurrently realize mutually independent stream transmission through the multiple groups of QP receiving and transmitting channels respectively. Therefore, compared with a serial mode of cascading transmission links of streaming transmission time division multiplexing ports of multiple types of interactive data, the transmission deadlock risk of data communication between processors can be reduced.

The invention relates to the technical field of data lines, and particularly discloses a data line system and a data line for intelligently switching data transmission and charging, and the system comprises a dual-core synchronization management module which is used for enabling dual cores to enter an initial detection state through encryption synchronization signaling when equipment is connected; the asynchronous signal processing module is used for generating state judgment parameters through multi-scale sliding window processing and time-frequency domain feature fusion; the consensus decision arbitration module outputs a backtracking trigger signal through dynamic projection transformation and self-adaptive threshold comparison; the state backtracking recovery module is used for generating a retry instruction with a random delay period based on the historical backtracking success rate and the signal quality evaluation; the safety mode control module is used for identifying dominant features by analyzing historical failure records and switching to a safety operation mode; through distributed dual-core cooperative processing and an intelligent fault recovery mechanism, the technical problems of confusion of protocol stacks and deadlock of a state machine in a complex electromagnetic environment are solved, and the anti-interference capability and reliability of the system are improved.

The invention provides a chip, a data transmission method and electronic equipment. The chip comprises a plurality of core particles, each core particle comprises a plurality of functional nodes, the plurality of core particles are interconnected by adopting a grid structure, and the plurality of functional nodes in each core particle are interconnected by adopting a bidirectional annular structure; a first data packet sent from the first core grain to the second core grain is transmitted in the annular structure in the first core grain according to a first direction, and is transmitted to the second core grain through the grid structure according to a dimension sequence routing strategy, and the first data packet is transmitted in the annular structure in the second core grain according to a second direction, the second direction is opposite to the first direction. According to the method and the device, deadlock can be avoided, the implementation complexity is low, and the operation overhead is small.

The invention relates to the technical field of inspection, in particular to an agent inspection task allocation method and device and an inspection system. The agent inspection task allocation method comprises the steps of obtaining an inspection task, performing task splitting on the inspection task to obtain sub-task information of a plurality of sub-tasks, sending the sub-task information to a plurality of second devices, so that the plurality of second devices generate first bidding information for a target sub-task according to the sub-task information, and allocating the first bidding information to the target sub-task according to the first bidding information. And obtaining first bidding information sent by the plurality of second devices, determining a target device from the plurality of second devices according to the first bidding information, and sending a first task execution instruction of the target sub-task to the target device, so that the target device executes the target sub-task according to the first task execution instruction. By splitting the complex inspection task and selecting the most suitable equipment to execute each split sub-task, not only can the task deadlock be avoided, but also the inspection task time delay can be reduced.