9 results about "Memory barrier" patented technology

This invention provides a distributed task scheduling method and apparatus based on task state switching, relating to the field of data processing. The method includes: distributively scheduling multiple tasks according to system service instructions and displaying the task states of the multiple tasks in a graphical user interface; responding to a state switching operation for a target task among the multiple tasks, mapping the target TCB and target key state fields corresponding to the target task to a writable memory region within the process in shared memory according to the state switching operation; modifying the state parameters in the writable memory region within the process online using atomic operations corresponding to memory barriers based on the target TCB and target key state fields; responding to the memory modification event corresponding to the completion of the state parameter modification, continuously polling the executor corresponding to the target task and sensing the state change through notification of the memory modification event, and adjusting the executor's own behavior according to the sensed state change.

This invention discloses a Java code layout optimization method that does not interrupt application services. The method includes: acquiring front-end bottleneck data of the application; when it is determined that code layout optimization is needed based on the front-end bottleneck data, collecting the dynamic control flow graph of the application service; calculating a new code layout based on the dynamic control flow graph; generating new code according to the new code layout; correcting relocation information in all code, that is, redirecting function calls and data references pointing to the old code to the new code. During the correction process, memory barriers and cache maintenance instructions are used to ensure the atomicity and consistency of the modification operations, so as to achieve uninterrupted application services; only reclaiming the memory space used by the old code that is no longer executed to store the new code generated in the next optimization, retaining the function code still on the call stack, so that most of the memory space can be reclaimed without interrupting application services. This method effectively alleviates the processor front-end bottleneck of Java applications and improves application performance.

This application provides an asynchronous communication management method, apparatus, electronic device, and storage medium, relating to the field of chip design and manufacturing technology. The method includes: modifying the instruction count and / or data volume count in the memory barrier data block of the asynchronous communication unit based on instructions sent by the asynchronous communication unit; and modifying the status bits in the memory barrier data block of the asynchronous communication unit when the instruction count and data volume count meet preset conditions. The method and apparatus provided by this application not only manage the synchronization state between producers and consumers based on memory barriers, ensuring the consistency and correctness of data exchanged between producers and consumers, but also abstract the complex count update and status judgment logic from specific test cases, forming a general asynchronous communication management mechanism that can be implemented by a dedicated memory barrier controller, supports random testing, and improves the flexibility of test verification.

One example provides a computing device (100) comprising a write communication channel (104) and an initiator device (120) connected to the write communication channel (104). The initiator device (120) has ordering rules for the write communication channel (104). Further, a network on a chip (NoC) device (112) is connected to the write communication channel (104). The NoC device (112) includes a reorder buffer (118). The computing device (100) also comprises a hardware memory barrier (HMB) device (102) connected to the write communication channel (104) such that at least a portion (132) of the write communication channel (104) is routed through the HMB device (102).

This application relates to the field of computer technology, providing a non-intrusive Linux memory barrier modification method and system. The method is applied to scenarios where an information system is migrated from a strong memory model chip architecture to a weak memory model chip architecture. Specifically, it includes: in the newly added adaptation layer, determining the target system calls invoked by the component layer, and constructing a rewritten function with the same name for each target system call. The rewritten function sequentially includes a first memory barrier instruction, an instruction to call the original target system call, and a second memory barrier instruction; compiling the rewritten function into a dynamic link library; and when the business process starts, preferentially loading the custom dynamic library by preloading environment variables to hijack system calls, so that the operating system's dynamic linker redirects the component layer's calls to the target system calls to the rewritten function. This application achieves complete decoupling of business logic and adaptation logic by implanting a memory barrier at the system call layer without modifying the business layer and component layer code.

One example provides a computing device comprising a write communication channel and an initiator device connected to the write communication channel. The initiator device has ordering rules for the write communication channel. Further, a network on a chip (NoC) device is connected to the write communication channel. The NoC device includes a reorder buffer. The computing device also comprises a hardware memory barrier (HMB) device connected to the write communication channel such that at least a portion of the write communication channel is routed through the HMB device.

This application provides a heterogeneous core spinlock implementation system and method. The system includes: a shared memory module for supporting atomic operation protocols of the architecture atomic operation unit; an ARM core module and a DSP core module, both used to complete initialization through the atomic operation unit, independently initiate lock requests through the architecture atomic operation unit and CAS logic processing unit, detect in real time whether the lock acquisition conditions are met based on the atomic operation unit, access shared resources based on the memory barrier control unit when the lock acquisition conditions are met, and independently release the lock through the atomic operation unit after completing the access to the shared resources; and an AXI bus interconnect module for realizing the interconnection between the dual cores and the shared memory module, which can adapt to the heterogeneous architecture of ARM cores and DSP cores, improve synchronization efficiency and reliability while ensuring fairness, and fully utilize the hardware performance of the dual cores.

This invention belongs to the field of virtual serial port technology, specifically relating to a method for implementing a bare-metal program to use a virtual serial port via Jailhouse. The method includes the following steps: Step S1: Obtain the address of the shared memory of the virtual serial port; Step S2: Configure the shared memory of the virtual serial port in Jailhouse based on the address of the shared memory; Step S3: Reimplement the print function in Jailhouse to write the output characters of the bare-metal program into the shared memory of the virtual serial port; Step S4: Recompile the Jailhouse code to generate an image file of the bare-metal program; Start the bare-metal program based on the image file, and write the output of the bare-metal program to the shared memory of the virtual serial port through the print function. This method allows the bare-metal program to directly write to the shared buffer and utilizes memory barriers to ensure data visibility, achieving high real-time character output.