16 results about "Memory barrier" patented technology

The invention relates to the technical field of multi-agent collaboration, in particular to a multi-agent collaboration method and system based on shared memory data exchange, and the method comprises the steps: creating and initializing a shared data area which is mapped and accessed by a plurality of agent processes in a physical memory; constructing an annular buffer structure on the shared data area, and realizing a lock-free read-write pointer propulsion mechanism based on atomic operation and a memory barrier so as to support a plurality of intelligent agents to perform data read-write concurrently; asynchronous notification of data updating is carried out between agent processes through a lightweight event notification mechanism; and each agent performs autonomous decision making and task scheduling based on the shared data so as to realize distributed collaboration. A data block version control and verification mechanism is introduced into the annular buffer structure, and when it is detected that the agents are abnormal, resources of the abnormal agents are automatically recycled, and a data consistency recovery process is triggered. Multiple times of data copying between a kernel mode and a user mode are eliminated, and communication delay is reduced.

This invention provides a distributed task scheduling method and apparatus based on task state switching, relating to the field of data processing. The method includes: distributively scheduling multiple tasks according to system service instructions and displaying the task states of the multiple tasks in a graphical user interface; responding to a state switching operation for a target task among the multiple tasks, mapping the target TCB and target key state fields corresponding to the target task to a writable memory region within the process in shared memory according to the state switching operation; modifying the state parameters in the writable memory region within the process online using atomic operations corresponding to memory barriers based on the target TCB and target key state fields; responding to the memory modification event corresponding to the completion of the state parameter modification, continuously polling the executor corresponding to the target task and sensing the state change through notification of the memory modification event, and adjusting the executor's own behavior according to the sensed state change.

The application discloses a Direct3D 12 resource management method based on a virtual general layout, and after VKD3D is initialized when VK_KHR_unified_image_layouts is not supported, a mapping matrix of a D3D12 resource state, a virtual general layout, a Vulkan physical layout and a pre-compiled conversion path library are constructed by traversing a Vulkan image format, when a D3D application creates a D3D12 resource, parameters are parsed to divide a sub-resource, a resource handle containing a physical layout pool and a sub-resource view array is created, binding of a Vulkan image and memory is completed, when a resource state is set, a resource handle is inquired, the virtual general layout and the Vulkan physical layout are compared in sequence, redundant requests with no change in semantics and layout are filtered to obtain a resource conversion request, the resource conversion request is combined to generate a batch memory barrier instruction, and the batch memory barrier instruction is pre-submitted to a kernel, and execution is completed by a GPU idle time window.

This invention discloses a Java code layout optimization method that does not interrupt application services. The method includes: acquiring front-end bottleneck data of the application; when it is determined that code layout optimization is needed based on the front-end bottleneck data, collecting the dynamic control flow graph of the application service; calculating a new code layout based on the dynamic control flow graph; generating new code according to the new code layout; correcting relocation information in all code, that is, redirecting function calls and data references pointing to the old code to the new code. During the correction process, memory barriers and cache maintenance instructions are used to ensure the atomicity and consistency of the modification operations, so as to achieve uninterrupted application services; only reclaiming the memory space used by the old code that is no longer executed to store the new code generated in the next optimization, retaining the function code still on the call stack, so that most of the memory space can be reclaimed without interrupting application services. This method effectively alleviates the processor front-end bottleneck of Java applications and improves application performance.

This application provides an asynchronous communication management method, apparatus, electronic device, and storage medium, relating to the field of chip design and manufacturing technology. The method includes: modifying the instruction count and / or data volume count in the memory barrier data block of the asynchronous communication unit based on instructions sent by the asynchronous communication unit; and modifying the status bits in the memory barrier data block of the asynchronous communication unit when the instruction count and data volume count meet preset conditions. The method and apparatus provided by this application not only manage the synchronization state between producers and consumers based on memory barriers, ensuring the consistency and correctness of data exchanged between producers and consumers, but also abstract the complex count update and status judgment logic from specific test cases, forming a general asynchronous communication management mechanism that can be implemented by a dedicated memory barrier controller, supports random testing, and improves the flexibility of test verification.

One example provides a computing device (100) comprising a write communication channel (104) and an initiator device (120) connected to the write communication channel (104). The initiator device (120) has ordering rules for the write communication channel (104). Further, a network on a chip (NoC) device (112) is connected to the write communication channel (104). The NoC device (112) includes a reorder buffer (118). The computing device (100) also comprises a hardware memory barrier (HMB) device (102) connected to the write communication channel (104) such that at least a portion (132) of the write communication channel (104) is routed through the HMB device (102).

This application relates to the field of computer technology, providing a non-intrusive Linux memory barrier modification method and system. The method is applied to scenarios where an information system is migrated from a strong memory model chip architecture to a weak memory model chip architecture. Specifically, it includes: in the newly added adaptation layer, determining the target system calls invoked by the component layer, and constructing a rewritten function with the same name for each target system call. The rewritten function sequentially includes a first memory barrier instruction, an instruction to call the original target system call, and a second memory barrier instruction; compiling the rewritten function into a dynamic link library; and when the business process starts, preferentially loading the custom dynamic library by preloading environment variables to hijack system calls, so that the operating system's dynamic linker redirects the component layer's calls to the target system calls to the rewritten function. This application achieves complete decoupling of business logic and adaptation logic by implanting a memory barrier at the system call layer without modifying the business layer and component layer code.

The invention discloses a data read-write method and device based on a memory barrier instruction and a program product, relates to the technical field of processors, is applied to a multi-core instruction set processor, and comprises the following steps: determining an initial memory barrier instruction in a current running user program code; the initial memory barrier instruction is a barrier instruction added by a user; checking the initial memory barrier instruction by utilizing a preset barrier instruction checking condition to obtain a checking result; the preset barrier instruction check condition is a condition which is constructed on the basis of a front-back execution sequence of the multi-core instruction and is used for controlling the read operation to obtain the latest value of the data; and adjusting the initial memory barrier instruction according to the check result, and executing subsequent data read-write operation based on the adjusted target barrier instruction. Therefore, the initial memory barrier instruction is adjusted in combination with the barrier instruction check condition, and then the data read-write operation is executed, so that the accuracy of the memory barrier function can be ensured, and the overall performance, safety and stability of the processor are improved.

One example provides a computing device comprising a write communication channel and an initiator device connected to the write communication channel. The initiator device has ordering rules for the write communication channel. Further, a network on a chip (NoC) device is connected to the write communication channel. The NoC device includes a reorder buffer. The computing device also comprises a hardware memory barrier (HMB) device connected to the write communication channel such that at least a portion of the write communication channel is routed through the HMB device.

This application provides a heterogeneous core spinlock implementation system and method. The system includes: a shared memory module for supporting atomic operation protocols of the architecture atomic operation unit; an ARM core module and a DSP core module, both used to complete initialization through the atomic operation unit, independently initiate lock requests through the architecture atomic operation unit and CAS logic processing unit, detect in real time whether the lock acquisition conditions are met based on the atomic operation unit, access shared resources based on the memory barrier control unit when the lock acquisition conditions are met, and independently release the lock through the atomic operation unit after completing the access to the shared resources; and an AXI bus interconnect module for realizing the interconnection between the dual cores and the shared memory module, which can adapt to the heterogeneous architecture of ARM cores and DSP cores, improve synchronization efficiency and reliability while ensuring fairness, and fully utilize the hardware performance of the dual cores.

The application discloses a system memory peak bandwidth measurement method and electronic equipment, and relates to the technical field of bandwidth measurement. The application optimizes a memory bandwidth measurement process by cooperating with a dynamically selected maximum width vector instruction, forced non-cache access and NUMA awareness binding. The application improves single operation data throughput to 512 bits or even higher by using the vector processing capability of a CPU. The application bypasses a cache level by cooperating a non-temporal instruction with a memory barrier instruction, eliminates the interference of cache hits or jitter on measurement results, ensures that measurement results truly reflect the performance of a memory system itself, avoids delay and congestion caused by cross-node access through an automatic NUMA binding mechanism, and improves the accuracy, stability and repeatability of test results.

The application provides an instruction synchronization method and an artificial intelligence chip, and relates to the technical field of the artificial intelligence chip. The method comprises the following steps: after a processing core sends a calculation instruction, a barrier instruction with a memory address is sent, so that the calculation instruction and the barrier instruction are in order into a cache, so as to ensure that the cache receives the calculation instruction and implements the calculation. In this way, a large number of memory barrier operations are reduced, so that the processing time delay of the memory instruction is reduced. For a plurality of processing cores bound to the same target barrier identifier, the number of synchronized instructions of the plurality of processing cores is recorded in real time. When the number of synchronized instructions is equal to the expected synchronization number, a synchronization success message is returned to the plurality of processing cores, so as to realize the instruction synchronization of the plurality of processing cores. The process does not need each processing core to loop read the atomic accumulation result, so that the occupation of bandwidth resources such as bus bandwidth and direct interconnection bandwidth is greatly reduced, so that the instruction synchronization cost is reduced and the efficiency of the whole system is improved.

This invention belongs to the field of virtual serial port technology, specifically relating to a method for implementing a bare-metal program to use a virtual serial port via Jailhouse. The method includes the following steps: Step S1: Obtain the address of the shared memory of the virtual serial port; Step S2: Configure the shared memory of the virtual serial port in Jailhouse based on the address of the shared memory; Step S3: Reimplement the print function in Jailhouse to write the output characters of the bare-metal program into the shared memory of the virtual serial port; Step S4: Recompile the Jailhouse code to generate an image file of the bare-metal program; Start the bare-metal program based on the image file, and write the output of the bare-metal program to the shared memory of the virtual serial port through the print function. This method allows the bare-metal program to directly write to the shared buffer and utilizes memory barriers to ensure data visibility, achieving high real-time character output.

The invention provides a spin lock implementation method and device based on hardware semaphore, equipment and a medium, and relates to the field of embedded operating systems, the method comprises the following steps: binding a spin lock with the hardware semaphore, and allocating a counting register to the spin lock; if the first core requests to acquire the spin lock, verifying whether the current holder of the hardware semaphore is the first core; if yes, reading a count value for validity check, and if valid, adding 1 to the count value and returning; if the core is not the first core, hardware semaphore locking is called; after the hardware semaphore is obtained, whether a current holder is a first core is verified, if yes, whether a count value is 0 is verified, and if yes, 1 is added to the count value, and a memory barrier instruction is inserted; if the first core requests to release the spin lock, verifying whether the first core is a holder of the spin lock; if yes, subtracting 1 from the count value, judging whether the count value is 0 or not, and if yes, calling hardware semaphore for unlocking to complete lock release. The scheme can reduce system power consumption.

The invention provides a shared memory consistency data structure, control method and system based on task priority calculation and a dynamic memory barrier mechanism. The data structure comprises a shared memory access control table, a task access control table, a memory barrier management table and a task barrier priority queue, the system comprises a scheduler; when the task starts, the scheduler calculates the activation time and granularity of the fence according to the priority and periodicity of the task; the fence granularity of the task with the highest priority is set to be minimum; each task checks the state of a corresponding memory area in the shared memory access control table before accessing the shared memory; when the memory fence state is in the locking state, the task cannot access the corresponding memory area, and when the memory fence locking state is released, the task obtains data and modifies the shared memory; when multiple tasks are executed concurrently, the scheduler dynamically adjusts the locking time of the memory fence according to the priority of the tasks, and the situation that the memory access of the task with the highest priority is blocked by tasks with other priorities is avoided.