48 results about "Random testing" patented technology

The invention discloses a chip random test method and device, equipment and a storage medium, and the method comprises the steps: obtaining an architecture description document corresponding to a to-be-tested chip, and analyzing the characteristic information of each sub-module in the to-be-tested chip and the interaction relation between the sub-modules; determining constraint conditions corresponding to the sub-modules, and determining a plurality of test scenes corresponding to the sub-modules according to the constraint conditions; integrating the constraint conditions corresponding to each sub-module in the top verification environment, and determining a target test scene corresponding to each sub-module in a plurality of test scenes according to an integration result; and determining a plurality of random test scenes corresponding to the to-be-tested chip according to the architecture description document, and generating a plurality of random test cases corresponding to the to-be-tested chip according to the target test scene and the random test scenes. According to the technical scheme, the random testing efficiency of the chip and the accuracy of the testing result can be remarkably improved, the requirement for simulation resources is reduced, and the integrity and reliability of the chip testing process are improved.

The invention relates to a GPU system verification method and device, electronic equipment, a storage medium and a program product. The method comprises the following steps: obtaining a target random test excitation sequence; respectively inputting the target random test excitation sequence into the GPU function model and the register transfer level model; wherein the GPU function model is a software model used for simulating functions of the GPU; the register transfer level model is a model written based on a hardware description language, and the register transfer level model is used for describing hardware implementation and behaviors of the GPU; obtaining a function simulation result output by the GPU function model in response to the target random test excitation sequence and a simulation result output by the register transfer level model in response to the target random test excitation sequence; and comparing the function simulation result with the simulation result to obtain a first random verification result of the GPU system. According to the method and the device, the GPU system verification flexibility can be remarkably improved.

The invention relates to a GPU system verification method and device, electronic equipment, a storage medium and a program product. The verification environment comprises a parameter transfer verification environment and a random verification environment which are mutually independent, the method comprises the steps that a parameter transfer test set and a random test set are obtained, the parameter transfer test set comprises a plurality of parameter transfer test cases, and the random test set comprises a plurality of random test cases; acquiring a verification environment control instruction; in response to the verification environment control instruction used for starting the random verification environment, verifying the GPU system based on the random test set through the random verification environment; or, responding to the verification environment control instruction used for starting the parameter unloading verification environment, and verifying the GPU system based on the parameter unloading test set through the parameter unloading verification environment. According to the invention, the efficiency and accuracy of GPU system verification can be improved.

The technology described herein provides an automated software-testing platform that functions in an undefined action space. The technology described herein starts with an undefined action space but begins to learn about the action space through random exploration. Both the action taken during testing and the resulting state may be communicated to a centralized testing service. The technology described herein also mines the action telemetry data and state telemetry data to identify action patterns that produce a sought after result. Once a plurality of action patterns is identified and, at least, a partial model of the action space is built, the testing on the test machines may be split into random test mode, replay test mode, and a pioneering test mode.

According to the game copy automatic test case generation method and the terminal, a copy digital twinning scene is constructed through an environment simulator, an intelligent agent is generated, and the intelligent agent makes a decision by using a dual-network mechanism of a layered DQN controller; training agents in a grading manner by utilizing dynamic course learning, gradually improving difficulty according to copy complexity and migrating low-level training weights, and guiding the agents to explore in combination with a multi-dimensional reward function; generating a test case according to the agent exploration trajectory; according to the method, the digital twinning scene is constructed through the environment simulator, and the intelligent agent autonomously explores and covers a hidden path and a dynamic mechanism based on layered DQN and dynamic course learning, so that the test coverage rate can be effectively improved, the effectiveness of test case generation is ensured, and the dynamic course learning can effectively improve the training efficiency and quickly adapt to copy updating; the defects of low random test efficiency and poor static algorithm adaptability are overcome, and high-coverage, efficient and self-adaptive test case generation is realized.

The invention discloses a page table data distribution method and device, equipment and a medium. The page table data distribution method comprises the following steps: based on a test request of an MMU circuit, reading non-required parameter interface input data and required parameter interface input data; inputting data based on the non-necessary parameter interface, and creating a target page table tree; and managing an address allocation space of the target page table tree according to the necessary parameter interface input data and the double linked list structure, and allocating page table data to the address allocation space of the target page table tree while traversing the target page table tree. According to the technical scheme provided by the embodiment of the invention, the page table data generation efficiency can be improved, the data dependence of page table data distribution is broken, and the requirement of MMU IP level large-scale random testing can be met.

This invention relates to the field of chip verification technology, and more particularly to a random verification method, electronic device, and medium based on register arrays. S1: Set m=1, execute S2; S2: Send data to RA in the target register array. m and RB m Input the same random test stimulus; S3, RA m Predict the random write value, and set F m Updated to RA m Predicted random write values; S4, RB m Write random numbers based on the input random test stimulus; S5, read the currently stored data in the RTL instances of all registers in the chip under test design in random order and compare it with the corresponding reference value. If they are all the same, proceed to S6; otherwise, the verification fails and the process ends; S6, compare m and M. If m

A DMA controller verification method is disclosed, comprising: constructing a hierarchical coverage model of functional characteristics based on the functional characteristics of the DMA controller, wherein the hierarchical coverage model of functional characteristics includes multiple levels corresponding to different functional dimensions of the DMA controller, and each level includes one or more coverage points corresponding to one or more functional characteristics under the corresponding functional dimension; generating a functional characteristic cross-combination matrix based on the hierarchical coverage model of functional characteristics, wherein the functional characteristic cross-combination matrix of functional characteristics includes multiple cross-combinations of coverage points selected from at least two different levels of the hierarchical coverage model of functional characteristics, and each cross-combination represents a corresponding functional characteristic cross-combination of the DMA controller; and generating a coverage monitoring configuration based on the functional characteristic cross-combination matrix of functional characteristics for monitoring the number of hits of the functional characteristic cross-combinations represented by various cross-combinations in the functional characteristic cross-combination matrix in random tests of the DMA controller.

An embodiment of the present invention provides a chip reset verification method, device and equipment supporting multiple spatial domains. The method includes: in a verification platform, encapsulating an independent and reusable general verification component for a reset signal; during simulation, driving the reset signal to the reset signal input port of a design under test in the reset_phase stage to reset the design under test, and monitoring the state of the reset signal by using a verification component related to the reset signal; jumping back to the reset_phase stage when the simulation is about to end; using a factory overloading mechanism to overload and replace the verification platform, so that after jumping back to the reset_phase, restarting the execution of a random test sequence; obtaining the actual response of the design under test to the random test sequence, and comparing the actual response with a predicted response to verify the reset function of the design under test. The present invention solves the problem of reset scenario testing for multiple clocks and their corresponding reset spatial domains that may exist in a DUT.

An embodiment of the present application provides an instruction verification method, device, electronic device and storage medium, the method comprising: obtaining an instruction set to be verified; performing directed testing and random testing on the instruction set to be verified, respectively, to obtain an assembly file corresponding to the instruction set to be verified; using preset simulation software and the assembly file corresponding to the instruction set to be verified, to determine a verification result corresponding to the instruction set to be verified. In an embodiment of the present application, directed testing and random testing are performed on the instruction set to be verified, wherein the directed test is used to test special functions of the set, and the random verification method can randomly verify the loop depth, number of loops, and instructions within the loop body. The instruction verification method provided by the present application has good scalability and reusability, and can meet the needs of related verification system upgrades brought about by future adjustments to the number of loop instructions, loop depth, etc.

The invention relates to a low-intrusive environment anomaly testing method and system, and belongs to the technical field of software testing. A current environment anomaly test method has the problems of uncontrollable resource occupation, inflexible tool deployment and the like, and the stability and the test efficiency of a system are influenced. The invention aims to solve the problem by constructing a test architecture in which a server side is separated from a test executor, the server side is responsible for generating and sending a test case, the test executor executes a corresponding test on a tested machine, and a control group technology is adopted to accurately manage resources, so that the test execution hardly affects the original system performance, and the test efficiency is improved. Besides, the method supports the combined configuration of fixed and random test parameters, so as to generate test cases with wider coverage, thereby greatly improving the comprehensiveness and depth of the test. Compared with the prior art, the method has obvious flexibility and expandability, the automation level of the testing process can be effectively improved, the testing deployment is simplified, and the early-stage preparation cost is reduced.

The invention provides a game testing method and device and electronic equipment, and the method comprises the steps: controlling at least one electronic equipment to load a specified game function module, and collecting test data generated when an artificial intelligence (AI) virtual role executes a game task included in game content corresponding to the specified game function module in the specified game function module; performing rule verification on the test data based on a pre-generated game design rule; performing comparison verification on the test data based on the historical test data passing the verification; and generating a test result of the target game based on the abnormal test data and the normal test data determined by the rule verification and the comparison verification. According to the method, a corresponding test script does not need to be written for each game task, and the AI virtual character is used for carrying out random running test, so that each function point in the game with high degree of freedom can be covered.

The present invention discloses a method, apparatus, device, and medium for allocating page table data. The method comprises: reading non-mandatory parameter interface input data and mandatory parameter interface input data based on a test request from an MMU circuit; creating a target page table tree based on the non-mandatory parameter interface input data; managing the address allocation space of the target page table tree according to the mandatory parameter interface input data and a bidirectional linked list structure, and allocating address space and page table data for the target page table tree while traversing the target page table tree. The technical solution of the embodiment of the present invention can improve the efficiency of page table data generation, break the data dependency of page table data allocation, and meet the requirements of large-scale random testing at the MMU IP level.

The embodiment of the invention provides a semi-random automatic testing method and system for an Android local library, and the method comprises the steps: taking an Android APK as input, and generating a local library function list; c / C + + codes in the APK are converted into Java byte codes, and the Java byte codes are repackaged to obtain a cross-language unified APK; based on the cross-language unified APK, constructing a composite call relation graph containing App states, UIs and cross-language function calls; according to the composite calling relation graph, guiding random testing so as to generate a state transition event library; based on the state transition event library, generating a test case pool by adopting a permutation and combination strategy; and selecting a test case from the test case pool, and executing a semi-random automatic test on the Android local library function. According to the invention, the pertinence, the coverage rate and the efficiency of the test can be obviously improved.

The invention relates to the field of quantum key distribution, and discloses a key distribution anti-attack method and system based on decoy state coding and an irrelevant protocol, and the method comprises the steps: Alice generates a signal state quantum pulse and a three-intensity decoy state quantum pulse in a mixed manner, and transmits and monitors channel parameters in real time through a quantum channel; bob randomly selects a measurement base for measurement, records original data and delays to obtain a state type identifier; the Charlie transmits a random test state, collects Bell inequality verification parameters, and implements equipment-independent security verification; the two parties screen matched data through base comparison, evaluate channel security and correct a signal state bit error rate by using a decoy state bit error rate; and based on the screened keys, a Toeplitz matrix negotiation protocol is adopted for compression to generate a final key, 10% of the keys are randomly extracted for cross validation, and after the cross validation is passed, the keys are stored, and the decoy state strength and the measurement base group parameters are updated. According to the method, an Alice, Bob and Charlie three-party system is constructed to form an iterative security closed loop, attack is comprehensively resisted, and a security key is generated.

Methods, systems, and apparatus, including computer-readable storage media for testing features of a database management system (DBMS). A DBMS testing framework generates new random test cases for testing database features on the system. The framework receives a query grammar specifying the structure of queries to generate and generates the queries randomly. The framework executes the queries with database features randomly enabled or disabled and generates performance data from the results of executing those queries. The framework identifies points of failure in the performance data, corresponding to instances in which queries executed with certain combinations of database features result in incorrect output, or degraded performance relative to executing the queries without the database features enabled. The testing framework divides the database preparation, query generation, and query execution parts of a test pipeline into separate components, which can be modified separately or left to proceed in a default operating mode.

The application discloses a random test case generation method. The method comprises the following steps: generating at least one random factor, and acquiring a current test step in a plurality of type step libraries matched with a test object according to the value of each random factor; if the current test step satisfies a legality condition according to a generated test step set, the current test step is added to the generated test step set; returning to the operation of generating at least one random factor until the number of test steps in the generated test step set reaches a target number threshold; and constructing at least one random test case according to the generated test step set at the end of the cycle. Through the above technical scheme, the test case of the random scene can be automatically generated according to the test requirement, and the coverage of the test is effectively improved.

This application provides an asynchronous communication management method, apparatus, electronic device, and storage medium, relating to the field of chip design and manufacturing technology. The method includes: modifying the instruction count and / or data volume count in the memory barrier data block of the asynchronous communication unit based on instructions sent by the asynchronous communication unit; and modifying the status bits in the memory barrier data block of the asynchronous communication unit when the instruction count and data volume count meet preset conditions. The method and apparatus provided by this application not only manage the synchronization state between producers and consumers based on memory barriers, ensuring the consistency and correctness of data exchanged between producers and consumers, but also abstract the complex count update and status judgment logic from specific test cases, forming a general asynchronous communication management mechanism that can be implemented by a dedicated memory barrier controller, supports random testing, and improves the flexibility of test verification.

The present invention discloses a method for regression of chip random test cases, comprising the following steps: setting the random number of each test case, and generating the corresponding number of seeded test cases for each test case; sequentially submitting all the seeded test cases of each test case for testing based on a preset maximum number of runs; in response to detecting that a certain seeded test case fails the test, stopping submitting other unsubmitted seeded test cases generated by its corresponding test case for testing; and obtaining the failure reason of the failed seeded test case and retesting the failed seeded test case based on a preset policy. The present invention also discloses a device for regression of chip random test cases, a computer device, and a readable storage medium. The present invention performs random testing of random test cases for a fixed number of times, without the need for users to learn additionally and with simpler operations; the input content is simplified and clear, and the result file is explicit, and a better handling method is also proposed for the situation after the test case fails.

Embodiments of the present application disclose an application program testing method and device, electronic equipment and storage medium. The method comprises: obtaining a first test duration of a random test mode; according to a graph of a to-be-tested application program, executing a segment corresponding to a control in a page of the to-be-tested application program by the random test mode, recording a first segment and a first page that have been executed, obtaining a test result of the first segment, until the test duration of the random test mode reaches the first test duration; the segment is test content corresponding to the control; according to the graph, the first segment and the first page, determining a second segment that has not been executed and a second page where the second segment is located; according to the second page, executing the second segment by a traversal test mode, and obtaining a test result of the second segment. The embodiments of the present application can improve test efficiency and software quality of the application program.

The invention discloses a simulation test method, device and equipment of an urban rail system and a storage medium, and relates to the field of electrical digital data processing, the method adopts a JSON configuration file to integrate rail topology and kinetic parameters, converts operation data through an OPC-UA server, realizes data intercommunication of heterogeneous systems through a preset JSON format, and improves compatibility; a Unity3D engine is used for building an equal-proportion digital model, the position and operation data of a train are mapped in real time, the visual limitation of traditional two-dimensional simulation is broken through, and system response of complex scenes such as high-density traffic flow and sudden failures can be observed conveniently; a multi-objective function is defined based on an operation strategy, a comprehensive optimal scheme is automatically output through a Pareto optimal solution set, the randomness defect that a traditional method depends on manual repeated testing is avoided, and the testing efficiency and decision scientificity are improved. Multi-train analogue simulation is realized, and the potential problems of interface fragmentation, insufficient scene visualization and low random test efficiency are solved.

The invention discloses a vehicle-mounted multi-source signal cloud test method, system and device, and relates to the technical field of vehicle-mounted electronic testing, and the method comprises the steps: obtaining a platform collection list, so as to generate a plurality of groups of random test data file information; constructing a DDS service simulation environment, and generating a corresponding signal sending sequence script and a reference data recording script according to each group of random test data files; based on a DDS service simulation environment, calling a signal sending sequence script and a reference data recording script, injecting signals according to a sequence, and recording reference data to a reference data file at the same time; and receiving and analyzing the cloud log collected by the vehicle end according to the collection strategy of the platform collection list to generate a result data file, and comparing the reference data file with the result data file to generate a test result. According to the invention, cloud testing of multi-source signals is realized, the coverage rate and efficiency of vehicle-mounted signal testing are greatly improved, the testing cost is reduced, and the problem of multi-source signal collaborative testing is solved.

The invention discloses a dynamic simulation execution extension and verification method for an instruction. The method comprises the following steps: 1) acquiring instruction semantic data of a target processor and defining a group of metamorphic relationships; 2) generating an instruction semantic function based on the instruction semantic information as a reference model; 3) generating a random test case based on the reference model; 4) mining a metamorphic relation of the instruction by using a large model; 5) formalizing each metamorphic relation into a logic constraint, and verifying whether the reference model conforms to the metamorphic relation or not; if the verification is passed, confirming that the corresponding metamorphic relationship is valid; if a counter example occurs, rejecting an unestablished metamorphic relationship; the method comprises the steps of (1) verifying a random test relation and a metamorphic relation, (2) generating a metamorphic test case based on each verified metamorphic relation, (7) completing simulation implementation of an instruction function according to an instruction semantic assembly interface, (8) executing the generated random test and metamorphic test cases and comparing an execution result with output of a reference model, if the execution result is inconsistent with the output of the reference model, readjusting instruction implementation, and otherwise, completing verification.

The application discloses a simulation test method, device and equipment of a city rail system and a storage medium, relates to the field of electric digital data processing, and integrates track topology and dynamic parameters by using a JSON configuration file, converts operation data through an OPC-UA server, realizes heterogeneous system data intercommunication through a preset JSON format, and improves compatibility; a Unity3D engine is used to build a digital model with the same proportion, real-time mapping of train position and operation data is realized, the visual limitation of traditional two-dimensional simulation is broken, and system response to complex scenes such as high-density traffic and sudden faults can be observed; a multi-objective function is defined based on an operation strategy, a comprehensive optimal scheme is automatically output through a Pareto optimal solution set, the randomness defect of traditional methods depending on artificial repeated testing is avoided, and the test efficiency and decision scientificity are improved. Multi-train simulation is realized, and potential problems such as interface fragmentation, insufficient scene visualization and inefficient random testing are solved.

The technology described herein provides an automated software testing platform that functions in an undefined action space. The techniques described herein begin from an undefined action space, but begin to understand the action space through random exploration. The actions taken during the test and the resultant status may both be communicated to a centralized test service. The techniques described herein also mine action telemetry data and status telemetry data to identify an action pattern that produces the sought result. Once multiple action modes are identified and at least a partial model of the action space is constructed, the test on the test machine can be divided into a random test mode, a replay test mode, and a pioneering test mode.

The invention discloses a test case generation method and device, equipment and a computer storage medium. The method comprises the steps of performing static analysis on a to-be-tested program to obtain program structure information; executing an initial test based on the program structure information, and collecting initial coverage information; selecting a target path from the to-be-covered path set based on a dynamic evaluation mechanism and the initial coverage information; performing symbolization processing on the target path, generating a path constraint and performing constraint solution; when constraint solving succeeds, generating a test case covering the target path; and when the constraint solution fails, generating a guide signal based on the unsuccessfully solved part, and executing a guide type search based on the guide signal to generate a test case covering the target path. According to the method, the problems that complex branches are difficult to cover due to low random test efficiency, symbolic execution path explosion and constraint solution are difficult, a search technology is easy to fall into local optimum, and initial exploration efficiency is low can be solved, and test case generation efficiency and path coverage capability are improved.

The invention relates to a PCIe bus test verification system, which is characterized in that an excitation generator generates a corresponding random test sequence according to the specific content of a test case; the driving module packages or encodes the random test sequences into corresponding signals or levels according to transaction types of the random test sequences, and sends the signals or levels to the PCIe module to be verified from different interfaces; the PCIe reference model serves as a control group of the to-be-verified PCIe module, excitation input to the to-be-verified PCIe module is synchronously input to the PCIe reference model to be processed, and output data are sent to the comparator; the monitoring module monitors a port level signal of the to-be-verified PCIe module, converts the output of the to-be-verified PCIe module into a test result transaction and sends the test result transaction to the comparator; the comparator collects test result transaction data, calls a result output by the PCIe reference model for real-time comparison, and judges the function operation condition of the to-be-verified PCIe module; and the function coverage rate module summarizes verification results of the comparators, and counts the coverage rate by sampling function coverage points to obtain a final verification result.

Hardware errors can be detected by generating a plurality of test templates to perform testing on an integrated circuit (IC) device. A set of random tests can be generated corresponding to the plurality of test templates. The set of random tests can be executed on the IC device for multiple passes, and the results of the multiple passes can be compared to detect the hardware error in the IC device. The set of random tests can be generated as a binary image for execution on the IC device. The IC device may include multiple processing cores, and executing the multiple passes may include changing logical role of each processing core between subsequent passes. The set of random tests can be executed in a bare-metal mode, or at an application level of the IC device.

This invention provides a fully randomized testing method, apparatus, device, medium, and product for an SGPIO master module. The method involves simultaneously transmitting the SGPIO master module's configuration object to the APB driver component, the SGPIO driver component, and the SGPIO sampling component. If the APB bus write transaction is an SGPIO control register configuration transaction, the parallel write data from the APB bus is parsed to obtain configuration information. The configuration object of the SGPIO master module is modified according to the configuration information, enabling the SGPIO driver component or the SGPIO sampling component to promptly change the protocol mode. Multiple reference models for interrupt states are instantiated in the basic test class. In the test case component, the reference model is selected using an override mechanism based on the currently verified interrupt triggering method. By comparing the expected value and the actual value of the interrupt status register, fully randomized verification of the SGPIO master module's interrupt status register value can be achieved. This invention improves the comprehensiveness and effectiveness of SGPIO master module testing.

A computer system, computer readable storage medium, and computer-implemented method for retrograding an instruction stream to enhance random test generation. The method includes generating a test case for a design-under-test (DUT) comprising positioning one or more placeholder instructions in the test case. The method also includes identifying one or more benefiting instructions. The method further includes executing the test case by replacing the one or more placeholder instructions with one or more respective retrograding instructions. The one or more retrograding instructions influence the one or more benefiting instructions.