5 results about "Deterministic testing" patented technology

Disclosed is a fail-closed conformance control layer for machine-assisted decision artifacts. The system generates replay-verifiable receipts that commit to a canonical artifact digest, evidence and snapshot identifiers, assumptions, toolchain identifiers, and a policy pack identifier and policy version digest. A deterministic validator evaluates a receipt under the versioned policy pack to output PASS, FAIL, or HOLD with reason codes from a reason-code registry, including time-stamped modeled-variability codes. Downstream side effects are gated in a control path and permitted only on PASS; otherwise they are withheld or routed to remediation or human review. The system may emit portable conformance packs and revalidate receipts over time to detect drift and manage a certification lifecycle. Conformance suites with deterministic test vectors and expected validator outputs may certify validator implementations by issuing signed conformance certificates and publishing a certificate or certificate digest to a verifiable certificate registry for independent verification and procurement acceptance testing.

Systems and methods for state clearing of internal memory and flip-flops of a system using built-in test and scan circuitry are provided. A method includes a security processor: (1) fetching memory built-in self-test (MBIST) data and providing the MBIST data to an internal field-test (IFT) controller such that the IFT controller can drive the MBIST data via an IJTAG network to respective MBIST controllers, and (2) fetching scan data and providing the scan data to the IFT controller such that the IFT controller can drive the scan data via a scan network to respective embedded deterministic test (EDT) controllers. The method further includes each of the respective MBIST controllers state clearing respective internal memories by writing pertinent MBIST data into the respective internal memories. The method further includes each of the respective EDT controllers state clearing respective flip-flops by writing pertinent scan data into the respective flip-flops.

A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; and a test response compactor configured to compact the test responses, the test response compactor comprising: first X-masking circuitry configured to mask, based on first masking information, some of X bits in the test responses, the first masking information remaining the same while a test response for each of the test patterns is being shifted out, the first masking information being different for at least two of the test patterns; and second masking circuitry configured to mask, based on second masking information, rest of the X bits in the test responses.

This invention relates to the field of explosion-proof valve technology, specifically to a test circuit for energy storage explosion-proof valves. The energy storage explosion-proof valve test circuit provides a pure hardware logic automated testing scheme that uses only basic analog circuits and discrete components to achieve complex sequential control. It is specifically designed for one-click batch testing of the "push-reset" action performance of energy storage explosion-proof valves, pursuing ultimate determinism and reliability. The H-bridge motor drive main circuit, the first relay interlock circuit, the second relay interlock circuit, and the main control circuit are precisely coordinated through the mechanical / electrical actions of relays and self-locking push-button switches. This elevates the explosion-proof valve testing process from a simple "forward and reverse cycle" to a deterministic testing process with time-guaranteed operation, complete action, and safety interlocks. Furthermore, after one-click triggering, automatic power-off and reset are achieved without manual intervention, significantly reducing operational intensity and error rate, and improving the efficiency and safety of batch testing.

Systems and methods for state clearing of internal memory and flip-flops of a system using built-in test and scan circuitry are provided. A method includes a security processor: (1) fetching memory built-in self-test (MBIST) data and providing the MBIST data to an internal field-test (IFT) controller such that the IFT controller can drive the MBIST data via an IJTAG network to respective MBIST controllers, and (2) fetching scan data and providing the scan data to the IFT controller such that the IFT controller can drive the scan data via a scan network to respective embedded deterministic test (EDT) controllers. The method further includes each of the respective MBIST controllers state clearing respective internal memories by writing pertinent MBIST data into the respective internal memories. The method further includes each of the respective EDT controllers state clearing respective flip-flops by writing pertinent scan data into the respective flip-flops.