36 results about "Deterministic testing" patented technology

Software in an electronic device can be tested using a combination of random testing and deterministic testing. In various embodiments, deterministic tests can run for a prescribed duration and/or a prescribed number of iterations before and/or after random testing. Test results can be weighted using a metric representing an amount of code that was stressed during testing. This metric can be determined by tracking software code that is loaded into memory during testing.

A digital system having multiple clock domain, each including at least one edge-triggered device, such as a flip-flop, is structured to be submitted to scan testing. Each data path from one clock domain to another includes a latch that is operated by a test clock. During scan testing, when the digital system is logically reconfigured to form one or more scan chains for receiving a test vector, the latches are operated to ensure that the test vector is passed from one domain to another.

In one embodiment, an IC with an embedded processor core, peripheral devices, and associated multiple scan chains, is provided with microcode that implements an arithmetic pseudo-random number generator and an arithmetic deterministic test vector generator, when executed by the embedded processor core, generates 2-D pseudo-random and deterministic test vectors for testing the peripheral devices respectively. The IC is further provided with microcode that implements an arithmetic test response compactor, which when executed by the embedded processor core, compacts test responses of the peripheral devices into a signature. The IC further includes a test port register and microcode that implements a number of ABIST instructions.

A method and a system for generating prime numbers and testing for primality of an integer. This invention has applicability to “public key” and other encryption techniques that play an important role in the security of information technology and electronic commerce. Generation of prime numbers requires the step of testing the primality. The method includes a deterministic test for testing the primality of a number in polynomial time. The system comprises a random number generator and a primality tester. The random number generator generates a random number and the primality tester tests the primality of this random number. The primality tester can also be used independent of the random number generator. In such a case, the number whose primality is to be tested can be input via a user interface.

The invention relates to a method for compressing the test data of integrated circuit, belonging to integrated circuit technical field, in particular to a deterministic self-test test data compressor. The invention comprises a phase shifter, a response compressor, a linear feedback shift register with a first and a second xor network while the shift register is connected with the phase shift, a scanning tree and a weigh random signal generating logic unit while the scan forest is connected with the phase shift, the gating signal end of the scan forest is connected with the weight random signal generating logic unit, and the output of the scan forest is connected with the response compressor. The invention further provides a deterministic self-test test data compression method. The invention uses the weight random signal generating logic unit to control the frequency of special signal of the input signal of the scan forest, to improve the fault coverage rate into the false random self-test process, to reduce the test data memory space generated by deterministic test vector.

Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded deterministic test) environment are also disclosed.

A test apparatus is configured to perform non-determinative testing of equipment. The test apparatus comprises a test computer arranged to automatically execute a non determinative test regime under the control of a test application. A network simulator connected to the test computer is provided with communication circuitry operable to communicate with the equipment under test. The network simulator is configurable into different network states according to the non-determinative test regime, and the test application is operable to control the network simulator to transition between a plurality of different network states. Data about unscripted communications between the network simulator and the equipment under test is monitored and can be analyzed to reach a test verdict.

An apparatus for generating a deterministic test pattern is provided for a BIST having a scan chain, comprising the control bits storing devise for storing the number of a deterministic test pattern that is covered by a tap configuration; pattern counter devise for receiving the values stored in the control bits storing devise one by one and then counting the values backward; configuration counter devise for tracing the order of a current tap configuration and incrementing the order by 1 whenever the value of the pattern counter passes through 1; a decoder for constituting a phase shifting network depending on the value of the configuration counter devise and determining an input signal of an XOR gate depending on TapConn_i^(j); and a reconfigurable phase shifter for receiving the input signal from the decoder to constitute an actual phase shifter.

The invention discloses a re-sowing test plan based on a parallel folding counter; the re-sowing test plan is characterized in that a test set is doubly compressed by a linear feedback shifting register (LFSR) and a folding counter code; a tested circuit moved into a multi-scan link structure in parallel by a phase shifter and a parallel folding control circuit in the test process completes the test function. In the plan of the invention, the circuit scanning structure is not changed, and the original mono-scan serial input is transformed to be multi-scan parallel input which is suitable for a plurality of test modes like random test mode, deterministic test and mixed test mode and the like; the test data storage volumes needed by tests are reduced, and the test time is greatly saved.

Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

The invention relates to a comprehensive energy system energy use flexibility evaluation method and system. The method comprises the following steps: S1, establishing a comprehensive energy system mapping model based on physical characteristics of energy equipment and an energy network topology structure; s2, according to the historical operation data of the comprehensive energy system and the historical load data in the supply area, establishing an uncertainty test set of the supply end and the demand end, and generating energy demand and energy supply pairs of the demand end under all the test sets; s3, calculating the flexibility of different energy flows according to the generated energy demand and energy supply pair; and S4, determining the overall energy use flexibility of the comprehensive energy system based on a fuzzy analytic hierarchy process. According to the method, guidance can be provided for energy gradient utilization and operation scheduling optimization of the comprehensive energy system, interaction between the supply end and the demand end is enhanced, and adverse effects caused by system uncertainty are reduced.

The uncertainty fault diagnosis efficiency evaluation method for the complex electronic system is high in automation degree and accurate in conclusion, and the average diagnosis step number and the diagnosis cost can be reduced. According to the technical scheme, the method comprises the steps that an electronic system hierarchical framework, an FMEA result and a test point scheme serve as input, and an uncertainty fault-test dependency matrix (D matrix) of a system is constructed for three test types of absolute test, non-absolute test and uncertainty test; then, the influence of non-absolute testing on the detectable fault mode set is eliminated, and a fault detection rate index is calculated; then, the influence of non-absolute testing on the detectable fault mode set is eliminated, and a fault detection rate index is calculated; next, the influence of uncertainty on the isolatable fault mode set is eliminated, and the fault mode set isolated to 1, 2 and 3 external field replaceable units or modules (LRU/LRM) and a fault isolation rate index are obtained;.

A method and system for built-in self-testing for high-performance circuits, configured to generate and apply a test pattern to a circuit under test (CUT). A logic structure in communication with the CUT and a memory device generates a plurality of test seeds from a plurality of original test seeds, the generated test seeds and original test seeds defining a total test seed plurality and a subset deterministic test pattern plurality. A response suppression circuit suppresses test responses from the CUT if not generated responsive to a deterministic test seed of the deterministic test pattern plurality.

The invention relates to the technical field of large-scale digital integrated circuits, and provides a low-power-consumption certainty BIST based on single and double jump and a seed compression method thereof. In order to reduce test power consumption, a novel single and double jump unit and an ROM control signal are applied to generate a certainty seed through single and double hybrid jump, and then certainty test vectors are generated by utilizing a single jump reseeding technology. Meanwhile, the generation number of the certainty test vectors in the reseeding process is constrained by additional arrangement of a 2-bit subtracting counter so as to reduce the number of redundant vectors and reduce test time. Besides, the corresponding seed compression method is also put forward so as to compress area overhead and generate the control signal. The experiment result proves that the test performance, such as test time, the area overhead and test power consumption, of the BIST and the seed compression method can be reduced to a large extent.

Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.

Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.