The invention relates to a
verification and test integrated platform for a probe processor, and belongs to the technical field of processor
verification and test. A probe processor adopts a self-defined probe instruction and a special probe operator unit, and a traditional
verification and test mode is difficult to consider the requirements of module-level verification and
system-level test. The UVM
verification system, the test
system and the management module are integrated, and unified management of verification and test is achieved. The UVM
verification system is based on a UVM architecture, a virtual interface is associated with a to-be-tested unit (such as a probe operator, GPIO, UART and the like) of a probe processor through a forced binding mechanism, and module-level verification is achieved. The test
system is responsible for compiling test codes into
machine codes and loading the
machine codes to the probe processor by starting the read-only memory, and system-level test is executed by the probe processor. And the management module adopts an automatic script to realize intelligent switching between verification and test
modes, so that the probe processor is suitable for different test scenes, the
test efficiency is improved, and the environmental redundancy is reduced. According to the method, the
reusability of the
test case is improved, the test consistency is ensured, the
resource utilization rate is optimized, the
automation degree and efficiency of verification are improved, and the method is suitable for efficient verification and test of probe processors and similar architecture chips.