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9 results about "Automatic test pattern generation" patented technology
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ATPG (acronym for both Automatic Test Pattern Generation and Automatic Test Pattern Generator) is an electronic design automation method/technology used to find an input (or test) sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. The generated patterns are used to test semiconductor devices after manufacture, or to assist with determining the cause of failure (failure analysis). The effectiveness of ATPG is measured by the number of modeled defects, or fault models, detectable and by the number of generated patterns. These metrics generally indicate test quality (higher with more fault detections) and test application time (higher with more patterns). ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test (full scan, synchronous sequential, or asynchronous sequential), the level of abstraction used to represent the circuit under test (gate, register-transfer, switch), and the required test quality.
SYSTEMS AND METHODS FOR AUTOMATIC TEST PATTERN GENERATION ON MULTIPLE STORAGE UNITS IN PARALLEL
Systems and procedures can perform sequential automatic test pattern generation (on parallel memory units). In one example, an array of logic gates (330-335) can output enable signals to cause multiple memory units (360, 361) to be enabled in parallel. The test pattern generation and test control logic (210) can perform forward path checking, backward path checking, and any other suitable check on the enabled memory units (360, 361). The systems and procedures can then move on to another group of memory units, enabling and testing them in parallel.
Owner:TEXAS INSTRUMENTS INC
Generating device for scan capture constraint and generating method thereof
PendingUS20260010669A1Geometric CADSpecial data processing applicationsAlgorithmAutomatic test pattern generation
A generating device and a generating method for scan capture constraint are provided. The generating method for scan capture constraint includes: performing a clock mapping operation according to clock information, a netlist, and first function constraint information to generate a clock mapping report; performing a timing constraint generating operation according to the first function constraint information, the clock mapping report, and a wrapper cell report to generate scan timing constraint information; and performing an automatic test pattern generation constraint generating operation according to the scan timing constraint information, a hard macro instance list, and test mode configuration information to generate automatic test pattern constraint information.
Owner:GLOBAL UNICHIP CORPORATION +1
Systems and methods to perform automatic test pattern generation on multiple memory units in parallel
Systems and methods may perform sequential automatic test pattern generation (ATPG) on parallel memory units. A first array of logic gates may output enable signals to cause multiple memory units to be enabled in parallel. Test pattern generation and test control logic may perform forward path testing, backward path testing, and any other appropriate testing on the enabled memory units. The systems and methods may then move on to another group of memory units, which are enabled in parallel and tested in parallel.
Owner:TEXAS INSTRUMENTS INC
Integrated circuit component diagnosis using real-time sensor-based violation information
Information pertaining to real-time sensor-based violations occurring during field operation of a failing integrated circuit component is used in conjunction with transition delay automatic test pattern generation (ATPG) test result information to diagnose the failing integrated circuit component. Real-time sensor-based violations can be captured during field operation at the integrated circuit component, with a sensor-based violation indicating that a sensor value generated by a sensor of the integrated circuit (such as a path margin monitor, temperature monitor, or voltage droop monitor) exceeds a sensor threshold value. Diagnosis of a failing integrated circuit component using real-time sensor-based violation information and transition delay ATPG test result information can aid in identifying a culprit path in the integrated circuit component that is likely responsible for causing the integrated circuit component failure.
Owner:INTEL CORP
Automatic test pattern generation to increase coverage in detecting defects in analog circuits
ActiveUS12626043B2Analog circuit testingComputer aided designHemt circuitsAutomatic test pattern generation
Owner:SYNOPSYS INC
Scanning capture limit generation device and generation method thereof
PendingCN121279207AComputer aided designSpecial data processing applicationsComputer hardwareAutomatic test pattern generation
The invention provides an apparatus and a method for generating a scan capture limit. The generation method of the scan capture limit comprises the following steps: executing a clock corresponding action according to clock information, a netlist and first function limit information to generate a clock mapping report; executing a timing limit generation action according to the first function limit information, the clock mapping report and the packaging unit report to generate scanning timing limit information; and performing an automatic test pattern generation restriction generation action according to the scan timing restriction information, the hardcore table and the test mode configuration information to generate automatic test pattern restriction information.
Owner:GLOBAL UNICHIP CORPORATION +1
System and method for performing automatic test pattern generation in parallel on multiple memory cells
Systems and methods may perform sequential automatic test pattern generation on parallel memory cells. In one example, an array of logic gates (330 to 335) may output enable signals to cause multiple memory cells (360, 361) to be enabled in parallel. The test pattern generation and test control logic (210) may perform a forward path test, a backward path test, and any other suitable test on the enabled memory cells (360, 361). The systems and methods may then be moved to another set of memory cells that are enabled in parallel and tested in parallel.
Owner:TEXAS INSTRUMENTS INC
Integrated circuit component diagnostics using real-time sensor-based violation information
Information relating to real-time sensor-based violations occurring during field operation of a failed integrated circuit component is used in conjunction with transition delay automatic test pattern generation (ATPG) test result information to diagnose the failed integrated circuit component. During field operation at an integrated circuit component, a real-time sensor-based violation may be captured, where the sensor-based violation indicates that a sensor value generated by a sensor of the integrated circuit, such as a path margin monitor, a temperature monitor, or a voltage droop monitor, exceeds a sensor threshold. Using real-time sensor-based violation information and transition delay ATPG test result information to diagnose a failed integrated circuit component may help identify criminal paths in the integrated circuit component that are likely to cause failure of the integrated circuit component.
Owner:INTEL CORP
Automatic test pattern generation for analog and mixed-signal circuits
PendingUS20250363276A1Electrical testingCAD circuit designHemt circuitsAutomatic test pattern generation
A method comprising: applying pre-determined DC voltage values to analog inputs of an analog or mixed signal circuit design (710); applying a plurality of sets of bit values generated for scan-based structural testing of circuits manufactured based on the circuit design, one set during each of a plurality of consecutive time intervals, to inputs of one or more node-connecting devices coupled to or to be coupled to one or more selected internal nodes of the circuit design, to one or more selected digital inputs of the circuit design, or both (720); and performing a simulation of the circuit design to determine, for each set of bit values, expected test response bit values at outputs of one or more threshold-comparing convertors and at selected digital signal nodes if the circuit design has the selected digital signal nodes (730). These operations may be repeated on the circuit design with defects being injected.
Owner:SIEMENS INDUSTRY SOFTWARE INC