870 results about "Application time" patented technology

A communication manager for web-based applications receives indications of application time outs via a callback mechanism. During session initiation, the communication manager provides a termination address to an application along with a session ID. If the session times out due to inactivity, the application may signal the communication manager that the session ID is invalid by sending a message to the termination address. Alternatively, when a communication manager establishes communication sessions for several applications with a common external terminal, the communication manager may receive messages identifying terminal activity at one of the applications and may signal to the other applications to keep their sessions active.

An IR pulse is applied to a tag region B that is disposed at the upstream side of the ascending aorta relative to a tag region A at a timing with a second predetermined delay time TD2 (for example, 600 ms) from the application time of an IR pulse to the tag region A to thereby perform tagging. By this tagging, it is possible to suppress the MR signals derived from the substantial portions and the blood within the tag region B. Subsequently, an imaging scan is performed after a predetermined time lapse TIA (for example, 1200 ms) from the application time of the IR pulse to the tag region A or after a predetermined time lapse TIB (for example, 600 ms) from the application time of the IR pulse to the tag region B.

A multiprocessor computer system comprises multiple data processors, each with an internal clock for providing time stamps to application software. The processors take turns as synchronization masters. The present master transmits a “request” time stamp (indicating the time of transmission according to the local clock) to the other (“slave”) processors. Each slave processor responds by returning a “response” time stamp (indicating the time of transmission of the response according to the local slave clock) of its own along with the received request time stamp. The master calculates clock adjustment values from the time of receipt of the responses and the included time stamps. This allows asynchronous clocks to be synchronized so that application time stamps can be validly compared across processors.

Disclosed is an input device capable of decreasing the number of layers of a detecting portion to reduce manufacturing costs and easily deforming layers provided above a pressure sensitive detecting portion. A capacitance-type detecting portion that detects the contact position of a finger on the basis of a variation in capacitance is provided on a pressure sensitive detecting portion that includes a lower detection layer formed on a lower base sheet and an upper detection layer formed on an upper base sheet. A voltage is applied to the pressure sensitive detecting portion and the capacitance-type detecting portion such that the application times of the voltages do not overlap each other. Therefore, it is possible to prevent interference between the detection operations of the two detecting portions.

A fixing device, and an image forming method and an image forming apparatus using the fixing device. The fixing device includes an application unit to apply a foam-like fixing agent including a softener to particulates including a resin on a medium, the softener softening the particulates by at least partially dissolving or swelling the resin and a thickness control unit to control a layer thickness of the foam-like fixing agent such that an application time during which the foam-like fixing agent is applied to the particulates is not shorter than a penetration time required for the foam-like fixing agent to penetrate through a layer of the particulates to the medium.

The invention relates to a simplified fertilizer application method of wheat and corn crop rotation anniversary, which is changed into an anniversary fertilizer application method that fertilizer application is carried out twice in a wheat season and fertilizer application is carried out once in a corn season from a traditional habitual fertilizer application method that the fertilizer application is carried out twice or three times in a wheat season and fertilizer application is carried out more than twice in a corn season. Wheat slow release fertilizer and corn slow release fertilizer are applied on crops, which not only can plan and consider the nutrient requirement of the anniversary of two-crop crops and ensure dependable crop and increasing yield of the crops but also can simplify fertilizer application times to a great extend and save labor force.

A “medication communicator” chart is used as a teaching tool to educate patients and to schedule events corresponding to a prescribed medication regimen. The “medication communicator” chart includes a scheduling graph having the shape of a 12-hour or 24-hour analog clock. The scheduling graph is divided into regions corresponding to each hour of a day for scheduling event information. Fields, on the “medication communicator” chart, are receptive to labels communicating information corresponding to numerous medications in the medication regimen. Timing indicators may be applied to the regions of the scheduling graph to indicate consumption or application times of each of the medications.

A catalyst composition is applied to an interior of a hollow substrate. The composition is coated on the substrate by immersing the substrate into a vessel containing a bath of coating slurry. A vacuum is then applied to the partially immersed substrate. The intensity of the vacuum and its application time is sufficient to draw the coating slurry upwardly from the bath into each of a plurality of channels located in the interior of the hollow substrate. After removing the substrate from the bath, it is rotated 180°. A blast of pressurized air is applied at an intensity and for a time sufficient to distribute the coating slurry within the channels of the substrate to form a uniform coating profile therein.

The invention provides a method for judging memory leak, comprising the following steps of: when a function application memory is judged aiming at each function in a program, accumulating the memory capacity and the application times of the named function application; when a function release memory is judged, reducing the released memory capacity from the memory capacity of the named function accumulated application and reducing release memory times from accumulated application times; sequencing the memory capacity and the times of the function application in different names in a descending mode by using the memory capacity as priority; ensuring and outputting a level of a memory leak degree according to the memory capacity and the times of the function accumulated application in different names; in addition, the invention provides a system for realizing the method in order to sequence memory distribution and information release according to the memory application times and liberate a programmer from large fussy analytical work.

A simulator for accurately simulating a deterioration amount and a recovery amount of transistor characteristics, by which a semiconductor device can be designed with high reliability, and the method are provided. When a gate voltage of a negative level (a negative bias voltage) “Vg” is applied to a gate of the transistor, characteristics of the transistor are deteriorated. When application of the negative level gate voltage “Vg” is terminated (when applying a bias free voltage), the deteriorated transistor characteristics are recovered. In a deterioration period and a recovery period, a logarithm “log(t)” is obtained for an application time “t” of the gate voltage, a deterioration amount ΔP_D(t)=C_D+B_D·log(t) is calculated by using constants C_D and B_D depending on the negative bias voltage, a recovery amount ΔP_R(t)=C_R+B_R·log(t) is calculated by using constants C_R and B_R depending on the bias free voltage, and the deterioration amount (ΔP_D), the recovery amount (ΔP_R) and a basic deterioration amount (X_D) are summed up. Preferably, passage of time is divided, and a deterioration amount and a recovery amount are obtained for each time zone by using different deterioration and recovery functions for each time zone.

An organic electro-luminescence (EL) device including at least an emission layer between an anode and a cathode that are opposed to each other, including an anode buffer layer that is composed of an electrically conductive material and is provided between the anode and the emission layer, a cathode buffer layer that is composed of an electrically conductive material and is provided between the cathode and the emission layer, and a drive unit that applies a forward bias voltage and a reverse bias voltage that have opposite polarities to the anode and the cathode with setting application time periods of the forward bias voltage and the reverse bias voltage according to a luminance ratio of an image to be displayed.

A method of determining breeding status in animals by (a) determining a breeding event (cyclicity, mounting, pregnancy, open) time, (b) providing an estrus or other breeding event detection apparatus, (c) affixing the estrus detection apparatus at a predetermined location on a female animal at a predetermined application time prior to the breeding event time, and (d) monitoring the estrus detection apparatus for activation thereof. An indicator apparatus is provided for use in indicating when an animal is in estrus. The apparatus is configured to be affixed to the rump of an animal to detect and indicate when the animal has been mounted and, thus, when the animal is in estrus. The apparatus is affixed to the animal by an adhesive layer. Layered on the top surface of the adhesive layer is an indicator layer that is in turn covered with a floodcoat layer. The floodcoat layer is adapted for removal upon the mounting of the first animal by a second animal. Removal of the floodcoat layer exposes the indicator layer indicating that the first animal has been mounted, thereby indicating that the first animal is in heat. The floodcoat layer is highly visible and may be seen from a distance.

The invention relates to a tunnel supporting structure, and in particular to a tunnel supporting structure across an active fault. The tunnel supporting structure comprises a fault across section and common supporting sections connected with the two ends of the tunnel supporting structure, wherein the common supporting sections adopt combined lining structures; the fault across section is orderly provided with a secondary lining, a foam concrete layer, a primary lining, a first waterproof layer and a preliminary support from inside to outside along the radial direction of the tunnel; the primary support, the first waterproof layer and the primary lining form the combined lining structure. The tunnel supporting structure is capable of overcoming the problem of application time selection, and is safe and convenient to construct. The primary lining is capable of partially bearing stress generated by the fault due to creep; in the meantime, the foam concrete is capable of providing a displacement space and absorbing energy; finally, the secondary lining is used for forming safety stock of the structure and ensuring that the clearance is not affected by fault movement; the tunnel supporting structure is high in safety storage, and has excellent shock resistance and excellent ability of resisting damage caused by fault creep and fault movement.

In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a p⁺ polysilicon gate electrode and a p⁺ field plate electrode in a trench, which were fabricated according to common design techniques, it has been found that, under conditions where a negative gate bias is applied continuously at high temperature with respect to the substrate, an absolute value of threshold voltage tends to increase steeply after the lapse of a certain period of stress application time. To solve this problem, the present invention provides a p-channel power MOSFET having an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode in each trench part thereof.