P-channel power mosfet

Abstract

In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a p+ polysilicon gate electrode and a p+ field plate electrode in a trench, which were fabricated according to common design techniques, it has been found that, under conditions where a negative gate bias is applied continuously at high temperature with respect to the substrate, an absolute value of threshold voltage tends to increase steeply after the lapse of a certain period of stress application time. To solve this problem, the present invention provides a p-channel power MOSFET having an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode in each trench part thereof.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The disclosure of Japanese Patent Application No. 2010-46452 filed on Mar. 3, 2010 including the specification, drawings and abstract is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates to semiconductor devices, and more particularly to a semiconductor integrated circuit device technique that is effectively applicable to a MOSFET device.[0003]In Japanese Unexamined Patent Publication No. 2006-202931 (Patent Document 1) or U.S. Patent Application Publication No. 2006-157779 (Patent Document 2) corresponding thereto, there is disclosed an n-channel MOSFET wherein a field plate electrode is disposed under an ordinary trench gate electrode.Related Art References—Patent Documents:[0004]Patent Document 1:[0005]Japanese Unexamined Patent Publication No. 2006-202931[0006]Patent Document 2:[0007]U.S. Patent Application Publication No. 2006-157779SUMMARY OF THE INVENTION[0008]In the eng...

AI Technical Summary

Benefits of technology

[0010]It is therefore an object of the present invention to provide a p-channel power MOSFET having higher reliability in performance.

[0014]To sum up, the following advantageous effect is provided according to the representative aspects of the present invention:

[0015]A p-channel power MOSFET configured to have an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode in each trench thereof in accordance with the present invention is capable of providing the advantageous effect of significantly reducing the degree of deterioration with time in terms of threshold voltage (Vth).

Problems solved by technology

In characteristic test measurements of these double-gate-in-trench p-channel power MOSFETs each having a p+ polysilicon gate electrode and a p+ field plate electrode in a trench, it has been found that there are disadvantageous problems in comparison with the n-channel power MOSFET structure concerned.

More specifically, in a gate bias stress test, a poor reliability condition such as NBTI (negative bias temperature instability) took place in the above p-channel power MOSFETs while no problematic condition was encountered in the n-channel device design.

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