322 results about "Polysilicon gate" patented technology

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide plane MOS device polysilicon gate self-alignment process and a low resistance structure, the silicon carbide plane MOS device polysilicon gate self-alignment process comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, and the N drift layer comprises a drain electrode, a source electrode and a grid electrode. The height of the P well layer in the single MOS cell is aligned with that of the grid electrode, and the P well layer is located on the left side and the right side of the grid electrode; the N well layer and the P + layer are both located above the grid electrode and the P well layer, and the P + layer is located on the outer side of the N well layer. According to the invention, the height of the P well layer is accurately aligned with the grid electrode, the P well layer is arranged at the two sides of the grid electrode, the design of the T-shaped source electrode is combined, the conduction path is optimized, and when the voltage is applied to the grid electrode, vertical channels are formed at the two sides of the P well layer, so that the path of current flowing from the drain electrode to the source electrode through the N drift layer is shorter and the distribution is uniform.

A method is provided for forming a light-shielding layer to block irradiation of light onto a light-sensitive storage region. The light-sensitive storage region is formed in a semiconductor substrate to store electric charges. A storage gate feature is formed over the light-sensitive storage region, and includes a polysilicon gate electrode that is disposed over the light-sensitive storage region. A metal layer is formed over the storage gate feature. A silicidation process is performed to transform a part of the metal layer that is in contact with the polysilicon gate electrode into a silicide light-shielding layer. A thermal process is performed to induce lateral growth of the silicide light-shielding layer to make the silicide light-shielding layer extend to cover a lateral surface of the storage gate feature. A process temperature of the thermal process is higher than that of the silicidation process.

The utility model provides a semiconductor device. The semiconductor device comprises a semiconductor substrate of a first conductive type; the deep well of the second conduction type is located in the semiconductor substrate; the shallow well of the first conductive type is located in the semiconductor substrate on the outer side of the deep well of the second conductive type; the JFET source electrode region, the drain electrode region and the LDMOS source electrode region are arranged at intervals; a field oxide layer, a JFET polysilicon gate and an LDMOS polysilicon gate, the field oxide layer is located in the deep trap of the second conduction type, and the JFET polysilicon gate and the LDMOS polysilicon gate are located on the field oxide layer; and the high-voltage well of the first conduction type comprises a first part and a second part, the first part is located in the deep well of the second conduction type between the JFET source region and the drain region, the second part is located in the deep well of the second conduction type between the drain region and the LDMOS polysilicon gate, and the second part is distributed in a polygonal matrix. The semiconductor device provided by the utility model can meet the performance requirements of the LDMOS and the JFET at the same time.

The invention discloses two-stage pressure regulation plasma etching cleaning equipment and a wafer processing method, the equipment comprises a main chamber, a remote plasma source, an auxiliary chamber, a vacuum pump, a first valve plate, a second valve plate and a flow limiting plate, and the flow limiting plate is provided with a flow limiting hole; a pressure difference foundation is laid through a flow limiting hole, flow fluctuation is dynamically compensated through cooperation of a second valve plate and a pressure regulating valve, millisecond-level precise control over the pressure of the double cavities can be achieved, and it can be guaranteed that efficient operation can be achieved in the two working modes; the wafer processing method aims at a polysilicon gate or a polysilicon-based structure, in the photoresist removing stage, free radicals react with etching residues, all reaction products are gaseous, and gaseous products can be pumped out by a vacuum pump; through the etching and degumming integrated synergistic process, the characteristics of the polycrystalline silicon material and the advantages of two-stage pressure regulation and control equipment are fully utilized, and the balance of efficiency, cost and environmental protection is realized while the process quality is guaranteed.

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

The invention discloses a contact hole forming method in a BCD and SGT integration process, and the method comprises the steps: S1, providing a substrate which comprises an SGT device region and a BCD device region; s2, performing an ion implantation process on the surface layer of the substrate to form source regions and a body lead-out region on the surface layer of the substrate in the SGT device region, and forming a substrate lead-out doped region, a body lead-out doped region, a source doped region and a drain doped region on the surface layer of the substrate in the BCD region, the source regions being located at two sides of the body lead-out region, the body lead-out doped region being located at two sides of the body lead-out region, the source doped region being located at two sides of the body lead-out region, and the drain doped region being located at two sides of the body lead-out region; the source region and the body lead-out region form a common connection structure; s3, forming a polycrystalline silicon gate structure on the surface of the substrate in the BCD device area; s4, forming a dielectric layer on the surface of the substrate, wherein the dielectric layer covers the polycrystalline silicon gate structure; and S5, simultaneously forming a contact hole of the SGT device and a contact hole of the BCD device in the dielectric layer. According to the scheme, the forming efficiency of the contact hole in the BCD and SGT integrated device can be improved.

The invention provides a manufacturing method of a separation gate semiconductor device, which comprises the following steps of: providing a wafer with a back sealing layer, and the back sealing layer comprises an inner polycrystalline silicon layer, a middle oxide layer and an outer polycrystalline silicon layer which are superposed in sequence; forming a groove from the front surface of the wafer; forming a sacrificial oxide layer on the inner wall of the groove, and removing the sacrificial oxide layer by wet etching; a trench gate structure is formed in the trench, the trench gate structure comprises a shield gate oxide layer, shield gate polycrystalline silicon, a gate oxide layer and gate polycrystalline silicon which are formed in sequence, a first oxide layer, a first polycrystalline silicon layer, a second oxide layer and a second polycrystalline silicon layer are accumulated on the back face of the wafer in sequence, and the first oxide layer is combined on the surface of the outer polycrystalline silicon layer. According to the invention, the back sealing layer with a sandwich structure of polycrystalline silicon, an oxide layer and polycrystalline silicon is adopted, the oxide layer on the back surface is retained due to the blocking of the polycrystalline silicon on the outer layer in the subsequent wet etching process, the warping degree of the wafer in the technological process is integrally improved, and various risks caused by warping in the measurement / technological process are reduced.

The invention belongs to the technical field of semiconductors, and particularly relates to a method for improving the height difference of an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor), a semiconductor structure and a device, which comprises the following steps of: providing an intermediate product which comprises a PMOS region and an NMOS region, and forming a polycrystalline silicon gate structure and a first oxide layer covering the polycrystalline silicon gate structure on each of the PMOS region and the NMOS region, the polycrystalline silicon gate structure comprises a gate polycrystalline silicon layer, a hard mask layer, a silicon oxide layer and a silicon nitride layer which are sequentially formed from inside to outside; grinding the first oxide layer to enable the surface of the first oxide layer to be flush; thinning the remaining first oxide layer to expose the top of the silicon nitride layer; etching to remove the top of the silicon nitride layer and a part of the side wall so as to expose the top of the silicon oxide layer; and thinning the remaining first oxide layer, and removing the silicon oxide layer and the top of the hard mask layer until the top surface of the gate polycrystalline silicon layer is reached. According to the invention, the height difference between the NMOS region and the PMOS region is effectively reduced.

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body; the semiconductor body comprises a first surface and a second surface which are oppositely arranged, the semiconductor body further comprises a well region and a first region, the first surface is provided with a gate trench, and the gate trench extends into the semiconductor body from the first surface; the grid electrode is positioned in the grid electrode groove; the grid electrode comprises a polycrystalline silicon grid electrode layer, a metal grid electrode layer and a metal silicide grid electrode layer; the metal silicide gate layer is used for reducing the resistance value of the gate, and the metal gate layer is used for preventing metal in the metal silicide gate layer from diffusing to the polycrystalline silicon gate layer; the second insulating layer is positioned on one side of the gate far away from the semiconductor body; the vertical projection of the second insulating layer on the first surface covers the vertical projection of the gate on the first surface; the source electrode is positioned on the first surface; and a drain electrode located on the second surface. According to the invention, the problem of gate voltage delay is effectively solved.

According to the device structure for improving the switching speed and robustness of the SiC MOS device and the manufacturing method, an arc-shaped gate oxide layer which is locally thickened is selectively additionally arranged above a JFET area of a device cell, the total input capacitance is reduced by reducing the gate-drain capacitance, the switching speed is improved, and power consumption is reduced; meanwhile, the thickened JFET region gate oxide layer improves the gate oxide reliability and the single particle resistance, and the channel region gate oxide layer is kept thin so as to maintain low Ron. The key preparation method comprises two gate oxidation and polycrystalline silicon deposition processes: local oxidation is carried out in a JFET region, an arc-shaped polycrystalline silicon gate is formed, a main gate structure is formed through second overall oxidation, and doping distribution is regulated and controlled in combination with self-aligned injection, hard mask step-by-step treatment and a high-temperature activation process. According to the invention, low Ron, high switching speed and high robustness are taken into account, the method is suitable for SiC and Si-based MOS devices, and the performance and reliability of the devices are significantly improved.

The application provides an inverse-conducting insulated gate bipolar transistor and a preparation method thereof, and belongs to the technical field of power semiconductor devices, and comprises: a first groove is a gate groove, a second groove is an emitter groove, and a third groove is an ineffective gate groove; in the lateral direction parallel to the cell surface, the first groove, the second groove and the third groove are sequentially and spacedly arranged, and the first groove and the second groove are connected through a fourth groove, and the fourth groove is a gate groove; in the longitudinal direction, the second groove is located between two adjacent fourth grooves. The beneficial effects are as follows: the gate groove and the ineffective gate groove are connected through the lateral gate groove, the forward conduction voltage drop and the conduction loss of the device are reduced; the current channel is increased, the current distribution is more uniform, the heat loss is reduced, the reliability and the power density of the device are improved; the emitter groove is used for repeatedly arranging the polysilicon gate and the metal gate in the lateral and longitudinal directions, the regularly arranged diodes and Schottky diodes are formed, and the reverse diode current distribution is more uniform.

A semiconductor device comprises a substrate, a metal gate over the substrate, a poly gate over the substrate, and a source region and a drain region formed in the substrate. The poly gate is separated from the metal gate. The metal gate comprises a metal gate stack and first spacers on sidewalls of the metal gate stack, and the poly gate comprises a poly gate stack and second spacers on sidewalls of the poly gate stack. The poly gate is between the source region and the drain region.

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.

The invention discloses a composite cross discharge ESD device, which belongs to the technical field of semiconductors, and comprises a substrate, a first electrode, a second electrode, a third electrode and a fourth electrode, the SCR structure is distributed in the substrate in the Y direction, an intersection region is arranged between well regions of the SCR structure, and insulating media are arranged at the positions, adjacent to the well regions and the substrate, of the intersection region; and the at least one discharge unit is arranged in the insulating medium of the crossing region, the discharge unit comprises a first polysilicon gate region, a first N-type channel region, a P-type channel region, a second N-type channel region and a second polysilicon gate region which are sequentially arranged along the X direction, and the P-type channel region penetrates out of the insulating medium at two sides in the Y direction so as to be connected with the well region. By improving the structure of a traditional SCR device, on the basis that the area of the device is not increased, an NPN type composite channel region of a super junction structure is added, and therefore adjustable current distribution and parameter characteristics of the SCR device, ESD protection in a crossed multi-current direction and better unit area integration performance are achieved.

A semiconductor device comprises a semiconductor layer structure that comprises at least one wide bandgap semiconductor layer; a gate pad on the semiconductor layer structure; and a gate runner that is electrically connected to the gate pad, the gate runner comprising a polysilicon gate runner and a metal gate runner on the polysilicon gate runner opposite the semiconductor layer structure. A gap is provided in the metal gate runner above a first portion of the polysilicon gate runner, where the gap separates the metal gate runner into a first metal gate runner segment and a second metal gate runner segment or separates the first metal gate runner segment from the gate pad.

The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.

The application discloses a kind of bionic visual sensor devices with pulse coding capability.Light quantum reaches device, and photoelectron-hole pair will be generated.Light-generated carriers continue to collide with lattice atoms by the strong electric field force between cathode and anode, and new photoelectron-hole pair is generated.The process will be repeated in turn, and then macroscopic current is generated.Through external resistance voltage division, the electric field between cathode and anode is reduced, so that macroscopic current is quenched, thereby realizing the pulse current lasting several nanoseconds.After tens of nanoseconds, the device quickly recovers to the initial state, preparing for detecting the next light quantum.In addition, the inversion layer formed below the polysilicon gate can effectively regulate the wavelength response of the device, enabling it to have a biologically reasonable visual color perception ability.Meanwhile, the device is fully compatible with standard microelectronic technology, enabling large-scale integrated bionic visual sensors to meet the development needs of fields such as bionic robots.

The application discloses a super-junction LDMOS device with high-resistance substrate TSV grounding and a manufacturing method thereof. The super-junction LDMOS device comprises a high-resistance substrate, a body region and a drift region formed in the high-resistance substrate, a body region contact region and a source region formed in the body region, a polysilicon gate formed on a substrate surface above the body region, and a drain region formed in the drift region. The drift region comprises a super-junction structure formed by a first column region and a second column region arranged at intervals in a gate width direction. A first buffer layer is arranged between the first column region and the drain region, a second buffer layer is arranged between the second column region and the drain region, and the first buffer layer and the second buffer layer are arranged to surround the drain region. The super-junction LDMOS device can effectively suppress substrate auxiliary effect, can realize optimal design of device breakdown voltage and on-resistance, and can reduce output capacitance of the device.

A semiconductor structure includes a substrate and a contact field plate (CFP) on the substrate. The contact field plate includes an insulation layer on the substrate, a poly gate over the insulation layer, a first-type semiconductor doping region in the poly gate; and a second-type semiconductor doping region in the poly gate.

The present application discloses a dual-stage pressure-regulated plasma etching and cleaning equipment and a wafer processing method, wherein the equipment includes a main chamber, a remote plasma source, a sub-chamber, a vacuum pump, a first valve plate, a second valve plate and a flow limiting plate, wherein a flow limiting hole is provided on the flow limiting plate; the flow limiting hole lays the foundation for the pressure difference, and then cooperates with the second valve plate and the pressure regulating valve to dynamically compensate for the flow fluctuation, thereby achieving millisecond-level precise control of the dual-chamber pressure, and ensuring that both working modes can operate efficiently; the wafer processing method targets polysilicon gates or polysilicon-based structures, and in the degumming stage, free radicals react with etching residues, and the reaction products are all gaseous, which can be extracted by a vacuum pump; through this "etching and degumming integration" collaborative process, the characteristics of polysilicon materials and the advantages of the dual-stage pressure regulation equipment are fully utilized, while ensuring process quality, achieving a balance between efficiency, cost and environmental protection.

Disclosed in the present invention are a low-dielectric-absorption, low-mismatch, precision, linear MIM capacitor and integration technology. The integration technology comprises the integration steps of: 1) forming an active region and an isolation field oxide region; 2) forming a thick gate oxide layer and a thin gate oxide layer; 3) depositing a polysilicon layer and constructing a polysilicon gate of an MOS transistor; 4) completing photolithography and implantation of a source and a drain for a multi-gate oxide high-low voltage BiCMOS / CMOS; 5) improving the flatness of the lower surface region of a metal thin film resistor by means of chemical mechanical planarization; 6) sputtering a high-resistivity microcrystalline titanium thin film on a lower electrode of a metal MIM capacitor by means of a PVD method; 7) depositing a silicon nitride SixNyHz as a dielectric layer of the metal MIM capacitor by means of PECVD; 8) sputtering the high-resistivity microcrystalline titanium thin film on an upper electrode of the metal MIM capacitor by means of a PVD method; and 9) sputtering an aluminum-copper film layer and completing etching processing of a metal connection line. The present invention optimizes the problem of precision matching of metal MIM capacitors, improves the packaging function density and the device density of integrated circuits, and promotes the miniaturization and reduced form of high-performance integrated circuits.

The invention discloses a sectional type grid-control Darlington transistor device structure and a manufacturing method thereof. The sectional type grid-control Darlington transistor device structure comprises a substrate P-Sub; a first N-Drift region is arranged in the substrate P-Sub; a first NW region, a first PW region and a second PW region are arranged above the N-Drift region; a first P + injection region and a first N + injection region are arranged in the first NW region; a second N + injection region, a second P + injection region and a third N + injection region are sequentially arranged in the first PW region from left to right; a third P + injection region, a fourth N + injection region and a fourth P + injection region are arranged in the second PW region; a first polysilicon gate is arranged between the second field oxide isolation region and the second N + injection region; therefore, the MOS current is amplified through the current gain of the two-stage NPN transistor, and an outflow channel is provided for carriers stored in the drift region through the sectional anode structure, so that the rapid turn-off of the device is realized, and the grid-control bipolar device with high current density and low turn-off loss is formed.

The application belongs to the technical field of semiconductor, and particularly relates to a method for improving height difference between NMOS and PMOS, a semiconductor structure and a device, which comprises the following steps: providing an intermediate product comprising a PMOS region and an NMOS region, and forming a polysilicon gate structure and a first oxide layer covering the polysilicon gate structure on the PMOS region and the NMOS region, wherein the polysilicon gate structure comprises a gate polysilicon layer, a hard mask layer, a silicon oxide layer and a silicon nitride layer formed in sequence from inside to outside; grinding the first oxide layer so that the surface of the first oxide layer is flush; thinning the remaining first oxide layer to expose the top of the silicon nitride layer; etching the top of the silicon nitride layer and a part of the side wall to expose the top of the silicon oxide layer; thinning the remaining first oxide layer, and removing the top of the silicon oxide layer and the hard mask layer until the top surface of the gate polysilicon layer stops. The application effectively reduces the height difference between the NMOS region and the PMOS region.

Power semiconductor devices are provided. In one example, a power semiconductor device includes a semiconductor structure. The power semiconductor device further includes a polysilicon gate layer on the semiconductor structure in an inactive region of the semiconductor device. The power semiconductor device further includes a gate insulating pattern between the polysilicon gate layer and the semiconductor structure, the gate insulating pattern having a thickness such that a distance between the semiconductor in the inactive region and the polysilicon gate layer through the gate insulating pattern is less than about 100 nm. The power semiconductor device further includes a shunt contact structure on semiconductor structure in the inactive region. A gate insulating electric field across the gate insulating pattern associated with a displacement current is less than about 8 MV / cm.

The invention provides a semiconductor device and a manufacturing method thereof. In the semiconductor device, a first polycrystalline silicon grid electrode of a PMOS (P-channel Metal Oxide Semiconductor) transistor is provided with P-type doping, a second polycrystalline silicon grid electrode of an NMOS (N-channel Metal Oxide Semiconductor) transistor is provided with N-type doping, and the first polycrystalline silicon grid electrode and the second polycrystalline silicon grid electrode are not directly connected but are connected through a common conductive plug. Compared with the prior art, the diffusion of the grid doped ions of the NMOS transistor to the grid of the PMOS transistor can be avoided to a greater extent, and the problem of diffusion neutralization when the first polycrystalline silicon grid and the second polycrystalline silicon grid share the polycrystalline silicon strip is avoided; the risk of threshold voltage mismatch, device performance reduction and the like caused by ion diffusion is reduced, the heat treatment process does not need to be reduced, the injection dosage of N-type ions for the second polycrystalline silicon grid NG does not need to be reduced, the injection width of the N-type ions does not need to be reduced, and the device performance cannot be affected.

This invention belongs to the field of power semiconductor technology and relates to a trench-gate DMOS device with an asymmetric channel. Its cell structure includes a metallized drain, a heavily doped first conductivity type semiconductor substrate above the metallized drain, a lightly doped first conductivity type semiconductor epitaxial layer above the first conductivity type semiconductor substrate, and a second conductivity type semiconductor body region above the lightly doped first conductivity type semiconductor epitaxial layer. By employing an asymmetric structure, this invention forms a vertical channel on one side of the polysilicon gate and an L-shaped channel on the other side, resulting in a longer channel region for carrier flow. This increases the influence of mobility on the drain current temperature coefficient, allowing the device to enter the negative temperature characteristic range of current earlier and lowering the zero-temperature point of the drain current. Furthermore, the channel resistance of the device can be changed by adjusting the ratio of the L-shaped channel to the vertical channel.

The present application discloses a method for manufacturing a metal gate, comprising: step 1, providing a semiconductor substrate on which dummy polysilicon gates are formed, wherein a first gate dielectric layer is formed at the bottom of the dummy polysilicon gates, and a spacing region between the dummy polysilicon gates is filled with a zero interlayer dielectric; step 2, removing the dummy polysilicon gates, comprising: step 21, performing first dry etching to remove a part of the thickness of the dummy polysilicon gate; step 22, performing carbon ion implantation to form a carbon containing surface region of the zero interlayer dielectric; and step 23, performing second wet etching to fully remove the remaining dummy polysilicon gates; step 3, performing third etching to remove the first gate dielectric layer; and step 4, forming a second gate dielectric layer and a metal gate.

The invention provides a split-gate flash memory test method comprising the following steps: forming a gate structure on the surface of a part of an active region, the gate structure comprising a floating gate located on the surface of the active region, a first side wall located on the surface of the floating gate, a word line located between openings formed by the floating gate, and a second side wall separating the first side wall and the floating gate from the word line; sequentially forming a memory gate and gate polycrystalline silicon on the surface of the gate structure, wherein the gate polycrystalline silicon exposes part of the surface of the memory gate; forming a first through hole structure on the gate polysilicon, forming a second through hole structure on the exposed memory gate, and forming a third through hole structure on the exposed active region; and testing a first capacitance between the first through hole structure and the second through hole structure or a second capacitance between the second through hole structure and the third through hole structure, judging whether the first capacitance is within a first set value, judging whether the second capacitance is within a second set value, and judging whether the sum of the first capacitance and the second capacitance is within a third set value.

A semiconductor device includes a resistor having a resistor body including polysilicon, with fluorine in the polysilicon. The resistor body has a laterally alternating distribution of silicon grain sizes. The semiconductor device further includes an MOS transistor having a gate including polysilicon with fluorine. The fluorine in the gate has a higher average concentration than the fluorine in the resistor body. The semiconductor device may be formed by forming a gate / resistor layer including polysilicon. A fluorine implant mask is formed over the gate / resistor layer, exposing the gate / resistor layer in an area for the gate and over implant segments in an area for the resistor body. The implant segments do not cover the entire area for the resistor body. Fluorine is implanted into the gate / resistor layer where exposed by the fluorine implant mask. The gate / resistor layer is patterned to form the gate and the resistor body.