216 results about "Polysilicon gate" patented technology

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

The invention belongs to the technical field of semiconductors, and particularly relates to a method for improving the height difference of an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor), a semiconductor structure and a device, which comprises the following steps of: providing an intermediate product which comprises a PMOS region and an NMOS region, and forming a polycrystalline silicon gate structure and a first oxide layer covering the polycrystalline silicon gate structure on each of the PMOS region and the NMOS region, the polycrystalline silicon gate structure comprises a gate polycrystalline silicon layer, a hard mask layer, a silicon oxide layer and a silicon nitride layer which are sequentially formed from inside to outside; grinding the first oxide layer to enable the surface of the first oxide layer to be flush; thinning the remaining first oxide layer to expose the top of the silicon nitride layer; etching to remove the top of the silicon nitride layer and a part of the side wall so as to expose the top of the silicon oxide layer; and thinning the remaining first oxide layer, and removing the silicon oxide layer and the top of the hard mask layer until the top surface of the gate polycrystalline silicon layer is reached. According to the invention, the height difference between the NMOS region and the PMOS region is effectively reduced.

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body; the semiconductor body comprises a first surface and a second surface which are oppositely arranged, the semiconductor body further comprises a well region and a first region, the first surface is provided with a gate trench, and the gate trench extends into the semiconductor body from the first surface; the grid electrode is positioned in the grid electrode groove; the grid electrode comprises a polycrystalline silicon grid electrode layer, a metal grid electrode layer and a metal silicide grid electrode layer; the metal silicide gate layer is used for reducing the resistance value of the gate, and the metal gate layer is used for preventing metal in the metal silicide gate layer from diffusing to the polycrystalline silicon gate layer; the second insulating layer is positioned on one side of the gate far away from the semiconductor body; the vertical projection of the second insulating layer on the first surface covers the vertical projection of the gate on the first surface; the source electrode is positioned on the first surface; and a drain electrode located on the second surface. According to the invention, the problem of gate voltage delay is effectively solved.

According to the device structure for improving the switching speed and robustness of the SiC MOS device and the manufacturing method, an arc-shaped gate oxide layer which is locally thickened is selectively additionally arranged above a JFET area of a device cell, the total input capacitance is reduced by reducing the gate-drain capacitance, the switching speed is improved, and power consumption is reduced; meanwhile, the thickened JFET region gate oxide layer improves the gate oxide reliability and the single particle resistance, and the channel region gate oxide layer is kept thin so as to maintain low Ron. The key preparation method comprises two gate oxidation and polycrystalline silicon deposition processes: local oxidation is carried out in a JFET region, an arc-shaped polycrystalline silicon gate is formed, a main gate structure is formed through second overall oxidation, and doping distribution is regulated and controlled in combination with self-aligned injection, hard mask step-by-step treatment and a high-temperature activation process. According to the invention, low Ron, high switching speed and high robustness are taken into account, the method is suitable for SiC and Si-based MOS devices, and the performance and reliability of the devices are significantly improved.

The application provides an inverse-conducting insulated gate bipolar transistor and a preparation method thereof, and belongs to the technical field of power semiconductor devices, and comprises: a first groove is a gate groove, a second groove is an emitter groove, and a third groove is an ineffective gate groove; in the lateral direction parallel to the cell surface, the first groove, the second groove and the third groove are sequentially and spacedly arranged, and the first groove and the second groove are connected through a fourth groove, and the fourth groove is a gate groove; in the longitudinal direction, the second groove is located between two adjacent fourth grooves. The beneficial effects are as follows: the gate groove and the ineffective gate groove are connected through the lateral gate groove, the forward conduction voltage drop and the conduction loss of the device are reduced; the current channel is increased, the current distribution is more uniform, the heat loss is reduced, the reliability and the power density of the device are improved; the emitter groove is used for repeatedly arranging the polysilicon gate and the metal gate in the lateral and longitudinal directions, the regularly arranged diodes and Schottky diodes are formed, and the reverse diode current distribution is more uniform.

A semiconductor device comprises a substrate, a metal gate over the substrate, a poly gate over the substrate, and a source region and a drain region formed in the substrate. The poly gate is separated from the metal gate. The metal gate comprises a metal gate stack and first spacers on sidewalls of the metal gate stack, and the poly gate comprises a poly gate stack and second spacers on sidewalls of the poly gate stack. The poly gate is between the source region and the drain region.

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.

The invention discloses a composite cross discharge ESD device, which belongs to the technical field of semiconductors, and comprises a substrate, a first electrode, a second electrode, a third electrode and a fourth electrode, the SCR structure is distributed in the substrate in the Y direction, an intersection region is arranged between well regions of the SCR structure, and insulating media are arranged at the positions, adjacent to the well regions and the substrate, of the intersection region; and the at least one discharge unit is arranged in the insulating medium of the crossing region, the discharge unit comprises a first polysilicon gate region, a first N-type channel region, a P-type channel region, a second N-type channel region and a second polysilicon gate region which are sequentially arranged along the X direction, and the P-type channel region penetrates out of the insulating medium at two sides in the Y direction so as to be connected with the well region. By improving the structure of a traditional SCR device, on the basis that the area of the device is not increased, an NPN type composite channel region of a super junction structure is added, and therefore adjustable current distribution and parameter characteristics of the SCR device, ESD protection in a crossed multi-current direction and better unit area integration performance are achieved.

A semiconductor device comprises a semiconductor layer structure that comprises at least one wide bandgap semiconductor layer; a gate pad on the semiconductor layer structure; and a gate runner that is electrically connected to the gate pad, the gate runner comprising a polysilicon gate runner and a metal gate runner on the polysilicon gate runner opposite the semiconductor layer structure. A gap is provided in the metal gate runner above a first portion of the polysilicon gate runner, where the gap separates the metal gate runner into a first metal gate runner segment and a second metal gate runner segment or separates the first metal gate runner segment from the gate pad.

The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.

The application discloses a kind of bionic visual sensor devices with pulse coding capability.Light quantum reaches device, and photoelectron-hole pair will be generated.Light-generated carriers continue to collide with lattice atoms by the strong electric field force between cathode and anode, and new photoelectron-hole pair is generated.The process will be repeated in turn, and then macroscopic current is generated.Through external resistance voltage division, the electric field between cathode and anode is reduced, so that macroscopic current is quenched, thereby realizing the pulse current lasting several nanoseconds.After tens of nanoseconds, the device quickly recovers to the initial state, preparing for detecting the next light quantum.In addition, the inversion layer formed below the polysilicon gate can effectively regulate the wavelength response of the device, enabling it to have a biologically reasonable visual color perception ability.Meanwhile, the device is fully compatible with standard microelectronic technology, enabling large-scale integrated bionic visual sensors to meet the development needs of fields such as bionic robots.

The application discloses a super-junction LDMOS device with high-resistance substrate TSV grounding and a manufacturing method thereof. The super-junction LDMOS device comprises a high-resistance substrate, a body region and a drift region formed in the high-resistance substrate, a body region contact region and a source region formed in the body region, a polysilicon gate formed on a substrate surface above the body region, and a drain region formed in the drift region. The drift region comprises a super-junction structure formed by a first column region and a second column region arranged at intervals in a gate width direction. A first buffer layer is arranged between the first column region and the drain region, a second buffer layer is arranged between the second column region and the drain region, and the first buffer layer and the second buffer layer are arranged to surround the drain region. The super-junction LDMOS device can effectively suppress substrate auxiliary effect, can realize optimal design of device breakdown voltage and on-resistance, and can reduce output capacitance of the device.

A semiconductor structure includes a substrate and a contact field plate (CFP) on the substrate. The contact field plate includes an insulation layer on the substrate, a poly gate over the insulation layer, a first-type semiconductor doping region in the poly gate; and a second-type semiconductor doping region in the poly gate.

The present application discloses a dual-stage pressure-regulated plasma etching and cleaning equipment and a wafer processing method, wherein the equipment includes a main chamber, a remote plasma source, a sub-chamber, a vacuum pump, a first valve plate, a second valve plate and a flow limiting plate, wherein a flow limiting hole is provided on the flow limiting plate; the flow limiting hole lays the foundation for the pressure difference, and then cooperates with the second valve plate and the pressure regulating valve to dynamically compensate for the flow fluctuation, thereby achieving millisecond-level precise control of the dual-chamber pressure, and ensuring that both working modes can operate efficiently; the wafer processing method targets polysilicon gates or polysilicon-based structures, and in the degumming stage, free radicals react with etching residues, and the reaction products are all gaseous, which can be extracted by a vacuum pump; through this "etching and degumming integration" collaborative process, the characteristics of polysilicon materials and the advantages of the dual-stage pressure regulation equipment are fully utilized, while ensuring process quality, achieving a balance between efficiency, cost and environmental protection.

Disclosed in the present invention are a low-dielectric-absorption, low-mismatch, precision, linear MIM capacitor and integration technology. The integration technology comprises the integration steps of: 1) forming an active region and an isolation field oxide region; 2) forming a thick gate oxide layer and a thin gate oxide layer; 3) depositing a polysilicon layer and constructing a polysilicon gate of an MOS transistor; 4) completing photolithography and implantation of a source and a drain for a multi-gate oxide high-low voltage BiCMOS / CMOS; 5) improving the flatness of the lower surface region of a metal thin film resistor by means of chemical mechanical planarization; 6) sputtering a high-resistivity microcrystalline titanium thin film on a lower electrode of a metal MIM capacitor by means of a PVD method; 7) depositing a silicon nitride SixNyHz as a dielectric layer of the metal MIM capacitor by means of PECVD; 8) sputtering the high-resistivity microcrystalline titanium thin film on an upper electrode of the metal MIM capacitor by means of a PVD method; and 9) sputtering an aluminum-copper film layer and completing etching processing of a metal connection line. The present invention optimizes the problem of precision matching of metal MIM capacitors, improves the packaging function density and the device density of integrated circuits, and promotes the miniaturization and reduced form of high-performance integrated circuits.

The invention discloses a sectional type grid-control Darlington transistor device structure and a manufacturing method thereof. The sectional type grid-control Darlington transistor device structure comprises a substrate P-Sub; a first N-Drift region is arranged in the substrate P-Sub; a first NW region, a first PW region and a second PW region are arranged above the N-Drift region; a first P + injection region and a first N + injection region are arranged in the first NW region; a second N + injection region, a second P + injection region and a third N + injection region are sequentially arranged in the first PW region from left to right; a third P + injection region, a fourth N + injection region and a fourth P + injection region are arranged in the second PW region; a first polysilicon gate is arranged between the second field oxide isolation region and the second N + injection region; therefore, the MOS current is amplified through the current gain of the two-stage NPN transistor, and an outflow channel is provided for carriers stored in the drift region through the sectional anode structure, so that the rapid turn-off of the device is realized, and the grid-control bipolar device with high current density and low turn-off loss is formed.

The application belongs to the technical field of semiconductor, and particularly relates to a method for improving height difference between NMOS and PMOS, a semiconductor structure and a device, which comprises the following steps: providing an intermediate product comprising a PMOS region and an NMOS region, and forming a polysilicon gate structure and a first oxide layer covering the polysilicon gate structure on the PMOS region and the NMOS region, wherein the polysilicon gate structure comprises a gate polysilicon layer, a hard mask layer, a silicon oxide layer and a silicon nitride layer formed in sequence from inside to outside; grinding the first oxide layer so that the surface of the first oxide layer is flush; thinning the remaining first oxide layer to expose the top of the silicon nitride layer; etching the top of the silicon nitride layer and a part of the side wall to expose the top of the silicon oxide layer; thinning the remaining first oxide layer, and removing the top of the silicon oxide layer and the hard mask layer until the top surface of the gate polysilicon layer stops. The application effectively reduces the height difference between the NMOS region and the PMOS region.

This invention belongs to the field of power semiconductor technology and relates to a trench-gate DMOS device with an asymmetric channel. Its cell structure includes a metallized drain, a heavily doped first conductivity type semiconductor substrate above the metallized drain, a lightly doped first conductivity type semiconductor epitaxial layer above the first conductivity type semiconductor substrate, and a second conductivity type semiconductor body region above the lightly doped first conductivity type semiconductor epitaxial layer. By employing an asymmetric structure, this invention forms a vertical channel on one side of the polysilicon gate and an L-shaped channel on the other side, resulting in a longer channel region for carrier flow. This increases the influence of mobility on the drain current temperature coefficient, allowing the device to enter the negative temperature characteristic range of current earlier and lowering the zero-temperature point of the drain current. Furthermore, the channel resistance of the device can be changed by adjusting the ratio of the L-shaped channel to the vertical channel.

The present application discloses a method for manufacturing a metal gate, comprising: step 1, providing a semiconductor substrate on which dummy polysilicon gates are formed, wherein a first gate dielectric layer is formed at the bottom of the dummy polysilicon gates, and a spacing region between the dummy polysilicon gates is filled with a zero interlayer dielectric; step 2, removing the dummy polysilicon gates, comprising: step 21, performing first dry etching to remove a part of the thickness of the dummy polysilicon gate; step 22, performing carbon ion implantation to form a carbon containing surface region of the zero interlayer dielectric; and step 23, performing second wet etching to fully remove the remaining dummy polysilicon gates; step 3, performing third etching to remove the first gate dielectric layer; and step 4, forming a second gate dielectric layer and a metal gate.

A method for manufacturing a semiconductor device includes: forming a dummy poly gate on a common edge of a first oxide-definition region and a second oxide-definition region, the dummy poly gate covering a stack unit, and including two first portions and a second portion disposed between the two first portions in a first direction, the first portion having a width in a second direction transverse to the first direction, the second portion having a width in the second direction, the width of the second portion being larger than the width of the first portion; forming first and second source / drain features on the first and second oxide-definition regions, respectively; removing the second portion to form a first opening that exposes the stack unit; removing the stack unit to form a second opening in spatial communication with the first opening; and forming an isolation structure in the first and second openings.

This invention relates to the field of semiconductor power device manufacturing technology, and discloses a SiC MOSFET structure with etched gate and low input capacitance, and its manufacturing method. The structure includes an N-type SiC substrate with an N-type SiC drift layer; a P-well, a heavily doped P-well region, and a heavily doped N-region are disposed within the surface of the N-type SiC drift layer; a gate oxide layer is disposed on the surface, and a discrete polysilicon gate is disposed above the gate oxide layer. The discrete polysilicon gate has an etched window to remove the polysilicon material directly above the JFET region; the surface of the discrete polysilicon gate is covered with an interlayer insulating dielectric; a source electrode and a polysilicon gate connection line are disposed on the front side, and the polysilicon gate connection line electrically shorts the strip-shaped polysilicon gate units separated by etching; a drain electrode is disposed on the back side. This invention reduces the plate area and lowers the input capacitance and reverse transfer capacitance by removing the polysilicon directly above the JFET region; and avoids potential floating by shorting the separated gate with the connection line, thus reducing switching losses.

This invention discloses a gate interconnect structure and its fabrication method, as well as a semiconductor device and its fabrication method. The gate interconnect structure includes: a gate; a first insulating layer located on one side of the gate; the first insulating layer including a first groove exposing a portion of the gate; a barrier layer including a first barrier layer and a second barrier layer, the first barrier layer and the second barrier layer having the same lattice constant; the first barrier layer including a first grain boundary line extending from the side of the first barrier layer away from the gate to the side of the first barrier layer near the gate; the second barrier layer including a second grain boundary line extending from the side of the second barrier layer away from the gate to the side of the second barrier layer near the gate; the first grain boundary line and the second grain boundary line are staggered along a direction parallel to the gate; and a gate metal trace located on the side of the barrier layer away from the gate. This invention can solve the problem of aluminum atoms in the gate metal trace fusing with the polycrystalline silicon gate.

The present invention relates to the field of MOS semiconductor technology and discloses a self-aligned polysilicon gate process and low-resistance structure for a silicon carbide planar MOS device. The device comprises a plurality of juxtaposed MOS cells, each comprising a drain, a semiconductor epitaxial layer, a source, and a gate. The semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P+ layer, and a P well layer. The P well layer in a single MOS cell is aligned with the gate in height and is located on the left and right sides of the gate. The N well layer and the P+ layer are both located above the gate and the P well layer, with the P+ layer located outside the N well layer. The present invention optimizes the conduction path by precisely aligning the P well layer with the gate and placing it on both sides of the gate, combined with a "T"-shaped source design. When a voltage is applied to the gate, vertical channels are formed on both sides of the P well layer, making the path for current flowing from the drain through the N drift layer to the source shorter and more evenly distributed.

A manufacturing method of a power device having a dual polysilicon gate, including: forming a well in a substrate; forming a gate oxide layer; forming a polysilicon gate layer; forming a photo resist layer on the polysilicon gate layer to define a reduced surface field region, an enhanced drift region, and a field plate groove; etching the polysilicon gate layer to form the field plate groove; implanting a plurality of first and second conductivity type dopants in the substrate to form the reduced surface field region and the enhanced drift region; forming a field plate region in the field plate groove; forming another polysilicon gate layer which connects and overlays the polysilicon gate layer and the field plate region; and etching the polysilicon gate layers to form a first poly silicon gate region and a second poly silicon gate region, so as to form the dual polysilicon gate.

The invention provides a split-gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a heterojunction diode, relates to the technical field of MOSFET devices, and aims to more easily form an MOSFET device which is high in quality, low in conduction voltage drop and low in switching loss. The polycrystalline silicon region is deposited in the groove, and the split gate structure is arranged in the left upper groove and the right upper groove of the polycrystalline silicon region; a first doped region is arranged at the bottom of the groove, and the bottom of the polycrystalline silicon region is in contact with the first doped region; the split gate structure comprises a first gate oxide layer, a second gate oxide layer, a first polycrystalline silicon gate and a second polycrystalline silicon gate; the outer layers of the left side, the bottom and the right side of the first polycrystalline silicon gate are wrapped with first gate oxide layers, and the outer layers of the left side, the bottom and the right side of the second polycrystalline silicon gate are wrapped with second gate oxide layers. The invention has the advantages of low third quadrant turn-on voltage and low switching loss.

The invention provides a chip structure, a manufacturing method thereof and a vehicle. Specifically, the chip structure comprises a substrate layer and an N-type drift layer, the N-type drift layer is arranged on the upper surface of the substrate layer, at least a field oxide layer, a gate oxide layer, a polycrystalline silicon gate and an insulating medium layer are arranged on the upper surface of the N-type drift layer in a stacked mode, and a cellular structure is formed between the gate oxide layer and an N-type drift region of the N-type drift layer; the area where the cellular structure is located is provided with a first type of source electrode contact hole, the first type of source electrode contact hole penetrates from the insulating dielectric layer to the upper surface of the N-type drift layer, the insulating dielectric layer is provided with a grid electrode contact hole, and the grid electrode contact hole penetrates from the outer side of the insulating dielectric layer to the surface of the polycrystalline silicon grid electrode; and a second type source contact hole is arranged between the grid contact hole and the first type source contact hole. The problem that in the prior art, in the turn-off process of a SiC MOSFET chip, due to the fact that an energy escape path is too long, a source electrode contact hole is too hot is solved.

The application provides a planar silicon carbide MOSFET device and a manufacturing method thereof, and the device structure comprises an N+ substrate, an N-drift region, a P-well region with a buried layer, an N+ source region, a P+ source region, a current spreading layer, P-type polysilicon, gate medium, insulating medium, N-type polysilicon, a gate, a source and a drain. On the basis of a traditional planar MOSFET, a P-type buried layer connected with the source potential and P-type polysilicon are introduced, a low third quadrant conduction voltage drop is realized through a silicon-silicon carbide heterojunction, and the saturation conduction current of the device is reduced and the short circuit resistance time is improved through the introduced JFET region. In addition, due to the fact that the device adopts split gate and contains a P-type buried layer, the area of the gate and the drain is reduced, the Cgd of the device is improved, and the switching speed of the device is improved.

The application relates to the technical field of semiconductors, and particularly discloses a trench MOSFET device and a preparation method thereof, wherein the device comprises an N-type substrate, the N-type substrate sequentially has an N-type epitaxial layer, two Pwell regions and two inverted-trapezoidal trenches between the two Pwell regions from bottom to top; the Pwell region has an N+ region and a first P+ region, the N+ region and the first P+ region are located at the top of the Pwell region; one inclined edge of the inverted-trapezoidal trench is in contact with the corresponding Pwell region and N+ region; a gate oxide layer is deposited in the inverted-trapezoidal trench; the inverted-trapezoidal trench further has a polysilicon gate region, the polysilicon gate region is close to the corresponding Pwell region and N+ region; the inverted-trapezoidal trench further has a second P+ region; the second P+ regions have a Schottky contact region; the first P+ region and the top of the N+ region have a source ohmic contact region; the bottom of the N-type substrate has a drain ohmic contact region. The technical scheme can improve the reliability of the device and reduce power consumption.

A high voltage field effect transistor includes a thick silicon oxide gate dielectric and polysilicon gate electrode, while a low voltage field effect transistor includes a high dielectric constant metal oxide gate dielectric and a metallic gate electrode.