129 results about "Polysilicon gate" patented technology

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

The application provides an inverse-conducting insulated gate bipolar transistor and a preparation method thereof, and belongs to the technical field of power semiconductor devices, and comprises: a first groove is a gate groove, a second groove is an emitter groove, and a third groove is an ineffective gate groove; in the lateral direction parallel to the cell surface, the first groove, the second groove and the third groove are sequentially and spacedly arranged, and the first groove and the second groove are connected through a fourth groove, and the fourth groove is a gate groove; in the longitudinal direction, the second groove is located between two adjacent fourth grooves. The beneficial effects are as follows: the gate groove and the ineffective gate groove are connected through the lateral gate groove, the forward conduction voltage drop and the conduction loss of the device are reduced; the current channel is increased, the current distribution is more uniform, the heat loss is reduced, the reliability and the power density of the device are improved; the emitter groove is used for repeatedly arranging the polysilicon gate and the metal gate in the lateral and longitudinal directions, the regularly arranged diodes and Schottky diodes are formed, and the reverse diode current distribution is more uniform.

A semiconductor device comprises a substrate, a metal gate over the substrate, a poly gate over the substrate, and a source region and a drain region formed in the substrate. The poly gate is separated from the metal gate. The metal gate comprises a metal gate stack and first spacers on sidewalls of the metal gate stack, and the poly gate comprises a poly gate stack and second spacers on sidewalls of the poly gate stack. The poly gate is between the source region and the drain region.

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.

The invention discloses a composite cross discharge ESD device, which belongs to the technical field of semiconductors, and comprises a substrate, a first electrode, a second electrode, a third electrode and a fourth electrode, the SCR structure is distributed in the substrate in the Y direction, an intersection region is arranged between well regions of the SCR structure, and insulating media are arranged at the positions, adjacent to the well regions and the substrate, of the intersection region; and the at least one discharge unit is arranged in the insulating medium of the crossing region, the discharge unit comprises a first polysilicon gate region, a first N-type channel region, a P-type channel region, a second N-type channel region and a second polysilicon gate region which are sequentially arranged along the X direction, and the P-type channel region penetrates out of the insulating medium at two sides in the Y direction so as to be connected with the well region. By improving the structure of a traditional SCR device, on the basis that the area of the device is not increased, an NPN type composite channel region of a super junction structure is added, and therefore adjustable current distribution and parameter characteristics of the SCR device, ESD protection in a crossed multi-current direction and better unit area integration performance are achieved.

A semiconductor device comprises a semiconductor layer structure that comprises at least one wide bandgap semiconductor layer; a gate pad on the semiconductor layer structure; and a gate runner that is electrically connected to the gate pad, the gate runner comprising a polysilicon gate runner and a metal gate runner on the polysilicon gate runner opposite the semiconductor layer structure. A gap is provided in the metal gate runner above a first portion of the polysilicon gate runner, where the gap separates the metal gate runner into a first metal gate runner segment and a second metal gate runner segment or separates the first metal gate runner segment from the gate pad.

The application discloses a super-junction LDMOS device with high-resistance substrate TSV grounding and a manufacturing method thereof. The super-junction LDMOS device comprises a high-resistance substrate, a body region and a drift region formed in the high-resistance substrate, a body region contact region and a source region formed in the body region, a polysilicon gate formed on a substrate surface above the body region, and a drain region formed in the drift region. The drift region comprises a super-junction structure formed by a first column region and a second column region arranged at intervals in a gate width direction. A first buffer layer is arranged between the first column region and the drain region, a second buffer layer is arranged between the second column region and the drain region, and the first buffer layer and the second buffer layer are arranged to surround the drain region. The super-junction LDMOS device can effectively suppress substrate auxiliary effect, can realize optimal design of device breakdown voltage and on-resistance, and can reduce output capacitance of the device.

A semiconductor structure includes a substrate and a contact field plate (CFP) on the substrate. The contact field plate includes an insulation layer on the substrate, a poly gate over the insulation layer, a first-type semiconductor doping region in the poly gate; and a second-type semiconductor doping region in the poly gate.

Disclosed in the present invention are a low-dielectric-absorption, low-mismatch, precision, linear MIM capacitor and integration technology. The integration technology comprises the integration steps of: 1) forming an active region and an isolation field oxide region; 2) forming a thick gate oxide layer and a thin gate oxide layer; 3) depositing a polysilicon layer and constructing a polysilicon gate of an MOS transistor; 4) completing photolithography and implantation of a source and a drain for a multi-gate oxide high-low voltage BiCMOS / CMOS; 5) improving the flatness of the lower surface region of a metal thin film resistor by means of chemical mechanical planarization; 6) sputtering a high-resistivity microcrystalline titanium thin film on a lower electrode of a metal MIM capacitor by means of a PVD method; 7) depositing a silicon nitride SixNyHz as a dielectric layer of the metal MIM capacitor by means of PECVD; 8) sputtering the high-resistivity microcrystalline titanium thin film on an upper electrode of the metal MIM capacitor by means of a PVD method; and 9) sputtering an aluminum-copper film layer and completing etching processing of a metal connection line. The present invention optimizes the problem of precision matching of metal MIM capacitors, improves the packaging function density and the device density of integrated circuits, and promotes the miniaturization and reduced form of high-performance integrated circuits.

The invention discloses a sectional type grid-control Darlington transistor device structure and a manufacturing method thereof. The sectional type grid-control Darlington transistor device structure comprises a substrate P-Sub; a first N-Drift region is arranged in the substrate P-Sub; a first NW region, a first PW region and a second PW region are arranged above the N-Drift region; a first P + injection region and a first N + injection region are arranged in the first NW region; a second N + injection region, a second P + injection region and a third N + injection region are sequentially arranged in the first PW region from left to right; a third P + injection region, a fourth N + injection region and a fourth P + injection region are arranged in the second PW region; a first polysilicon gate is arranged between the second field oxide isolation region and the second N + injection region; therefore, the MOS current is amplified through the current gain of the two-stage NPN transistor, and an outflow channel is provided for carriers stored in the drift region through the sectional anode structure, so that the rapid turn-off of the device is realized, and the grid-control bipolar device with high current density and low turn-off loss is formed.

The application belongs to the technical field of semiconductor, and particularly relates to a method for improving height difference between NMOS and PMOS, a semiconductor structure and a device, which comprises the following steps: providing an intermediate product comprising a PMOS region and an NMOS region, and forming a polysilicon gate structure and a first oxide layer covering the polysilicon gate structure on the PMOS region and the NMOS region, wherein the polysilicon gate structure comprises a gate polysilicon layer, a hard mask layer, a silicon oxide layer and a silicon nitride layer formed in sequence from inside to outside; grinding the first oxide layer so that the surface of the first oxide layer is flush; thinning the remaining first oxide layer to expose the top of the silicon nitride layer; etching the top of the silicon nitride layer and a part of the side wall to expose the top of the silicon oxide layer; thinning the remaining first oxide layer, and removing the top of the silicon oxide layer and the hard mask layer until the top surface of the gate polysilicon layer stops. The application effectively reduces the height difference between the NMOS region and the PMOS region.

This invention belongs to the field of power semiconductor technology and relates to a trench-gate DMOS device with an asymmetric channel. Its cell structure includes a metallized drain, a heavily doped first conductivity type semiconductor substrate above the metallized drain, a lightly doped first conductivity type semiconductor epitaxial layer above the first conductivity type semiconductor substrate, and a second conductivity type semiconductor body region above the lightly doped first conductivity type semiconductor epitaxial layer. By employing an asymmetric structure, this invention forms a vertical channel on one side of the polysilicon gate and an L-shaped channel on the other side, resulting in a longer channel region for carrier flow. This increases the influence of mobility on the drain current temperature coefficient, allowing the device to enter the negative temperature characteristic range of current earlier and lowering the zero-temperature point of the drain current. Furthermore, the channel resistance of the device can be changed by adjusting the ratio of the L-shaped channel to the vertical channel.

This invention relates to the field of semiconductor power device manufacturing technology, and discloses a SiC MOSFET structure with etched gate and low input capacitance, and its manufacturing method. The structure includes an N-type SiC substrate with an N-type SiC drift layer; a P-well, a heavily doped P-well region, and a heavily doped N-region are disposed within the surface of the N-type SiC drift layer; a gate oxide layer is disposed on the surface, and a discrete polysilicon gate is disposed above the gate oxide layer. The discrete polysilicon gate has an etched window to remove the polysilicon material directly above the JFET region; the surface of the discrete polysilicon gate is covered with an interlayer insulating dielectric; a source electrode and a polysilicon gate connection line are disposed on the front side, and the polysilicon gate connection line electrically shorts the strip-shaped polysilicon gate units separated by etching; a drain electrode is disposed on the back side. This invention reduces the plate area and lowers the input capacitance and reverse transfer capacitance by removing the polysilicon directly above the JFET region; and avoids potential floating by shorting the separated gate with the connection line, thus reducing switching losses.

This invention discloses a gate interconnect structure and its fabrication method, as well as a semiconductor device and its fabrication method. The gate interconnect structure includes: a gate; a first insulating layer located on one side of the gate; the first insulating layer including a first groove exposing a portion of the gate; a barrier layer including a first barrier layer and a second barrier layer, the first barrier layer and the second barrier layer having the same lattice constant; the first barrier layer including a first grain boundary line extending from the side of the first barrier layer away from the gate to the side of the first barrier layer near the gate; the second barrier layer including a second grain boundary line extending from the side of the second barrier layer away from the gate to the side of the second barrier layer near the gate; the first grain boundary line and the second grain boundary line are staggered along a direction parallel to the gate; and a gate metal trace located on the side of the barrier layer away from the gate. This invention can solve the problem of aluminum atoms in the gate metal trace fusing with the polycrystalline silicon gate.

The invention provides a split-gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a heterojunction diode, relates to the technical field of MOSFET devices, and aims to more easily form an MOSFET device which is high in quality, low in conduction voltage drop and low in switching loss. The polycrystalline silicon region is deposited in the groove, and the split gate structure is arranged in the left upper groove and the right upper groove of the polycrystalline silicon region; a first doped region is arranged at the bottom of the groove, and the bottom of the polycrystalline silicon region is in contact with the first doped region; the split gate structure comprises a first gate oxide layer, a second gate oxide layer, a first polycrystalline silicon gate and a second polycrystalline silicon gate; the outer layers of the left side, the bottom and the right side of the first polycrystalline silicon gate are wrapped with first gate oxide layers, and the outer layers of the left side, the bottom and the right side of the second polycrystalline silicon gate are wrapped with second gate oxide layers. The invention has the advantages of low third quadrant turn-on voltage and low switching loss.

The application provides a planar silicon carbide MOSFET device and a manufacturing method thereof, and the device structure comprises an N+ substrate, an N-drift region, a P-well region with a buried layer, an N+ source region, a P+ source region, a current spreading layer, P-type polysilicon, gate medium, insulating medium, N-type polysilicon, a gate, a source and a drain. On the basis of a traditional planar MOSFET, a P-type buried layer connected with the source potential and P-type polysilicon are introduced, a low third quadrant conduction voltage drop is realized through a silicon-silicon carbide heterojunction, and the saturation conduction current of the device is reduced and the short circuit resistance time is improved through the introduced JFET region. In addition, due to the fact that the device adopts split gate and contains a P-type buried layer, the area of the gate and the drain is reduced, the Cgd of the device is improved, and the switching speed of the device is improved.

The invention relates to a PMOS (P-channel Metal Oxide Semiconductor) transistor and a manufacturing method thereof. According to the manufacturing method, after a first groove penetrating through a first dielectric layer is formed in a substrate, a first side wall and a gate dielectric layer are formed on the side wall of the first groove, then the first groove is filled with a polycrystalline silicon material layer, and the polycrystalline silicon material layer is etched to form a second groove in the top of the first groove; the remaining polycrystalline silicon material layer forms a polycrystalline silicon gate, then a hard mask layer is formed in the second groove to cover the upper surface of the polycrystalline silicon gate, then the first dielectric layer is removed, and a groove epitaxial process is carried out on the two sides of the polycrystalline silicon gate to form a source-drain epitaxial layer. The polycrystalline silicon grid electrode is protected by the first side wall and the hard mask layer, and epitaxial growth of the polycrystalline silicon grid electrode is avoided. The width of the polycrystalline silicon grid electrode is gradually reduced from top to bottom, so that the resistance of the metal silicide is reduced, the contact resistance of the grid electrode is reduced, and the performance of the PMOS transistor is improved.

The present application belongs to the technical field of power semiconductor, and relates to a trench gate MOSFET structure, which comprises a metallized drain, a heavily doped first-conductivity-type semiconductor substrate, a lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer, a first-conductivity-type semiconductor heavily doped source region I, a first-conductivity-type semiconductor heavily doped source region II, an interlayer dielectric, a trench polysilicon gate electrode, a planar polysilicon gate electrode, a metal via, a gate oxide layer, a second-conductivity-type semiconductor heavily doped contact region, a longitudinal channel region, a lateral channel region and a second-conductivity-type semiconductor body region. The present application designs a lateral MOSFET inside the device without additional layout area and without deeper trench depth, which is connected in series with the longitudinal channel to extend the channel length, so that the influence of the mobility on the drain current will be significantly increased, and the device can enter the current negative temperature characteristic region earlier, thereby improving the reliability of the device.

The invention relates to a PMOS (P-channel Metal Oxide Semiconductor) transistor and a manufacturing method thereof. According to the manufacturing method, a gate dielectric layer, a polycrystalline silicon gate and a side wall are formed in a first groove in a substrate, and the polycrystalline silicon gate has a structure with a wide upper part and a narrow lower part, so that the area of the upper surface of the gate can be increased while the smaller feature size of the transistor is met, the contact resistance of the polycrystalline silicon gate can be reduced, and the reliability of the transistor is improved. After a protection layer is formed on the upper surface of a polycrystalline silicon gate, sigma-shaped grooves are formed in the two sides of the polycrystalline silicon gate, a source-drain epitaxial layer is grown through an epitaxial process, and the side face and the upper surface of the polycrystalline silicon gate are covered during the epitaxial process, so that epitaxial growth of the polycrystalline silicon gate can be avoided; when the groove is formed on the polycrystalline silicon layer to fill the protective layer, the polycrystalline silicon grid electrode does not need to be etched, so that uneven thickness of the polycrystalline silicon grid electrode caused by an etching load effect can be avoided, and the performance of the PMOS transistor can be improved.

The application relates to the technical field of power electronic devices, and provides a silicon carbide MOSFET device and a manufacturing method thereof. The source region structure of the silicon carbide MOSFET device comprises: a first n-type region, which is a nitrogen ion implantation region, and the lateral boundary of which is self-aligned with the boundary of a p-type well region; a second n-type region, which is a phosphorus ion implantation region, and is located in the first n-type region; the lateral extension width of the first n-type region is greater than the lateral extension width of the second n-type region, and the lateral boundaries of the two have a fixed lateral offset; the lateral boundary of the second n-type region is inwardly recessed relative to the edge of a polysilicon gate, thereby forming a lateral buffer gap, which is used for deviating a high-concentration phosphorus implantation damage region of the second n-type region from a gate oxide layer; and a metal silicide layer is located above the second n-type region, and is used for forming a source region contact. The application realizes inward retraction of the phosphorus implantation region through a self-alignment process, and reduces the contact resistance by using the high solid solubility of phosphorus while protecting the gate oxide layer.

The application belongs to the technical field of power semiconductor, and relates to a silicon carbide MOSFET structure, which comprises a metallized drain, a high-doped first-conductivity-type semiconductor substrate, a first-conductivity-type semiconductor epitaxial layer, a second-conductivity-type semiconductor well, a high-doped second-conductivity-type semiconductor ohmic contact region, a high-doped first-conductivity-type semiconductor source contact region, a high-doped first-conductivity-type semiconductor current guide layer, a first-conductivity-type semiconductor JFET region, a metallized source, a gate oxide layer, a Schottky metal region, a polysilicon gate electrode, an oxide layer and an N+ polysilicon short circuit layer. The application adopts a split gate structure, integrates a Schottky contact in the middle of the gate, and sets a current guide layer in the JFET region. With the increase of the drain voltage, the Schottky contact makes the JFET region quickly deplete and clamp off in advance, thereby reducing the saturation current of the device. The current guide layer provides a current path, which can improve the short circuit current resistance of the device and reduce the on-resistance of the device.

The invention discloses a process integration method for improving the yield of an SRAM (Static Random Access Memory) area, which comprises the following steps of: 1, providing a semiconductor substrate on which a dummy gate structure is formed, and covering a contact hole etching barrier layer on the top surface, the side surface and the external surface of the dummy gate structure; 2, a first interlayer film is formed, a part of the gate spacer is not completely filled and forms a closed cavity, the size of the cavity is related to the thickness of the first interlayer film deposition and the thickness of the contact hole etching barrier layer, when the SRAM capacities are different, the technological conditions of the first interlayer film deposition and the contact hole etching barrier layer are kept unchanged, and when the SRAM capacities are different, the first interlayer film deposition and the contact hole etching barrier layer are not changed; and process integration of SRAMs with different capacities is realized. And step 3, carrying out first CMP (Chemical Mechanical Polishing) which is stopped at the etching barrier layer of the contact hole. And 4, forming a second interlayer film. And step 5, stopping the second CMP on the polysilicon gate. According to the invention, the process integration of SRAMs with different capacities can be realized, and the yield can be improved.

The invention provides a reverse conducting insulated gate bipolar transistor and a preparation method thereof, and belongs to the technical field of power semiconductor devices, the reverse conducting insulated gate bipolar transistor is characterized in that a first trench is a gate trench, a second trench is an emitter trench, and a third trench is an invalid gate trench; the first groove, the second groove and the third groove are sequentially arranged at intervals in the transverse direction parallel to the surface of the cell, the first groove and the second groove are connected through a fourth groove, and the fourth groove is a grid electrode groove; in the longitudinal direction, the second grooves are located between every two adjacent fourth grooves. The beneficial effects of the invention are that the gate trench is connected with the invalid gate trench through the transverse gate trench, thereby reducing the forward conduction voltage drop and conduction loss of the device; current channels are increased, so that current distribution is more uniform, heat loss is reduced, and reliability and power density of the device are improved; the polysilicon gates and the metal gates are repeatedly arranged at intervals in the transverse direction and the longitudinal direction of the emitter trench to form the diodes and the Schottky diodes which are regularly arranged, so that the current distribution of the backward diodes is more uniform.

The invention relates to an NMOS (N-channel Metal Oxide Semiconductor) transistor and a preparation method thereof, and the preparation method comprises the steps: providing a substrate, the substrate is provided with a plurality of discrete active regions extending along a first direction, P-type well regions are formed in the active regions, shallow trench isolation structures are formed among the active regions, and the top surfaces of the shallow trench isolation structures are equal to or lower than the top surfaces of the active regions; forming a gate oxide dielectric layer on the surface of the active region; a polysilicon gate electrode crossing the plurality of active regions in a second direction is formed on the oxygen dielectric layer, P-type foreign ions are doped in the polysilicon gate electrode, and the second direction is perpendicular to the first direction; and forming a source region and a drain region in the P-type well region on two sides of the polysilicon gate electrode. The migration speed of electron carriers of the NMOS transistor formed in the direction of the invention is higher, so that the speed of forming the NMOS is improved.

The application relates to the technical field of semiconductor integrated circuits, in particular to a static protection device structure. The static protection device structure comprises a first conductive type substrate, an upper layer of the first conductive type substrate forms a first conductive type well region; in the first conductive type well region, source regions and drain regions are arranged in a transverse interval, the source regions and the drain regions are both of a second conductive type; all the drain regions are connected to lead out a static input end of the static protection device structure, and each source region is connected to lead out a static output end of the static protection device structure; a first conductive type diffusion region is inserted into the drain region, and the first conductive type diffusion region is not provided with a leading-out end; and a polysilicon gate is located on an interval region between the interval adjacent source region and drain region. The static protection device structure can solve the problems of high turn-on voltage and low static protection capability of the static protection device structure in the related art.

The application provides a SiC MOSFET and a preparation method of the SiC MOSFET, which comprises, from bottom to top, a drain metallization layer, an N+ substrate layer, an N-drift region, a current spreading region, a P-well region, a second N+ source region, a second P-base region, a first P-base region, a first N+ source region, a gate oxide, a polysilicon gate, an isolation oxide, and a source metallization layer; the first N+ source region, the second N+ source region, and the P-well region are in contact with the source metallization layer; the second N+ source region surrounds the bottom, two corners, and one sidewall of a trench gate oxide; the second N+ source region is shielded by the P-well region and the second P-base region, and is isolated from the current spreading region and the N-drift region. The application effectively suppresses a strong electric field of the gate oxide caused by high-energy charged particle radiation, and greatly improves the anti-single-particle gate punch-through capability of the trench type SiC MOSFET.

The application discloses a SiC MOSFET signal input end bidirectional full-port electrostatic protection module, which comprises a SiC epitaxial region and a SiC substrate, a drain back gold, a side wall polysilicon, a side wall-free polysilicon gate, a source lead-out metal and a gate connection metal, the SiC epitaxial wafer is prepared by a standard SiC MOSFET process, and the SiC epitaxial wafer comprises a SiC substrate and a doped SiC epitaxial region above the SiC substrate, wherein the SiC epitaxial region comprises a SiC N-drift region, a SiC NSL current diffusion layer, a JFET region, a Pwell region, a Pbase region, a P++ region, an electric field advance termination N++ region, an ohmic contact injection N++ region and a gate connection injection N++ region. The application constructs a bidirectional full-port electrostatic protection device for a SiC MOSFET signal input end, and forms full-port protection for four types of electrostatic impacts, i.e., positive and negative electrostatic charges of a gate-source and positive and negative electrostatic charges of a gate-drain.

The invention provides an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method of the MOSFET device. The MOSFET device comprises a substrate, an epitaxial layer, a trench gate structure, a source electrode structure and a drain electrode structure, wherein the epitaxial layer is located on one side of the substrate; the trench gate structure is located in the epitaxial layer, the width of the trench gate structure is gradually increased in the direction from the substrate to the epitaxial layer, the trench gate structure comprises a polysilicon gate, a first gate dielectric layer, a second gate dielectric layer and a gate electrode, and the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer; the source electrode structure is located at one side, far away from the substrate, of the epitaxial layer and one side, far away from the substrate, of the trench gate structure; the drain structure is located on one side of the substrate away from the epitaxial layer. According to the MOSFET device provided by the invention, the performance of the MOSFET device can be improved.

The invention relates to the technical field of semiconductors, in particular to a trench MOSFET integrated with a temperature sensor and a testing method, the trench MOSFET mainly comprises a metal layer, a doped substrate layer and a doped epitaxial layer which are sequentially arranged from bottom to top, and a doped buried layer, a polysilicon gate layer and a first silicon dioxide layer are arranged on the left side of the upper portion of the doped epitaxial layer; a doped well region layer, a first doped source region layer, a second doped source region layer and a source metal layer are arranged in the middle of the upper part of the doped epitaxial layer, and an electrical isolation layer, a second silicon dioxide layer, a first doped polycrystalline silicon layer and a second doped polycrystalline silicon layer are arranged on the right side of the upper part of the doped epitaxial layer. According to the invention, through dielectric isolation of the electrical isolation layer and the second silicon dioxide layer, the temperature sensor is not interfered by a main device, and the precision of the sensor is guaranteed.

Various embodiments of the utility model relate to a semiconductor device. The semiconductor device comprises a first active region layer extending along a first direction; a first over-diffusion metal layer extending in a second direction different from the first direction, the first over-diffusion metal layer being over the first active region layer; a first polysilicon gate contact extending in a second direction over the first active region layer; a first polysilicon end of the first polysilicon gate contact adjoining the first dielectric region; and a first low-k dielectric material in the first dielectric region.