229results about How to "Reduce RC delay" patented technology

A method of forming an interconnect for a semiconductor device using triple hard layers, comprises: forming a first hard layer serving as an etch stop layer on a metal interconnect-formed dielectric layer; forming a second hard layer on the first hard layer; forming a dielectric layer on the second hard layer; forming a third hard layer on the dielectric layer; forming a hole through the third and second hard layers, the dielectric layer, and the first hard layer; and filling the hole with metal to establish an interconnect. The second and third hard layers are each made of carbon-doped silicon oxide formed from a source gas and a redox gas, while controlling the carbon content in the second hard layer as a function of a flow rate of the redox gas.

A four color liquid crystal display (LCD) including red, green, blue, and white sub-pixels are provided. The LCD also includes a plurality of gate lines for transmitting gate signals to the sub-pixels and a plurality of data lines for transmitting data signals to the sub-pixels. The white sub-pixel is smaller than the other sub-pixels, and each of the data lines passes between adjacent two sub-pixels and includes at least one curved portion. Furthermore, the lengths of the data lines are substantially uniform.

A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active are that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that form the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.

A touch recognition enabled display device includes a plurality of common electrode blocks serving as touch-sensing regions and/or touch-driving regions. Conductive lines connected to the common electrode blocks are placed under the common electrode blocks and the pixel electrodes of the pixels, and they are routed across the active area, directly toward an inactive area where drive-integrated circuits are located. The conductive lines are positioned under one or more planarization layers, and are connected to the corresponding common electrode blocks via one or more contact holes.

The invention relates to integrated circuit fabrication, and more particularly to a Field Effect Transistor with a low resistance metal gate electrode. An exemplary structure for a gate electrode for a Field Effect Transistor comprises a lower portion formed of a first metal material having a recess and a first resistance; and an upper portion formed of a second metal material having a protrusion and a second resistance, wherein the protrusion extends into the recess, wherein the second resistance is lower than the first resistance. The metal gate electrode provided in the invention has a low gate resistance value, so can reduce the capacitance-resistance delay of circuit and improve the performance an apparatus.

A display panel includes an array substrate including a plurality of connection lines extending from a plurality of signal lines and at least one repair line crossing the connection lines. An opposite substrate including a common electrode formed on a surface of the second substrate that is closest to the array substrate is coupled to the array substrate. The common electrode includes a plurality of openings that are positioned to align with a plurality of intersections between the connection lines and the repair line, thereby preventing an electrical coupling between the signal line and the common electrode.

A liquid crystal display (LCD) array substrate and its manufacturing method are provided. Scan lines and data lines of the LCD array substrate are composed of two conductive layers to decrease their RC delay. Moreover, the dielectric layer and even the planarization layer are removed from pixel areas defined by the scan lines and the data lines to increase the light penetration percentage.

A touch sensor integrated display device includes a plurality of common electrode blocks serving as touch-sensing regions and/or touch-driving regions. Conductive lines connected to the common electrode blocks are placed under the common electrode blocks and the pixel electrodes of the pixels, and they are routed across the active area, directly toward an inactive area where drive-integrated circuits are located. The conductive lines are positioned under one or more planarization layers, and are connected to the corresponding common electrode blocks via one or more contact holes.

Disclosed are a method for removing a photoresist layer and a method for forming a metal line using the same. The method for removing a photoresist pattern, including the steps of: forming a bottom layer on a substrate by using the photoresist pattern as a mask; and removing the photoresist pattern with use of a high density plasma (HDP) apparatus. The method for forming a metal line, including the steps of: preparing a semi-finished substrate including an inter-layer insulation layer; forming a photoresist pattern on the inter-layer insulation layer; forming an opening by etching the inter-layer insulation layer with use of the photoresist pattern as an etch mask; removing the photoresist pattern by using a high density plasma (HDP) apparatus; and forming the metal line by filling the opening with a predetermined material.

The invention provides a method of manufacturing a semiconductor element metal gate stack. The present disclosure provides a method that includes forming a high k dielectric layer on a semiconductor substrate; forming a polysilicon layer on the high k dielectric layer; patterning the high k dielectric layer and polysilicon layer to form first and second dummy gates in first and second field effect transistor (FET) regions, respectively; forming an inter-level dielectric (ILD); applying a first CMP process to the semiconductor substrate, exposing the first and second dummy gates; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a first metal electrode in the first gate trench; applying a second CMP process; forming a mask covering the first FET region and exposing the second dummy gate; thereafter removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a second metal electrode in the second gate trench; and applying a third CMP process. The invention maintains the integration of metal gate electrode and the expected working function and improves the circuit effect.

An integrated circuit structure includes a semiconductor substrate; a first bottom metallization (M1) layer over the semiconductor substrate; a second M1 layer over the first M1 layer, wherein metal lines in the first and the second M1 layer have widths of greater than about a minimum feature size; and vias connecting the first and the second M1 layers.

The invention discloses a liquid crystal display device and a display panel thereof. The display panel comprises a display region, and a fan-out region connected with at least one side of the display region, wherein the fan-out region comprises at least one group of fan-out routings; each group of fan-out routings comprise a plurality of routings; the multiple routings comprise first layers of metal routings and second layers of metal routings which are arranged alternately; the adjacent first layer and second layer of metal routings are partially superposed. Due to the mode, the liquid crystal display device has the advantages that the RC time delay among all the routings of each group of fan-out routings can be reduced, and the display quality is improved.

The invention discloses a manufacturing method for a MOSFET adopting a separated trench side gate structure with a shield gate. The manufacturing method comprises the steps of performing injection for a well region and a source region in a semiconductor substrate and performing an annealing-boosting process; forming a hard mask layer, and performing a photoetching process to define a gate formation region; performing anisotropic etching for the first time to form a trench; performing anisotropic etching for the second time to increase the width and the depth of the trench; forming a gate dielectric layer and a gate metal layer; performing back etching on the gate metal layer; performing anisotropic etching for the semiconductor substrate at the bottom of the trench; forming oxide layers on the internal surface of the deep trench and the side face of the gate metal layer at the same time; and performing source shield metal layer growth. According to the manufacturing method, the gate resistance can be lowered, the application of the device in a high-frequency circuit is expanded by reducing RC delay, technological steps in a thermal process are reduced, the product manufacturing period is shortened, gate drain capacitance can be lowered, the thickness of the gate source isolating oxide layer can be improved, and the gate source electric leakage can be reduced.