11443 results about "Semiconductor components" patented technology

In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.

A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.

A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.

A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions that are covered with a non-oxidizing metal. The method can be used to fabricate stackable semiconductor packages having integrated circuits in electrical communication with the external contacts. The method can also be used to fabricate interconnects for electrically engaging packages, dice and wafers for testing or for constructing electronic assemblies.

A method and a device can be used for checking the layout of an electronic circuit of a semiconductor component. For example, the method includes an automatic classification of cells in at least one layout into a cell database, and an automatic layout checker comparing the cell database to a layout to be checked.

An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.

A method of making a light active sheet. A bottom substrate having an electrically conductive surface is provided. A hotmelt adhesive sheet is provided. Light active semiconductor elements, such as LED die, are embedded in the hotmelt adhesive sheet. The LED die each have a top electrode and a bottom electrode. A top transparent substrate is provided having a transparent conductive layer. The hotmelt adhesive sheet with the embedded LED die is inserted between the electrically conductive surface and the transparent conductive layer to form a lamination. The lamination is run through a heated pressure roller system to melt the hotmelt adhesive sheet and electrically insulate and bind the top substrate to the bottom substrate. As the hotmelt sheet is softened, the LED die breakthrough so that the top electrode comes into electrical contact with the transparent conductive layer of the top substrate and the bottom electrode comes into electrical contact with the electrically conductive surface of the bottom substrate. Thus, the p and n sides of each LED die are automatically connected to the top conductive layer and the bottom conductive surface. Each LED die is encapsulated and secured between the substrates in the flexible, hotmelt adhesive sheet layer. The bottom substrate, the hotmelt adhesive (with the embedded LED die) and the top substrate can be provided as rolls of material. The rolls are brought together in a continuous roll fabrication process, resulting in a flexible sheet of lighting material.