2814 results about "Semiconductor components" patented technology

An electronic device including an electronic unit and a functional unit is provided. The electronic unit includes a substrate, a plurality of semiconductor components, and a cover layer. The substrate has a plurality of first side surfaces. The semiconductor components are disposed on the substrate. The cover layer is disposed on the semiconductor components and has a plurality of second side surfaces. The functional unit is disposed on at least one of at least one of the first side surfaces and at least one of the second side surfaces.

Methods, systems, and devices for pass-through power delivery for logic-on-top semiconductor systems are described. A semiconductor system may be configured with a two-dimensional pattern of power delivery conductors that pass through semiconductor components of a stack (e.g., through one or more memory stacks), providing a more-distributed delivery of power to a logic component bonded with the stack. The power delivery conductors may include through-substrate vias that bypass circuitry of the stack, and thus may be allocated for providing power to the logic component. Such techniques may be combined with a redistribution component, such as a package substrate or interposer (e.g., opposite the logic component in the heterogeneous stack), which may include redistribution conductors that convert from relatively fewer interconnections at a surface of the semiconductor system (e.g., for solder interconnection) to relatively more interconnections at a surface bonded with the stack (e.g., for hybrid bonding interconnection).

A semiconductor module includes first to fourth semiconductor elements, a plurality of wiring patterns, a first power source terminal, second power source terminals, a first intermediate point terminal and a second intermediate point terminal, and a full bridge circuit is formed in the semiconductor module. The semiconductor module further includes a temperature detection element; first and second temperature detection wiring patterns; and first and second temperature detection terminals. The temperature detection element is disposed in a region surrounded by a first switching path and a second switching path. The semiconductor module is configured to reduce noises caused by a parasitic capacitance between a second wiring pattern and a first temperature detection wiring pattern, and a parasitic capacitance between a fourth wiring pattern and a first temperature detection wiring pattern.

To provide a semiconductor module capable of more accurately performing a temperature detection.SOLUTION: A semiconductor module 1 includes: first to fourth semiconductor elements Q1 to Q4; a plurality of wiring patterns; a first power supply terminal 51; second power supply terminals 52 and 53; a first midpoint terminal 61; and a second midpoint terminal 62, in which a full bridge circuit is configured. The semiconductor module 1 further includes: a temperature detection element 90; first and second temperature detection wiring patterns 93 and 94; and first and second temperature detection terminals T1 and T2. The temperature detection element 90 is disposed in a region surrounded by a first switching path A and a second switching path B, and is configured to reduce noise based on a parasitic capacitance between a second wiring pattern 20 and the first temperature detection wiring pattern 93 and the parasitic capacitance between a fourth wiring pattern 40 and the first temperature detection wiring pattern 93.SELECTED DRAWING: Figure 4

In a semiconductor element including a silicon carbide heterostructure, the resistance component generated due to spontaneous polarization at the hetero-matched interface is suppressed, thereby reducing the specific on-resistance of the semiconductor element. A hetero-matched interface (S X ) and 1 × 10 19 cm -3 The tunnel doped region (D T By providing the layer, a carrier transport mechanism by tunneling is realized, and the specific on-resistance of the semiconductor element is kept low.

A semiconductor device includes: a semiconductor element; a support member; a bonding layer interposed between the semiconductor element and the support member; and a sealing resin that covers the semiconductor element and at least a portion of the support member, wherein the bonding layer is a layer in which a layer containing first metal and a layer containing second metal are integrated without going through a molten state, and wherein the support member includes a first surface facing in a thickness direction and facing a side on which the semiconductor element is located, and a plurality of first recesses located outside the bonding layer and recessed from the first surface when viewed along the thickness direction.

A polishing liquid containing: abrasive grains; an additive; and water, in which the additive includes (A1) a polyglycerol having a weight average molecular weight of 350 to 2800 and (B) a compound having two or more nitrogen atoms to which a hydroxyalkyl group is bonded. A polishing liquid containing: abrasive grains; an additive; and water, in which the additive includes (A2) a polyglycerol having a hydroxyl value of 800 to 1000 mgKOH / g and (B) a compound having two or more nitrogen atoms to which a hydroxyalkyl group is bonded.

A semiconductor device (100, 100A, 100B, 100C, 100D, 100E) comprises: an insulating substrate (10); at least one semiconductor element (20); a printed circuit board (30); and a connecting material (41). The insulating substrate has a first surface and a first electrode (12) disposed on the first surface. Each of the at least one semiconductor element is disposed on the first electrode, and has a second surface as well as a second electrode (21) and a third electrode (22) that are disposed on the second surface. The third electrode has a potential differing from that of the second electrode. The printed circuit board has: a circuit that drives the at least one semiconductor element; an input pattern (36a) and an output pattern (36c) that are disposed inside the printed circuit board; an input terminal (37a) and an output terminal (37c) that protrude from the printed circuit board; a third surface that faces the first surface and the second surface; and a plurality of third electrodes (31) that are disposed on the third surface.

Provided is an electric circuit body including: a power semiconductor element; a first conductor plate configured to be connected to one surface of the power semiconductor element; a first sheet-shaped member having a first resin insulation layer and configured to at least cover a surface of the first conductor plate; a sealing material configured to seal each of the power semiconductor element, the first conductor plate, and an end of the first sheet-shaped member; and a first cooling member configured to be adhesively attached to the first sheet-shaped member. In the electric circuit body, the first sheet-shaped member includes: an embedded portion where the end of the first sheet-shaped member is covered with the sealing material; a heat dissipation surface as a region to overlap the surface of the first conductor plate; and a margin as a region between the embedded portion and the heat dissipation surface, the margin is located more inward than the heat dissipation surface, and the embedded portion is located more inward than the margin.

A bonded structure is disclosed. The bonded structure can comprise a first semiconductor element having a first contact pad. An interposer can include a second contact pad on a first side of the interposer and a third contact pad and a fourth contact pad on a second side of the interposer opposite the first side, the second contact pad bonded to the first contact pad; a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad. A switching circuitry can be configured to switch between a first electrical connection between the second and third contact pads and a second electrical connection between the second and fourth contact pads.

A circuit assembly includes first and second circuit carriers and a semiconductor component arranged between the circuit carriers and having first and second load terminals. The first load terminal has a first load terminal surface which faces the first circuit carrier and around which an electrically insulating edging structure is arranged. The second load terminal has a second load terminal surface which faces the second circuit carrier and is larger than the first load terminal surface. The first circuit carrier has a first through-contact which electrically connects the first load terminal surface to a first conductor path, which runs inside the first circuit carrier or on a top side of the first circuit carrier facing away from the semiconductor component. The second circuit carrier has a top side facing the semiconductor component and formed by a first electrically conductive layer that is electrically connected to the second load terminal surface.

In a semiconductor device, a first wiring member is electrically connected to a first main electrode on a first surface of a semiconductor element, and a second wiring member is electrically connected to a second main electrode on a second surface of the semiconductor element. An encapsulating body encapsulates at least a part of each of the first and second wiring members, the semiconductor element and a bonding wire. The semiconductor element has a protective film on the first surface of the semiconductor substrate, and the pad has an exposed surface exposed from an opening of the protective film. The exposed surface includes a connection area to which the bonding wire is connected, and a peripheral area on a periphery of the connection area. The peripheral area has a surface that defines an angle of 90 degrees or less relative to a surface of the connection area.

An optoelectronic semiconductor device (1) is specified, comprising: - a stack of layers (10) comprising a first main surface (10A) and a second main surface (10C) opposite the first main surface (10A), as well as at least one side surface (10B) that laterally bounds the stack of layers (10) and connects the first and second main surfaces (10A, 10C), - a metallic reflective layer (3) extending from the second main surface (10C) to at least one side surface (10B) and having an end region (3A) facing away from the second main surface (10C), and - an encapsulation (5) extending from the second main surface (10C) across the side surface (10B) to the first main surface (10A) and comprising a first insulating layer (2) and a second insulating layer (4), wherein the metallic reflective layer (3) is arranged on the at least one side surface (10B) between the first and second insulating layers (2, 4) and the end region (3A) is covered by the encapsulation (5). Furthermore, a method for manufacturing an optoelectronic semiconductor device is described.

A semiconductor device includes a semiconductor element, a sealing member, and a rewiring layer. The rewiring layer includes an insulating layer covering a front surface of the semiconductor element and a part of the sealing member, an electrode connected to the semiconductor element, and an externally-exposed layer being conductive and covering a portion of the electrode exposed from the insulating layer.

A semiconductor device includes a cell portion and a peripheral portion. The cell portion has a semiconductor element including a drift layer, a first impurity region, a second impurity region, trench-gate structures, a high-concentration layer, an interlayer insulating film, a first electrode and a second electrode. The interlayer insulating film is located on the trench-gate structures, the first impurity region and the second impurity region, and has a first contact hole communicating with the first impurity region and the second impurity region. The peripheral portion has a section facing the cell portion in one direction, and the interlayer insulating film further has a second contact hole at the section of the peripheral portion. The second contact hole exposes the first impurity region, and the first electrode is electrically connected to the first impurity region through the second contact hole in the peripheral portion.

The invention relates to a switch-off unit (1, 1.1, 1.2, 1.3, 1.4, 1.5) for an electric charging device (3, 25, 27) with a switch-off arrangement (5, 5.1, 5.2, 5.3, 5.4, 5.5) having a first controllable power semiconductor component (9, 9.1) and a second controllable power semiconductor component (9, 9.2), and a switch-off control device (7), whereinthe first power semiconductor component (9, 9.1) and the second power semiconductor component (9, 9.2) are arranged antiserially, whereinthe first power semiconductor component (9, 9.1) and the second power semiconductor component (9, 9.2) are configured to conduct a charging current of the charging device (3, 25, 27) in a switched-on state, whereinthe switch-off control device (7) is operatively connected to the first power semiconductor component (9, 9.1) and the second power semiconductor component (9, 9.2) and is configured for their respective control, whereinthe switch-off control device (7) is configured to acquire a value of at least one charging parameter which is characteristic of the charging current, andin dependence on the acquired value, to switch off the first power semiconductor component (9, 9.1) and / or the second power semiconductor component (9, 9.2) and thereby interrupt the charging current.

The invention relates to an electronic assembly (1), having - a main printed circuit board (2) and - a semiconductor component (28) arranged on the main printed circuit board (2), characterized by - a measuring printed circuit board (26) arranged in thermally conducting contact with the semiconductor component (28), and - a temperature sensor (16) arranged on the measuring printed circuit board (26) and configured to measure a temperature, on the basis of which a junction temperature (θ_J) of the semiconductor component (28) can be determined.

An optoelectronic semiconductor device (1) comprising a micro-LED (100) and a conversion element (200) is described. The micro-LED (100) is configured to emit a first electromagnetic radiation in the blue wavelength range. The conversion element (200) is configured to convert the first electromagnetic radiation into a second electromagnetic radiation. The conversion element (200) is in direct contact with the micro-LED (100). Furthermore, a method for fabricating an optoelectronic semiconductor device (1) is described.

Thermal management components are included over semiconductor components on both sides of a package substrate of a semiconductor device package to provide two-sided thermal management system for the semiconductor device package. The two-sided thermal management system of the semiconductor device package enables heat to be dissipated from the semiconductor components on both sides of the package substrate of the semiconductor device package. This enables the semiconductor components on both sides of the package substrate of the semiconductor device package to operate at lower temperatures, which may increase the performance of the semiconductor components, may enable the performance of the semiconductor components to be sustained for longer time durations, and / or may increase the reliability and longevity of the semiconductor components, among other examples.

Method for manufacturing a housing for mounting a semiconductor element by using a forming tool with an upper tool and a lower tool, wherein the housing for mounting a semiconductor element comprises a substrate having a mounting surface for mounting a semiconductor element, and an encapsulation body formed from a cured product of a curable resin and having a frame-shaped section surrounding the mounting surface, and wherein the housing has a concave section formed by the mounting surface and the encapsulation body, and the method for manufacturing a housing for mounting a semiconductor element comprises: a step of arranging a mold release film, having a substantially constant thickness across the film, on the upper tool, which has a convex section whose shape corresponds to the concave section, arranging the substrate on the lower tool, and closing the upper and lower tools so that the convex section is in close contact with the mounting section of the substrate by means of the mold release film, a step of filling a space formed between the upper tool and the lower tool with a curable resin, whereupon the curable resin is cured, and a step of separating a cured product of the curable resin together with the substrate from the mold tool, wherein the mold release film comprises a first layer, which is intended to be in contact with the curable resin at the time of curing of the curable resin, and a second layer, the first layer has a thickness of 3 to 25 µm and furthermore has a tensile energy storage modulus at 180 °C of 10 to 40 MPa and the second layer has a product of the tensile energy storage modulus (MPa) at 180 °C and a thickness (µm) of 2000 to 13000.

In a semiconductor device, a first wiring member is electrically connected to a first main electrode on a first surface of a semiconductor element, and a second wiring member is electrically connected to a second main electrode on a second surface of the semiconductor element. An encapsulating body encapsulates at least a part of each of the first and second wiring members, the semiconductor element and a bonding wire. The semiconductor element has a protective film on the first surface of the semiconductor substrate, and the pad has an exposed surface exposed from an opening of the protective film. The exposed surface includes a connection area to which the bonding wire is connected, and a peripheral area on a periphery of the connection area. The peripheral area has a surface that defines an angle of 90 degrees or less relative to a surface of the connection area.

A semiconductor device includes: a supporting conductor including a first obverse surface facing a first side in a thickness direction; a plurality of semiconductor elements including four or more semiconductor elements disposed on the first obverse surface; and a sealing resin covering the plurality of semiconductor elements and the supporting conductor. The plurality of semiconductor elements are disposed side by side in a first direction perpendicular to the thickness direction, and include a first semiconductor element and a second semiconductor element that are located near a center in the first direction. A first distance, which is a distance between a center of the first semiconductor element and a center of the second semiconductor element, is greater than a second distance, which is a distance between the center of one of the first semiconductor element and the second semiconductor element and a center of one of a third semiconductor element and a fourth semiconductor element that is adjacent to the one of the first semiconductor element and the second semiconductor element in the first direction.

The invention relates to a method for manufacturing a semiconductor device. The method comprises providing a substrate with an alignment structure and arranging at least one first semiconductor chip on the substrate laterally to the alignment structure using a flowable adhesive. Due to wetting of the substrate with the adhesive, the adhesive flows in the direction of the alignment structure, so that the first semiconductor chip is moved in the direction of the alignment structure and aligned with it. The invention further relates to a semiconductor device.

An electric circuit body includes a semiconductor device incorporating a semiconductor element by sealing with a sealing material and having a heat dissipating surface for dissipating heat of the semiconductor element, the heat dissipating surface being formed on at least one surface, a cooling member disposed facing the heat dissipating surface of the semiconductor device and configured to cool the semiconductor element, and a heat conduction member disposed between the semiconductor device and the cooling member, wherein a terminal connected to the semiconductor element protrudes out from at least one side surface of the semiconductor device, and a first interval between the sealing material and the cooling member on the one side surface of the semiconductor device from which the terminal is protruded is narrower than a second interval between the sealing material and the cooling member on the other side surface of the semiconductor device from which the terminal is not protruded.

A semiconductor device (1) is specified, comprising: - a semiconductor chip (2), - at least one functional layer (3) which has a physical function and is arranged on a surface (2A, 2B) of the semiconductor chip (2), - a distribution of functional particles (4) which have a material corresponding to the functional layer (3) and / or a physical function corresponding to the functional layer (3), wherein the distribution of the functional particles (4) is located at least partially in an area of ​​the semiconductor device (1) that does not laterally overlap with the functional layer (3). Furthermore, a method for manufacturing a semiconductor device (1) is specified.

To reduce transmission loss of an electric signal between components while reducing the number of connection components of a solid-state imaging element and a semiconductor element to a connection substrate, and to reduce a mounting area.SOLUTION: The semiconductor package 1 includes the solid-state imaging device 10 having the chip substrate 11 and the semiconductor device 60, the circuit substrate 20 is disposed in the outer peripheral portion of the first surface 11a which is the surface of the chip substrate 11 on the light incident side, the circuit substrate 20 has the first surface 20a which is the surface on the light incident side and the second surface 20a opposite to the first surface 20b of the circuit substrate 20, and the semiconductor device 60 is disposed on the second surface 20b of the circuit substrate 20.SELECTED DRAWING: Figure 1

A polishing liquid for polishing undoped silicate glass, the polishing liquid having a pH of 3.0 or more. A polishing method including a step of polishing a surface to be polished of a member to be polished containing undoped silicate glass by using the above-described polishing liquid. A method for manufacturing a component, including obtaining a component by using a polished member polished by the above-described polishing method.

A semiconductor device includes: an active region having a semiconductor element and a surface electrode provided by a wiring electrode material and connected to the semiconductor element on a side adjacent to a surface of a semiconductor chip; and a pad arrangement region having a pad provided by the wiring electrode material. The pad arrangement region overlaps the active region in a direction normal to the surface of the semiconductor chip. In a part where the pad arrangement region and the active region overlap, the pad is disposed on the surface electrode through an isolation insulating film so that the wiring electrode material is in two layers to provide a double-layer wiring electrode structure. In a part of the active region without overlapping the pad arrangement region, the surface electrode has a single-layer wiring electrode structure composed of a single layer of the wiring electrode material.

A semiconductor device includes a plurality of semiconductor elements, each of the plurality of semiconductor elements including an active region disposed on a substrate, and a gate structure intersecting the active region and extending in a first direction that is parallel to an upper surface of the substrate; and at least one dummy element disposed between a pair of semiconductor elements adjacent to each other in a second direction, intersecting the first direction, among the plurality of semiconductor elements. The dummy element includes a dummy active region and at least one dummy gate structure intersecting the dummy active region and extending in the first direction. A length of the dummy active region in the second direction is less than a length of the active region included in each of the pair of semiconductor elements.

A semiconductor device includes a semiconductor element, a sealing material, and an extension wire. The semiconductor element has, on a front surface, a first electrode pad and at least one second electrode pad, and generates a current in a direction connecting the front surface and a back surface. The sealing material is made of an insulating resin material and covers a part of the front surface and a side surface of the semiconductor element. The extension wire is disposed above the semiconductor element and inside the sealing material or on the sealing material. The extension wire is electrically connected to the second electrode pad, and extends from a position inside of a contour of the semiconductor element to a position outside of the contour of the semiconductor element.