1549 results about "Semiconductor components" patented technology

In a semiconductor element including a silicon carbide heterostructure, the resistance component generated due to spontaneous polarization at the hetero-matched interface is suppressed, thereby reducing the specific on-resistance of the semiconductor element. A hetero-matched interface (S X ) and 1 × 10 19 cm -3 The tunnel doped region (D T By providing the layer, a carrier transport mechanism by tunneling is realized, and the specific on-resistance of the semiconductor element is kept low.

A bonded structure is disclosed. The bonded structure can comprise a first semiconductor element having a first contact pad. An interposer can include a second contact pad on a first side of the interposer and a third contact pad and a fourth contact pad on a second side of the interposer opposite the first side, the second contact pad bonded to the first contact pad; a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad. A switching circuitry can be configured to switch between a first electrical connection between the second and third contact pads and a second electrical connection between the second and fourth contact pads.

In a semiconductor device, a first wiring member is electrically connected to a first main electrode on a first surface of a semiconductor element, and a second wiring member is electrically connected to a second main electrode on a second surface of the semiconductor element. An encapsulating body encapsulates at least a part of each of the first and second wiring members, the semiconductor element and a bonding wire. The semiconductor element has a protective film on the first surface of the semiconductor substrate, and the pad has an exposed surface exposed from an opening of the protective film. The exposed surface includes a connection area to which the bonding wire is connected, and a peripheral area on a periphery of the connection area. The peripheral area has a surface that defines an angle of 90 degrees or less relative to a surface of the connection area.

An optoelectronic semiconductor device (1) is specified, comprising: - a stack of layers (10) comprising a first main surface (10A) and a second main surface (10C) opposite the first main surface (10A), as well as at least one side surface (10B) that laterally bounds the stack of layers (10) and connects the first and second main surfaces (10A, 10C), - a metallic reflective layer (3) extending from the second main surface (10C) to at least one side surface (10B) and having an end region (3A) facing away from the second main surface (10C), and - an encapsulation (5) extending from the second main surface (10C) across the side surface (10B) to the first main surface (10A) and comprising a first insulating layer (2) and a second insulating layer (4), wherein the metallic reflective layer (3) is arranged on the at least one side surface (10B) between the first and second insulating layers (2, 4) and the end region (3A) is covered by the encapsulation (5). Furthermore, a method for manufacturing an optoelectronic semiconductor device is described.

The invention relates to an electronic assembly (1), having - a main printed circuit board (2) and - a semiconductor component (28) arranged on the main printed circuit board (2), characterized by - a measuring printed circuit board (26) arranged in thermally conducting contact with the semiconductor component (28), and - a temperature sensor (16) arranged on the measuring printed circuit board (26) and configured to measure a temperature, on the basis of which a junction temperature (θ_J) of the semiconductor component (28) can be determined.

Method for manufacturing a housing for mounting a semiconductor element by using a forming tool with an upper tool and a lower tool, wherein the housing for mounting a semiconductor element comprises a substrate having a mounting surface for mounting a semiconductor element, and an encapsulation body formed from a cured product of a curable resin and having a frame-shaped section surrounding the mounting surface, and wherein the housing has a concave section formed by the mounting surface and the encapsulation body, and the method for manufacturing a housing for mounting a semiconductor element comprises: a step of arranging a mold release film, having a substantially constant thickness across the film, on the upper tool, which has a convex section whose shape corresponds to the concave section, arranging the substrate on the lower tool, and closing the upper and lower tools so that the convex section is in close contact with the mounting section of the substrate by means of the mold release film, a step of filling a space formed between the upper tool and the lower tool with a curable resin, whereupon the curable resin is cured, and a step of separating a cured product of the curable resin together with the substrate from the mold tool, wherein the mold release film comprises a first layer, which is intended to be in contact with the curable resin at the time of curing of the curable resin, and a second layer, the first layer has a thickness of 3 to 25 µm and furthermore has a tensile energy storage modulus at 180 °C of 10 to 40 MPa and the second layer has a product of the tensile energy storage modulus (MPa) at 180 °C and a thickness (µm) of 2000 to 13000.

In a semiconductor device, a first wiring member is electrically connected to a first main electrode on a first surface of a semiconductor element, and a second wiring member is electrically connected to a second main electrode on a second surface of the semiconductor element. An encapsulating body encapsulates at least a part of each of the first and second wiring members, the semiconductor element and a bonding wire. The semiconductor element has a protective film on the first surface of the semiconductor substrate, and the pad has an exposed surface exposed from an opening of the protective film. The exposed surface includes a connection area to which the bonding wire is connected, and a peripheral area on a periphery of the connection area. The peripheral area has a surface that defines an angle of 90 degrees or less relative to a surface of the connection area.

A semiconductor device (1) is specified, comprising: - a semiconductor chip (2), - at least one functional layer (3) which has a physical function and is arranged on a surface (2A, 2B) of the semiconductor chip (2), - a distribution of functional particles (4) which have a material corresponding to the functional layer (3) and / or a physical function corresponding to the functional layer (3), wherein the distribution of the functional particles (4) is located at least partially in an area of ​​the semiconductor device (1) that does not laterally overlap with the functional layer (3). Furthermore, a method for manufacturing a semiconductor device (1) is specified.

A polishing liquid for polishing undoped silicate glass, the polishing liquid having a pH of 3.0 or more. A polishing method including a step of polishing a surface to be polished of a member to be polished containing undoped silicate glass by using the above-described polishing liquid. A method for manufacturing a component, including obtaining a component by using a polished member polished by the above-described polishing method.

A semiconductor device includes: an active region having a semiconductor element and a surface electrode provided by a wiring electrode material and connected to the semiconductor element on a side adjacent to a surface of a semiconductor chip; and a pad arrangement region having a pad provided by the wiring electrode material. The pad arrangement region overlaps the active region in a direction normal to the surface of the semiconductor chip. In a part where the pad arrangement region and the active region overlap, the pad is disposed on the surface electrode through an isolation insulating film so that the wiring electrode material is in two layers to provide a double-layer wiring electrode structure. In a part of the active region without overlapping the pad arrangement region, the surface electrode has a single-layer wiring electrode structure composed of a single layer of the wiring electrode material.

Bonding strength of a connection portion bonded to a semiconductor element is measured. The semiconductor element includes a semiconductor substrate and a bond pad. In the semiconductor substrate, an element is formed, and a wiring region having a wiring for transmitting a signal of the element is disposed adjacent. The bond pad is disposed in the wiring region adjacent to a semiconductor substrate removal region, which is a region where the semiconductor substrate is removed, connected to the wiring, and bonded with a connection portion for connection to an outside. The semiconductor substrate removal region includes a region for measuring bonding strength of the bond pad and the connection portion.

The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can suppress deformation of wires connecting semiconductor elements while maintaining the insulating distance between semiconductor elements in a semiconductor device sealed with a sealing material. [Solution] The device comprises a first semiconductor element 4, a second semiconductor element 5, a wire 6b connecting the first semiconductor element 4 and the second semiconductor element 5, a first frame portion 9 on which the first semiconductor element 4 is provided, a second frame portion 10 positioned above and separated from the first frame portion 9 in the left-right direction, on which the second semiconductor element 5 is provided, and a sealing member 2. The upper surface 10a of the second frame portion 10 is provided with a recess 14 that is recessed downward, the recess is located above the first frame portion 9, and the second semiconductor element 5 is fixed in the recess 14.

A microelectronic interconnect structure having a pre-formed hybrid bonding layer is disclosed. The hybrid bonding layer is formed over a temporary carrier comprising a substantially flat upper surface. A routing structure comprising a device or metallization layers is then provided over the hybrid bonding layer. After the hybrid bonding layer coupled with the routing structure is properly reinforced, the temporary carrier is removed to reveal a bonding surface of the hybrid bonding layer. The interconnect structure can comprise an organic dielectric material interspersing the hybrid bonding layer and forming part of the routing structure, and as such exhibit bending flexibility.

To provide a semiconductor storage device for storing data by accumulating majority carriers in an electrically floating body of a MOSFET.SOLUTION: In a memory device using a semiconductor device, plate lines PLL0, PLR0 capacitively coupled to floating bodies of memory cells MCL, MCR are wired in parallel with word lines WLL0, WLR0 separately for each word line, and an erase operation of majority carriers is executed simultaneously along the word lines by applying a voltage to the plate lines. In the refresh operation, after the data along the selected word line is read and latched by the sense amplifier S / A, the bit lines BLL and BLR are separated from the sense amplifier to once erase the majority carriers all together from the floating bodies of the cells on the selected word line, and the majority carriers are injected into the cells in which a large number of majority carriers are originally stored depending on the state of the sense amplifier. In addition, the write operation includes an operation of simultaneously extracting majority carriers from the selected cell and simultaneously writing data to the sense amplifier from the outside.SELECTED DRAWING: Figure 4

Current directional device (100), containing: a power semiconductor module (300U, 300V, 300W) containing a power semiconductor element designed to convert direct current into alternating current; a first flow path forming body (110) which forms a first flow path (112a) to allow a cooling refrigerant to flow through it; a second flow path forming body (401) which forms a housing space (402) to allow a cooling refrigerant to flow through it; a first base plate (400) for attaching the second flow path forming body (401) to it; a driver circuit board (200) on which a driver circuit is mounted to output a control signal for controlling the power semiconductor element; and a housing (101) for accommodating the power semiconductor module (300U, 300V, 300W), the first flow path forming body (110), the second flow path forming body (401), the first base plate (400) and the driver circuit board (200), wherein the driver circuit board (200) is arranged such that the mounting surface of the driver circuit is opposite a side wall (401A) of the second flow path forming body (401), wherein the second flow path forming body (401) forms the accommodation space (402) for the accommodation of the power semiconductor module (300U, 300V, 300W), wherein the second flow path forming body (401) also forms an insertion opening (403) leading to the accommodation space (402) in the side wall (401A) opposite the mounting surface of the driver circuit, wherein the power semiconductor module (300U, 300V, 300W) has a control terminal (325) which passes through the insertion opening (403) and is connected to the driver circuit board (200), wherein the first flow path forming body (110) is attached to the housing (101), wherein the first flow path forming body (110) also forms an opening section leading to the first flow path (112a), wherein the first base plate (400) is designed to close the opening section and is connected to the first flow path forming body (110), and wherein the first base plate (400) also forms a first through-hole (406) connecting the first flow path (112a) and the accommodation space (402).

A semiconductor device with a configuration that contributes to a reduction in size is provided. The semiconductor device comprises an insulated circuit substrate (1) provided with conductive layers (5a, 5c) on the cover surface (S1) side, semiconductor chips (2a, 2b, 2e, 2f) provided on the conductive layers (5a, 5c), a wiring substrate (3) provided on the semiconductor chips (2a, 2b, 2e, 2f), and an output terminal (19) having an end (31) side and a negative electrode terminal (18) having an end (27) side, each end side being located between the conductive layers (5a, 5c) and the wiring substrate (3).The semiconductor device further comprises intersubstrate connectors (24a, 24h) which have upper end faces pressed into first through-holes (16a, 16h) provided in the wiring substrate (3) and lower end faces pressed into second through-holes (22a, 22h) provided in the top faces of the output terminal (19) and the negative electrode terminal (18).

The purpose of the present invention is to provide a technique capable of suppressing cracking of an insulating substrate even when warpage of a product occurs after transfer molding. The semiconductor device includes: an insulating substrate having an insulating layer, a front surface pattern, and a back surface pattern; a semiconductor element mounted on the surface pattern; and a molding resin that seals the insulating substrate and the semiconductor element in a state in which a surface of the rear surface pattern on the opposite side from a surface facing the insulating layer is exposed. The rear surface pattern is bonded to the heat sink by solder, the surface of the rear surface pattern bonded to the heat sink and the surface of the molded resin facing the heat sink are at the same height position, and the front surface pattern is provided with first slits for dividing the front surface pattern into a plurality of regions. The back pattern is provided with a second slit for dividing the back pattern into a plurality of regions, and when viewed from the thickness direction of the insulating substrate, the first slit and the second slit do not overlap or only partially overlap.

A semiconductor device comprises multiple nanostructures, a first epitaxial structure, a second epitaxial structure, a gate structure, multiple spacers, and multiple silicon-based cover layers. The multiple nanostructures can be stacked on top of each other and spaced apart. The first epitaxial structure and a second epitaxial structure can each be coupled to the ends of each of the multiple nanostructures. The gate structure wraps around each of the multiple nanostructures. Each of the multiple spacers can be positioned between a corresponding region of the gate structure and the first or second epitaxial structure. Each of the silicon-based cover layers can be positioned above or below a corresponding of the multiple spacers.

A power semiconductor device includes at least one power semiconductor element having an emitter terminal through which an emitter current flows and a sense terminal through which a sense current proportional to the emitter current flows, and a first current mirror circuit. The sense terminal is connected to an output terminal of the first current mirror circuit, and an input terminal of the first current mirror circuit is connected to a first current source.

The subject of the invention is a method for producing a polycrystalline semiconductor material, comprising introducing a reaction gas containing hydrogen and at least one semiconductor component into a reaction chamber of a vapor deposition reactor, the reaction chamber being delimited by a reactor housing and a bottom plate, wherein the reaction gas is introduced through at least one nozzle located in the bottom plate, and wherein the reaction chamber contains at least two filament rods attached to the bottom plate, on which the semiconductor material is deposited, wherein the at least two filament rods differ in length.

A semiconductor device includes a semiconductor component and a silicon-based passive component. The silicon-based passive component is stacked on the semiconductor component in a thickness direction of the semiconductor component.

In the present invention, a first switching element, a second switching element, a first rectifying element, and a second rectifying element are each composed of an even number of surface-mounted power semiconductor elements. In a planar direction orthogonal to the lamination direction in a multilayer circuit board, the first switching element and the second switching element are mounted at positions symmetrical to the first rectifying element and the second rectifying element with respect to the configuration position of a dual resonance transformer. The first switching element, the second switching element, the first rectifying element, and the second rectifying element are arranged respectively at upper, lower, left, and right positions on a plane with respect to the configuration position of the dual resonance transformer. The first switching element, the second switching element, the first rectifying element, and the second rectifying element, which are each composed of the even number of power semiconductor elements, are: mounted on the top surface and the bottom surface of the multilayer circuit board; overlapped when viewed in the lamination direction; connected in parallel through via conductors for power semiconductor connection; and thermally coupled in the lamination direction. The ON periods of the first rectifying element and the second rectifying element are set to the ON periods of the first switching element and the second switching element, respectively. The first switching element, the second switching element, the first rectifying element, and the second rectifying element change the occurrence of power loss over time vertically and horizontally with respect to the configuration position of the dual resonance transformer in the planar direction, thereby evenly dispersing the heat generation and uniformizing and integrating the heat distribution.

Procedure (100; 300), comprising: Providing (110) a machined substrate arrangement (10; 70) comprising a machined semiconductor substrate (12) and a metallization layer structure (14) on a major surface (16) of the machined semiconductor substrate (12), and Release etching (120) from an area of ​​the metallization layer structure (14) towards the processed semiconductor substrate (12) to create a cut (22) in the metallization layer structure (14) at a separation region (25) in the processed semiconductor substrate (12), wherein the separation region (25) defines a boundary between a die region (27; 34a-b) of the processed substrate arrangement (10; 70) and at least a second region of the processed substrate arrangement (10; 70); where the release etching (120) further includes: Exposure of a MEMS functional element (18) arranged on the machined semiconductor substrate (12), wherein the MEMS functional element is a MEMS sensor and / or comprises a silicon material.

Provided is a novel curable organopolysiloxane composition and the like that can be used in the production of semiconductor components and the like. A curable organopolysiloxane composition comprising: (A1) an organopolysiloxane having no curable functional group having an aliphatic unsaturated bond within the molecule, and containing at least 20 mol% or more of siloxane units represented by SiO 4 / 2 (A1-1) in the total siloxane units; (A2) an organopolysiloxane having at least one monovalent hydrocarbon group having an aliphatic unsaturated bond in one molecule; (B) an organohydrogenpolysiloxane containing at least two silicon-bonded hydrogen atoms in one molecule; (C) a first hydrosilylation catalyst that exhibits activity by irradiation of high-energy rays; and (D) a second hydrosilylation catalyst microencapsulated by a thermoplastic resin having a softening point in the temperature range of 50 to 200°C.

New substantially single-phase polycrystalline materials are disclosed. The new substantially single-phase polycrystalline materials generally include from 0.01-20 mol. % zirconia, at least 80 mol. % of one or more rare earth oxides (REO), and 40 to 7000 ppm aluminum by weight, wherein the substantially single-phase polycrystalline material comprises at least 95 wt. % of a solid-solution of REO-zirconia as measured by x-ray diffraction. The new substantially single-phase polycrystalline materials may realize a high density, such as a density of at least 95% of theoretical density, or higher. The new substantially single-phase polycrystalline materials may be in the form of a semiconductor component, including those suited for use in a plasma chamber environment.

The utility model discloses an electronic device and a fixing structure for chip packaging. The electronic device comprises a printed circuit board, a semiconductor element, a packaging connecting material and at least one fixing piece, the semiconductor element is arranged on the printed circuit board. The package connection material attaches the semiconductor element to the printed circuit board. The fixing piece is provided with a first end, a second end opposite to the first end and a middle section connected between the first end and the second end, and the fixing piece spans an upper surface of the semiconductor element from a first side of the semiconductor element to a second side of the semiconductor element; the first end and the second end are respectively fixed on the printed circuit board, and the middle section limits the movement of the semiconductor element relative to the direction of the printed circuit board.

The purpose of the present invention is to provide a technology capable of welding a terminal thicker than a circuit portion of an insulating substrate to the circuit portion without impairing insulation performance of the insulating substrate in a semiconductor device. This semiconductor device comprises: an insulating substrate having an insulating layer and a circuit portion provided on the insulating layer; a terminal having a laser irradiation surface, joined to the circuit portion by laser welding, and having a thickness greater than a thickness of the circuit portion; a semiconductor element joined to the circuit portion via a joining material and electrically connected to the terminal; a metal film formed on a surface of the terminal opposite to the laser irradiation surface and having a melting point higher than a melting point of the terminal; and a gap formed between the terminal and the circuit portion in a non-laser-welded portion.

The present invention provides a method for manufacturing a semiconductor device in which the occurrence of flow marks on the surface of a encapsulating material containing an LDS additive is suppressed. [Solution] The present invention provides a method for manufacturing a semiconductor device, comprising the steps of: mounting a lead frame 14 on a protective film 12; mounting a semiconductor element 16 on the lead frame 14; sealing the lead frame 14 and the semiconductor element 16 with a first sealing material 18 containing an LDS (LASER DIRECT STRUCTURING) additive; peeling the protective film 12 from the lead frame 14; forming through holes 20 in the thickness direction of the first sealing material 18, through holes 20 in which the surface of the semiconductor element 16 is exposed to the bottom surface, through holes 20 in which the surface of the lead frame 14 is exposed to the bottom surface, and grooves 22 on the surface of the first sealing material 18 that connect these through holes 20 in a horizontal direction, and activating the inner wall surface of the through holes 20 and the surface of the grooves 22; selectively depositing metal in the through holes 20 and grooves 22 to form metal-plated wiring 24, and electrically connecting the semiconductor element 16 and the lead frame 14; and sealing the first sealing material 16 with the metal-plated wiring 24 with a second sealing material 26.

The present application provides a semiconductor module that improves temperature detection accuracy of a semiconductor element without affecting the original performance of the semiconductor element. The semiconductor module (1) includes: a laminated substrate (2) formed by disposing a circuit board (22) on an upper surface of an insulating board (20) and a heat sink (21) on a lower surface of the insulating board; a semiconductor element (3) disposed on an upper surface of the circuit board; a metal wiring board (4) disposed on an upper surface of the semiconductor element; and a temperature sensor (6) disposed on an upper surface of the metal wiring board for detecting a temperature of the semiconductor element. The metal wiring board has a cutout portion (40) that shields heat of the semiconductor element.