4031 results about "Semiconductor components" patented technology

A method for surface defect inspection can comprise obtaining topographical data from one or more portions of a semiconductor element. The semiconductor element can have a surface comprising a dielectric and a plurality of metal pads. The method can further comprise processing the topographical data of the one or more portions of the semiconductor element to determine at least a first property of the plurality of metal pads, computing at least one variability value for the first property, and identifying candidate defects in the one or more portions of the semiconductor element based at least in part on the at least one variability value.

A semiconductor device includes semiconductor elements and conductors. The conductors include a first upper conductor connected to an upper electrode of the first semiconductor element through a first upper solder, a first lower conductor connected to a lower electrode of the first semiconductor element through a first lower solder, a second upper conductor connected to an upper electrode of the second semiconductor element through a second upper solder, a second lower conductor connected to a lower electrode of the second semiconductor element through a second lower solder, and a joint conductor connecting the first upper conductor and the second lower conductor through a relay solder. Each solder contains Cu and Sn. Each solder connection target has an Ni layer. A grain size of at least one of the first upper solder, second upper solder, or relay solder is smaller than a grain size of the first and second lower solders.

A power conversion device includes a power conversion unit and a control unit. The power conversion unit includes a first semiconductor module. The first semiconductor module includes a plurality of power semiconductor elements. Some of the plurality of power semiconductor elements are detection target elements. The power conversion unit further includes a temperature sensor and a voltage sensor. The temperature sensor detects a surface temperature of the detection target element as a sensor position temperature. The voltage sensor detects an inter-terminal voltage of the detection target element. The control unit calculates a loss in the detection target element based on the sensor position temperature and the inter-terminal voltage, and estimates a maximum temperature based on the calculated loss.

A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

A semiconductor module includes a wiring board, a semiconductor element disposed on and electrically connected to a conductor pattern of the wiring board, and a wiring member electrically connecting a conductor to an electrode of the semiconductor element. The wiring member includes a first conductor spacer, a second conductor spacer, and a laminate connecting the conductor spacers to each other. The laminate includes a plurality of conductor foils that are disposed in a laminated manner. The plurality of conductor foils includes at least one intermediate conductor foil, and first and second conductor foils sandwiching the intermediate conductor foil interposed therebetween. The intermediate conductor foil includes a void formation area in which a void is formed in the thickness direction between the linking region of the first conductor foil and the linking region of the second conductor foil.

A method for producing a semiconductor component. The method includes: providing a substrate and / or drain layer, a first-type doped drift and / or spread layer applied to the substrate and / or drain layer, a channel layer applied to the drift and / or spread layer, and a first-type doped source layer inserted into the channel layer and / or applied to the channel layer; forming a gate trench, which extends in the vertical direction from the source layer into the drift and / or spread layer; and forming a second-type doped shielding region, which extends in the vertical direction into the drift and / or spread layer. The shielding region has a lateral distance from the gate trench, so that a channel region corresponding to the lateral distance remains in the channel layer, and at least part of the shielding region extends in the vertical direction to below the gate trench.

The utility model relates to wafer plasma surface activation equipment, and belongs to the technical field of equipment for processing semiconductor components. According to the utility model, gas molecules in the chamber are effectively excited through a high-intensity magnetic field generated by the ICP coil, so that high-density and high-activity plasma is formed; the I CP reactor is arranged on the upper side of the activation chamber, the activation chamber and the I CP reactor are isolated through the insulating ceramic isolation plate, I CP electromagnetic induction can penetrate through the isolation plate, and the isolation plate not only ensures the leakproofness of the activation chamber, but also effectively isolates the high-temperature environment of the I CP reactor. The adverse effect of the high temperature in the I CP reactor on the activation chamber is prevented; the I CP coil is arranged between the inner cylinder and the outer cylinder, the heat dissipation fan is arranged on the outer cylinder, and the heat dissipation coil pipe is arranged in the activation chamber, so that the heat dissipation effect is improved, and the temperature in the activation chamber can be effectively reduced.

A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions at both ends of the semiconductor base, and first and second gate conductor layers. A page erase operation, a page write operation, and a page read operation are performed by controlling voltages applied to the first and second impurity regions and the first and second gate conductor layers. In a first page group including at least one page, a refresh operation of increasing positive holes is performed in a memory cell storing logical data “1”. The refresh operation is performed continuously to an N-th page group.

An electronic device including an electronic unit and a functional unit is provided. The electronic unit includes a substrate, a plurality of semiconductor components, and a cover layer. The substrate has a plurality of first side surfaces. The semiconductor components are disposed on the substrate. The cover layer is disposed on the semiconductor components and has a plurality of second side surfaces. The functional unit is disposed on at least one of at least one of the first side surfaces and at least one of the second side surfaces.

A degradation diagnosis system includes a semiconductor element including a gate, a first main terminal that is a source or an emitter, and a second main terminal that is a drain or a collector. The degradation diagnosis system includes a push-pull circuit, a gate resistance provided in the push-pull circuit or between the push-pull circuit and the gate, and a capacitor coupled in parallel with the gate resistance. The degradation diagnosis system includes a degradation diagnosis device configured to diagnose degradation of the semiconductor element based on a capacitor voltage that is generated across the capacitor.

Methods, systems, and devices for pass-through power delivery for logic-on-top semiconductor systems are described. A semiconductor system may be configured with a two-dimensional pattern of power delivery conductors that pass through semiconductor components of a stack (e.g., through one or more memory stacks), providing a more-distributed delivery of power to a logic component bonded with the stack. The power delivery conductors may include through-substrate vias that bypass circuitry of the stack, and thus may be allocated for providing power to the logic component. Such techniques may be combined with a redistribution component, such as a package substrate or interposer (e.g., opposite the logic component in the heterogeneous stack), which may include redistribution conductors that convert from relatively fewer interconnections at a surface of the semiconductor system (e.g., for solder interconnection) to relatively more interconnections at a surface bonded with the stack (e.g., for hybrid bonding interconnection).

A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.

This power semiconductor module comprises: a substrate; a plurality of power semiconductor elements arranged on the substrate; a first terminal connected to first electrodes of the plurality of power semiconductor elements; a second terminal connected to second electrodes of the plurality of power semiconductor elements; and a third terminal connected to third electrodes of the plurality of power semiconductor elements. One or more terminals from among the first to third terminals cross the upper sides of the plurality of power semiconductor elements so as to be commonly and electrically connected to the upper sides of the plurality of power semiconductor elements.

A semiconductor component, in particular a transistor. The semiconductor component includes: a first-type-doped source layer, an second-type-doped channel layer, a first-type-doped drift region, a substrate layer, the channel layer being located between the source layer and the substrate layer and is adjacent to the source layer, wherein the drift region is located between the channel layer and the substrate layer, wherein the semiconductor component includes a gate trench, which extends vertically from the source layer toward the drift region and is adjacent to the channel layer and at least a portion of the source layer; and a second-type-doped shielding region, which extends vertically from the source layer toward the drift region, is adjacent to the channel layer and the source layer and is laterally separated from the gate trench, and wherein the drift region includes a plurality of first-type-doped drift layers, which each have a different doping concentration.

A semiconductor module includes first to fourth semiconductor elements, a plurality of wiring patterns, a first power source terminal, second power source terminals, a first intermediate point terminal and a second intermediate point terminal, and a full bridge circuit is formed in the semiconductor module. The semiconductor module further includes a temperature detection element; first and second temperature detection wiring patterns; and first and second temperature detection terminals. The temperature detection element is disposed in a region surrounded by a first switching path and a second switching path. The semiconductor module is configured to reduce noises caused by a parasitic capacitance between a second wiring pattern and a first temperature detection wiring pattern, and a parasitic capacitance between a fourth wiring pattern and a first temperature detection wiring pattern.

This semiconductor device comprises: a substrate (50) including a surface metal body (52) connected to a semiconductor element; and a sealing body (30) for sealing the semiconductor element and at least a part of the substrate (50) including the surface metal body (52). High-adhesion sections (527a, 527b, 527c) having an enhanced degree of adhesion to the sealing body (30) and a low-adhesion section (527p) having a lower degree of adhesion to the sealing body (30) than the high-adhesion sections are formed in the portion of the surface metal body (52) that is in contact with the sealing body (30). At least some of the high-adhesion sections are disposed between parts of the substrate (50) having different potentials.

A tunable laser includes: a channel selection assembly, a plurality of optical amplifiers, a micro-ring filtering assembly and a reflection assembly. The micro-ring filtering assembly is coupled to the reflection assembly, and operation wavelength ranges of the respective optical amplifiers are different. The channel selection assembly is used for selecting any optical amplifier to input a gain optical signal to the micro-ring filtering assembly. The micro-ring filtering assembly is used for filtering the gain optical signal under a vernier caliper effect to obtain filtered optical signals, and then inputting same into the reflection assembly. The reflection assembly is used for outputting some of the filtered optical signal outwards, and reflecting, after the remaining optical signals pass through the micro-ring filtering assembly, the remaining optical signals to an optical amplifier currently selected by the channel selection assembly.

An optical module includes a base material, an optical semiconductor element, an optical circuit element, a first adhesive, and a second adhesive. The base material has a first surface. The optical semiconductor element has a first optical port and is provided on the first surface. The optical circuit element has a second optical port, which faces the first optical port and is optically coupled to the first optical port, in a side surface thereof. The optical circuit element is disposed alongside the optical semiconductor element on the first surface. The first adhesive mainly includes a UV curable material. The first adhesive fixes the optical semiconductor element to the first surface and has a first thermal conductivity. The second adhesive mainly includes a thermosetting material and has a second thermal conductivity higher than the first thermal conductivity. The second adhesive fixes the optical semiconductor element to the first surface.

To provide a semiconductor module capable of more accurately performing a temperature detection.SOLUTION: A semiconductor module 1 includes: first to fourth semiconductor elements Q1 to Q4; a plurality of wiring patterns; a first power supply terminal 51; second power supply terminals 52 and 53; a first midpoint terminal 61; and a second midpoint terminal 62, in which a full bridge circuit is configured. The semiconductor module 1 further includes: a temperature detection element 90; first and second temperature detection wiring patterns 93 and 94; and first and second temperature detection terminals T1 and T2. The temperature detection element 90 is disposed in a region surrounded by a first switching path A and a second switching path B, and is configured to reduce noise based on a parasitic capacitance between a second wiring pattern 20 and the first temperature detection wiring pattern 93 and the parasitic capacitance between a fourth wiring pattern 40 and the first temperature detection wiring pattern 93.SELECTED DRAWING: Figure 4

In a semiconductor element including a silicon carbide heterostructure, the resistance component generated due to spontaneous polarization at the hetero-matched interface is suppressed, thereby reducing the specific on-resistance of the semiconductor element. A hetero-matched interface (S X ) and 1 × 10 19 cm -3 The tunnel doped region (D T By providing the layer, a carrier transport mechanism by tunneling is realized, and the specific on-resistance of the semiconductor element is kept low.

A semiconductor device includes: a semiconductor element; a support member; a bonding layer interposed between the semiconductor element and the support member; and a sealing resin that covers the semiconductor element and at least a portion of the support member, wherein the bonding layer is a layer in which a layer containing first metal and a layer containing second metal are integrated without going through a molten state, and wherein the support member includes a first surface facing in a thickness direction and facing a side on which the semiconductor element is located, and a plurality of first recesses located outside the bonding layer and recessed from the first surface when viewed along the thickness direction.

A polishing liquid containing: abrasive grains; an additive; and water, in which the additive includes (A1) a polyglycerol having a weight average molecular weight of 350 to 2800 and (B) a compound having two or more nitrogen atoms to which a hydroxyalkyl group is bonded. A polishing liquid containing: abrasive grains; an additive; and water, in which the additive includes (A2) a polyglycerol having a hydroxyl value of 800 to 1000 mgKOH / g and (B) a compound having two or more nitrogen atoms to which a hydroxyalkyl group is bonded.

A semiconductor device (100, 100A, 100B, 100C, 100D, 100E) comprises: an insulating substrate (10); at least one semiconductor element (20); a printed circuit board (30); and a connecting material (41). The insulating substrate has a first surface and a first electrode (12) disposed on the first surface. Each of the at least one semiconductor element is disposed on the first electrode, and has a second surface as well as a second electrode (21) and a third electrode (22) that are disposed on the second surface. The third electrode has a potential differing from that of the second electrode. The printed circuit board has: a circuit that drives the at least one semiconductor element; an input pattern (36a) and an output pattern (36c) that are disposed inside the printed circuit board; an input terminal (37a) and an output terminal (37c) that protrude from the printed circuit board; a third surface that faces the first surface and the second surface; and a plurality of third electrodes (31) that are disposed on the third surface.

Provided is an electric circuit body including: a power semiconductor element; a first conductor plate configured to be connected to one surface of the power semiconductor element; a first sheet-shaped member having a first resin insulation layer and configured to at least cover a surface of the first conductor plate; a sealing material configured to seal each of the power semiconductor element, the first conductor plate, and an end of the first sheet-shaped member; and a first cooling member configured to be adhesively attached to the first sheet-shaped member. In the electric circuit body, the first sheet-shaped member includes: an embedded portion where the end of the first sheet-shaped member is covered with the sealing material; a heat dissipation surface as a region to overlap the surface of the first conductor plate; and a margin as a region between the embedded portion and the heat dissipation surface, the margin is located more inward than the heat dissipation surface, and the embedded portion is located more inward than the margin.

Single switch power module (114) comprising: - A molded body (130), wherein the molded body (130) at least partially encloses one or more semiconductor components (106) arranged on a substrate (128), and - A lead frame (108), the lead frame (108) having a first part (110) and a second part (112), the first part (110) having a gate (118), a source (120) and a power source (122) and the second part (112) having a power drain (124), wherein the substrate (128) can be placed asymmetrically to the longitudinal direction (104) and / or the one or more semiconductor components (106) are placed parallel to the longitudinal direction (104), wherein a connection for electrically contacting the power source (122) to a semiconductor component source is effected via a fork-shaped embodiment (140) of the power source (122), wherein the fork-shaped embodiment (140) is designed such that universal electrical contacting for semiconductor components (106) of a different semiconductor component size is ensured.

A bonded structure is disclosed. The bonded structure can comprise a first semiconductor element having a first contact pad. An interposer can include a second contact pad on a first side of the interposer and a third contact pad and a fourth contact pad on a second side of the interposer opposite the first side, the second contact pad bonded to the first contact pad; a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad. A switching circuitry can be configured to switch between a first electrical connection between the second and third contact pads and a second electrical connection between the second and fourth contact pads.

A circuit assembly includes first and second circuit carriers and a semiconductor component arranged between the circuit carriers and having first and second load terminals. The first load terminal has a first load terminal surface which faces the first circuit carrier and around which an electrically insulating edging structure is arranged. The second load terminal has a second load terminal surface which faces the second circuit carrier and is larger than the first load terminal surface. The first circuit carrier has a first through-contact which electrically connects the first load terminal surface to a first conductor path, which runs inside the first circuit carrier or on a top side of the first circuit carrier facing away from the semiconductor component. The second circuit carrier has a top side facing the semiconductor component and formed by a first electrically conductive layer that is electrically connected to the second load terminal surface.

In a semiconductor device, a first wiring member is electrically connected to a first main electrode on a first surface of a semiconductor element, and a second wiring member is electrically connected to a second main electrode on a second surface of the semiconductor element. An encapsulating body encapsulates at least a part of each of the first and second wiring members, the semiconductor element and a bonding wire. The semiconductor element has a protective film on the first surface of the semiconductor substrate, and the pad has an exposed surface exposed from an opening of the protective film. The exposed surface includes a connection area to which the bonding wire is connected, and a peripheral area on a periphery of the connection area. The peripheral area has a surface that defines an angle of 90 degrees or less relative to a surface of the connection area.

An optoelectronic semiconductor device (1) is specified, comprising: - a stack of layers (10) comprising a first main surface (10A) and a second main surface (10C) opposite the first main surface (10A), as well as at least one side surface (10B) that laterally bounds the stack of layers (10) and connects the first and second main surfaces (10A, 10C), - a metallic reflective layer (3) extending from the second main surface (10C) to at least one side surface (10B) and having an end region (3A) facing away from the second main surface (10C), and - an encapsulation (5) extending from the second main surface (10C) across the side surface (10B) to the first main surface (10A) and comprising a first insulating layer (2) and a second insulating layer (4), wherein the metallic reflective layer (3) is arranged on the at least one side surface (10B) between the first and second insulating layers (2, 4) and the end region (3A) is covered by the encapsulation (5). Furthermore, a method for manufacturing an optoelectronic semiconductor device is described.

A semiconductor device includes a semiconductor element, a sealing member, and a rewiring layer. The rewiring layer includes an insulating layer covering a front surface of the semiconductor element and a part of the sealing member, an electrode connected to the semiconductor element, and an externally-exposed layer being conductive and covering a portion of the electrode exposed from the insulating layer.