4869 results about "Semiconductor components" patented technology

A semiconductor element is provided with a micro-structured metal oxide layer over a conductive feature at a hybrid bonding surface. The micro-structured metal oxide layer comprises fine metal oxide grains, such as nanograins. The grains can be formed over the conductive feature by oxidizing a metal comprised in the conductive feature, or by providing a metal oxide over the conductive feature. When directly bonded to another element, the micro-structured metal oxide layer can form strong bonds at the bonding interface at substantially reduced annealing temperature.

A method for surface defect inspection can comprise obtaining topographical data from one or more portions of a semiconductor element. The semiconductor element can have a surface comprising a dielectric and a plurality of metal pads. The method can further comprise processing the topographical data of the one or more portions of the semiconductor element to determine at least a first property of the plurality of metal pads, computing at least one variability value for the first property, and identifying candidate defects in the one or more portions of the semiconductor element based at least in part on the at least one variability value.

A semiconductor device includes semiconductor elements and conductors. The conductors include a first upper conductor connected to an upper electrode of the first semiconductor element through a first upper solder, a first lower conductor connected to a lower electrode of the first semiconductor element through a first lower solder, a second upper conductor connected to an upper electrode of the second semiconductor element through a second upper solder, a second lower conductor connected to a lower electrode of the second semiconductor element through a second lower solder, and a joint conductor connecting the first upper conductor and the second lower conductor through a relay solder. Each solder contains Cu and Sn. Each solder connection target has an Ni layer. A grain size of at least one of the first upper solder, second upper solder, or relay solder is smaller than a grain size of the first and second lower solders.

A power conversion device includes a power conversion unit and a control unit. The power conversion unit includes a first semiconductor module. The first semiconductor module includes a plurality of power semiconductor elements. Some of the plurality of power semiconductor elements are detection target elements. The power conversion unit further includes a temperature sensor and a voltage sensor. The temperature sensor detects a surface temperature of the detection target element as a sensor position temperature. The voltage sensor detects an inter-terminal voltage of the detection target element. The control unit calculates a loss in the detection target element based on the sensor position temperature and the inter-terminal voltage, and estimates a maximum temperature based on the calculated loss.

The invention provides a semiconductor element and a preparation method thereof. The semiconductor device includes a first substrate including a front surface and a back surface; a first passivation layer over the front surface; the second passivation layer is positioned above the back surface and is provided with an upper surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating the second passivation layer and the first substrate and electrically coupled to the through substrate via of the conductive feature; and a polymer pad between the TSV and the first substrate, where an upper surface of the polymer pad is lower than the upper surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer pad and the TSV, and between the interconnect structure and the TSV; and an adhesive layer between the barrier layer and the TSV.

The invention provides a preparation method of a semiconductor element. The method includes forming a conductive feature in a first passivation layer over a front surface of a first substrate; forming a second passivation layer over a back surface of the first substrate; forming a first recess in an upper surface of the second passivation layer to expose the conductive feature; conformally forming an isolation pad on a side wall of the first recess; performing a pulse etch operation to conformally form a polymer liner on the sidewall of the isolation liner, wherein an upper surface of the polymer liner is lower than the upper surface of the second passivation layer; conformally forming a barrier layer over the polymer liner and the release liner; conformally forming an adhesive layer on the barrier layer; and forming a conductive material in the first recess to form a through-substrate via.

A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a plate line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the plate line of the memory cell connected to an unselected page.

A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

A semiconductor package includes a semiconductor element, at least one electronic die, at least one optical die, an encapsulant, and a substrate. The semiconductor element has a first side and a second side opposing to the first side. The at least one electronic die is disposed over the first side. The at least one optical die is disposed over the first side and next to the at least one electronic die. The encapsulant is disposed on the first side and covers the at least one electronic die, where a sidewall of the at least one optical die is distant from the encapsulant, and a sidewall of the encapsulant is aligned with a sidewall of the semiconductor element. The substrate is disposed over the second side, where the at least one electronic die is electrically coupled to the substrate and the at least one optical die through the semiconductor element.

A semiconductor module includes a wiring board, a semiconductor element disposed on and electrically connected to a conductor pattern of the wiring board, and a wiring member electrically connecting a conductor to an electrode of the semiconductor element. The wiring member includes a first conductor spacer, a second conductor spacer, and a laminate connecting the conductor spacers to each other. The laminate includes a plurality of conductor foils that are disposed in a laminated manner. The plurality of conductor foils includes at least one intermediate conductor foil, and first and second conductor foils sandwiching the intermediate conductor foil interposed therebetween. The intermediate conductor foil includes a void formation area in which a void is formed in the thickness direction between the linking region of the first conductor foil and the linking region of the second conductor foil.

A lateral high-voltage semiconductor device and a method of forming a lateral high-voltage semiconductor device are disclosed wherein the lateral high-voltage semiconductor device (1) comprises a semiconductor substrate (2) having a front side and a semiconductor element (10). The semiconductor element comprises a first semiconductor region (11) of a first conductivity type formed in the semiconductor substrate, a second semiconductor region (12) formed in the semiconductor substrate and spaced apart from the first semiconductor region (11) in a first lateral direction parallel to the front side, and an extension region (13) adjoining the second semiconductor region (12). A lateral high-voltage semiconductor device (1) is configured to control a load current between a first semiconductor region and a second semiconductor region. The extension region (13) extends along the front side of the semiconductor substrate and comprises at least one mesa (14) protruding at the front side (101) of the semiconductor substrate.

An electronic device comprises a substrate, a semiconductor element disposed on the substrate and comprising a top surface, a bottom surface and a side surface connected between the top surface and the bottom surface, and a shielding element comprising a first portion, a second portion and a third portion. The first portion is disposed between the bottom surface of the semiconductor layer and the substrate, the second portion surrounds the side surface of the semiconductor element, and the semiconductor element is disposed between the first portion and the third portion.

A semiconductor device includes an output element, a temperature detection circuit, a current limiting circuit, and an overcurrent detection circuit. The output element is a power semiconductor element that drives a load, and is turned on by applying a predetermined turn-on voltage to a gate of the output element in a normal state. The temperature detection circuit detects the temperature of the output element as a detected temperature, during the operation of the output element. The overcurrent detection circuit detects an overcurrent state of the output element. When the overcurrent state is detected and the detected temperature exceeds a set temperature, the current limiting circuit sets a gate voltage of the output element to a set voltage lower than the predetermined turn-on voltage. In addition, the current limiting circuit increases the set voltage in stages as the temperature decreases.

A method for producing a semiconductor component. The method includes: providing a substrate and / or drain layer, a first-type doped drift and / or spread layer applied to the substrate and / or drain layer, a channel layer applied to the drift and / or spread layer, and a first-type doped source layer inserted into the channel layer and / or applied to the channel layer; forming a gate trench, which extends in the vertical direction from the source layer into the drift and / or spread layer; and forming a second-type doped shielding region, which extends in the vertical direction into the drift and / or spread layer. The shielding region has a lateral distance from the gate trench, so that a channel region corresponding to the lateral distance remains in the channel layer, and at least part of the shielding region extends in the vertical direction to below the gate trench.

The invention provides a power module. The power module comprises a substrate, a semiconductor element, a plurality of pins and a packaging body, the substrate has a first metal surface. The semiconductor element is disposed on the first metal surface. The plurality of pins extend from the first metal surface and are configured to be electrically connected to the semiconductor element. The packaging body is configured to cover the first metal surface and the semiconductor element, and the packaging body partially covers each of the pins. An interval is arranged between every two adjacent pins of the pins, and a separating element is arranged in the interval so as to increase a creepage distance between every two adjacent pins of the pins.

A leakage current detection and interruption (LCDI) device includes a leakage current detection module, including a first and a second leakage current detection line and at least one resistive element and / or at least one semiconductor element, configured to detect a leakage current signal on the first or second current-carrying line and to generate a leakage fault signal in response to detecting the leakage current signal. The first and second leakage current detection lines are electrically insulated from each other, and respectively cover one of the first and second current-carrying lines. The at least one resistive element and / or semiconductor element is coupled in series between the first and second leakage current detection lines to form a current path for detecting an open circuit fault in the leakage current detection module. By detecting the fault in the first and second leakage current detection lines, the reliability of the LCDI device is improved.

A memory device uses semiconductor elements. By controlling voltages applied to plate lines, word lines, source lines, and bit lines, the memory device performs a data write operation of holding positive hole groups formed by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base material, and a data erase operation of removing positive hole groups from inside the semiconductor base material. The memory device includes a block made up of memory cells, which are arrayed in a matrix. Storage data of memory cells connected with a first word line, i.e., a selected one of the word lines, in the block is read to the bit lines by applying a first voltage to the first word line, and a second voltage to a second word line adjacent to the first word line.

Decoder circuit, memory device, and control method are disclosed. The decoder circuit includes a decoding circuit and a power supply control circuit including: a first transistor, its input is connected to a low-level voltage node, and its output outputs a first ground voltage; a second transistor, its input is connected to a high-level voltage node, and its output outputs a first voltage; and a reverse circuit, its input receives a semiconductor component enabling signal, and its output is connected to the control terminal of one of the first or second transistor; and the control terminal of the first or second transistor not connected to the reverse circuit receives the semiconductor component enabling signal. The decoding circuit includes sub-circuits, wherein a power supply interface of sub-circuit is connected to the output of second transistor, or a grounding interface of sub-circuit is connected to the output of first transistor.

A semiconductor device assembly is disclosed. The semiconductor device assembly includes a first semiconductor die and second semiconductor dies and an additional semiconductor component coupled with the logic die. Dielectric peripheral material is disposed along sidewalls of the first die and extends beyond a first footprint of the first die. A gap fill material is disposed at the first die and at the dielectric peripheral material beyond a second footprint of the second semiconductor dies and a third footprint of the additional semiconductor component such that the gap fill material at least partially surrounds the second semiconductor dies and the additional semiconductor component.

The invention relates to the field of electronic packaging materials, and discloses an epoxy molding compound as well as a preparation method and application thereof. Based on the total weight of the epoxy molding compound, the epoxy molding compound contains 13 to 20 weight percent of epoxy resin, 6 to 14 weight percent of a curing agent, 0.05 to 0.2 weight percent of a curing accelerator, 70 to 78 weight percent of filler, 0.1 to 1 weight percent of a coupling agent, 0.1 to 4 weight percent of a stress modifier, 0.1 to 2 weight percent of a release agent, 3 to 8 weight percent of a flame retardant, 0.01 to 0.3 weight percent of an ion trapping agent and 0.3 to 0.6 weight percent of a coloring agent, wherein the curing accelerator is 2-undecylimidazole, and the curing accelerator is 2-undecylimidazole; and the coupling agent is gamma-mercaptopropyl trimethoxy silane and / or gamma-glycidyl ether oxypropyl trimethoxy silane. The invention further discloses a preparation method of the silane coupling agent. The epoxy molding compound is simple to prepare, shows relatively high bonding performance and demolding performance when being used for packaging semiconductor components, and has relatively high operability and reliability.

The utility model relates to wafer plasma surface activation equipment, and belongs to the technical field of equipment for processing semiconductor components. According to the utility model, gas molecules in the chamber are effectively excited through a high-intensity magnetic field generated by the ICP coil, so that high-density and high-activity plasma is formed; the I CP reactor is arranged on the upper side of the activation chamber, the activation chamber and the I CP reactor are isolated through the insulating ceramic isolation plate, I CP electromagnetic induction can penetrate through the isolation plate, and the isolation plate not only ensures the leakproofness of the activation chamber, but also effectively isolates the high-temperature environment of the I CP reactor. The adverse effect of the high temperature in the I CP reactor on the activation chamber is prevented; the I CP coil is arranged between the inner cylinder and the outer cylinder, the heat dissipation fan is arranged on the outer cylinder, and the heat dissipation coil pipe is arranged in the activation chamber, so that the heat dissipation effect is improved, and the temperature in the activation chamber can be effectively reduced.

To improve the characteristics of an optical semiconductor element.SOLUTION: An optical semiconductor element according to the present invention includes a first active layer having an emission and reception wavelength of a first wavelength, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer having an emission and reception wavelength of a second wavelength, and the first and second active layers include Sb, and the tunnel junction layer has a p-type InAs layer and an n-type InAs layer.SELECTED DRAWING: Figure 1

An embodiment includes a controller and a driver. The controller controls to drive a semiconductor element having a first gate electrode and a second gate electrode base on a control signal. The driver outputs a first driving signal to the first gate electrode and a second driving signal to the second gate electrode. The first driving signal drives the first gate electrode at ON or OFF timing of the control signal. The second driving signal drives the second gate electrode a timing earlier than the OFF timing of the control signal. The driver switches output impedances corresponding to the switching speed of the semiconductor element.

The invention relates to the technical field of semiconductor part materials, in particular to a high-purity low-resistivity beta-phase silicon carbide material and a preparation method and application thereof. The method specifically comprises the following steps: soaking washed rice husks in a weakly acidic aqueous solution, boiling the rice husks in an acidic aqueous solution before use, and cleaning and drying the rice husks; carrying out low-temperature carbonization on the dried rice hulls, cooling, and then carrying out ball milling and sieving; further carrying out water-bath heating and stirring with an aqueous alkali solution, and filtering; the filtrate is a silicate aqueous solution B; drying the filter residue D; the filter residues D are subjected to heat preservation, cooling and washing, and rice husk carbon E is obtained and dried; carrying out ball milling on the silicate aqueous solution B and the rice husk carbon E, and drying to constant weight to obtain a loose block F; burning the loose block F to obtain beta-SiC powder; the beta-SiC powder and the superfine silicon carbide powder are mixed and sintered, and the beta-SiC sintered body is obtained. The silicon carbide material prepared by the invention can meet the requirements of high purity and high density required in the semiconductor manufacturing process.

A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions at both ends of the semiconductor base, and first and second gate conductor layers. A page erase operation, a page write operation, and a page read operation are performed by controlling voltages applied to the first and second impurity regions and the first and second gate conductor layers. In a first page group including at least one page, a refresh operation of increasing positive holes is performed in a memory cell storing logical data “1”. The refresh operation is performed continuously to an N-th page group.

An electronic device including an electronic unit and a functional unit is provided. The electronic unit includes a substrate, a plurality of semiconductor components, and a cover layer. The substrate has a plurality of first side surfaces. The semiconductor components are disposed on the substrate. The cover layer is disposed on the semiconductor components and has a plurality of second side surfaces. The functional unit is disposed on at least one of at least one of the first side surfaces and at least one of the second side surfaces.

The invention relates to a lateral high-voltage semiconductor device (1) comprising a semiconductor substrate (2) with a front face and a semiconductor element (10). The semiconductor element comprises a first semiconductor region (11) of a first conductivity type formed within the semiconductor substrate, a second semiconductor region (12) formed within the semiconductor substrate and spaced apart from the first semiconductor region (11) in a first lateral direction (x) parallel to the front face, and an extension region (13) adjacent to the second semiconductor region (12). The semiconductor device (1) is configured to control a load current between the first semiconductor region and the second semiconductor region. The extension region (13) extends along the front face of the semiconductor substrate and comprises at least one mesa (14) projecting from the front face (101) of the semiconductor substrate.

The present invention provides: a sealing sheet which is excellent in terms of embeddability and seamless properties in cases where an optical semiconductor element is sealed therewith, and which is excellent in terms of embeddability and seamless properties even in cases where the sealing sheet is applied to a display that uses a micro LED as a light source; and a display. Provided is a sealing sheet (1) for sealing an optical semiconductor element (5), the sealing sheet (1) including a protective film and a resin composition layer (2) arranged in this order. The resin composition layer (2) contains 5.3-48.2 parts by mass of metal oxide particles (B) relative to a total of 100 parts by mass of a resin (A), a monomer, and an oligomer. The number average primary particle diameter of the metal oxide particles (B) is 5-50 nm, and the refractive index of the resin composition layer (2) is 1.45-1.65.

A degradation diagnosis system includes a semiconductor element including a gate, a first main terminal that is a source or an emitter, and a second main terminal that is a drain or a collector. The degradation diagnosis system includes a push-pull circuit, a gate resistance provided in the push-pull circuit or between the push-pull circuit and the gate, and a capacitor coupled in parallel with the gate resistance. The degradation diagnosis system includes a degradation diagnosis device configured to diagnose degradation of the semiconductor element based on a capacitor voltage that is generated across the capacitor.

Methods, systems, and devices for pass-through power delivery for logic-on-top semiconductor systems are described. A semiconductor system may be configured with a two-dimensional pattern of power delivery conductors that pass through semiconductor components of a stack (e.g., through one or more memory stacks), providing a more-distributed delivery of power to a logic component bonded with the stack. The power delivery conductors may include through-substrate vias that bypass circuitry of the stack, and thus may be allocated for providing power to the logic component. Such techniques may be combined with a redistribution component, such as a package substrate or interposer (e.g., opposite the logic component in the heterogeneous stack), which may include redistribution conductors that convert from relatively fewer interconnections at a surface of the semiconductor system (e.g., for solder interconnection) to relatively more interconnections at a surface bonded with the stack (e.g., for hybrid bonding interconnection).