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738 results about "Monocrystalline silicon" patented technology

Monocrystalline silicon (also called single-crystal silicon (or Si), mono c-Si or simply mono-Si) is the base material for silicon-based discrete components and integrated circuits used in virtually all modern electronic equipment. Mono-Si also serves as a photovoltaic, light-absorbing material in the manufacture of solar cells.

Treatment recovery method for monocrystalline silicon cutting waste liquor

A treatment and reclaim method of single crystal silicon cutting waste liquid comprises the steps: (1). the waste liquid is treated with diluted hydrochloric acid then is stirred and mixed to enable the liquid to become a flowable mixture; (2). the mixed material is heated to separate solid and liquid, by which water and polyethylene glycol are extracted. The polyethylene glycol is obtained by the process of condensation, dehydration and recovery. The solid after being separated is a crude solid mixture of silicon carbide and silicon; (3). the quadratic-cleaning solid mixture of silicon diluted and silicon is obtained after quadratic cleaning to the crude solid mixture obtained in step 2; (4). the mixture is treated by mixed acid liquid comprising HNO3+HF to recover and get silicon diluted and silicon. The method has easy operation, simple equipment, low cost, high efficiency in treatment and recovery. The allover recovery rate calculated based on the weight of waste liquid can reach 26-46 percent and the recovering material can reach or close to the standard index, and can be directly used in solar energy battery production, so the invented method has good economic benefit and also can greatly contribute to environment protective, thereby having large exploration prospect.
Owner:金柏林

Solar cell with composite dielectric passivation layer structure and preparation process thereof

The invention discloses a solar cell with a composite dielectric passivation layer structure and a preparation process thereof. A silicon oxide film, an alumina film and a silicon nitride or silicon oxynitride film are deposited in turn on the front, back and sides of a p-type silicon substrate to form a composite dielectric film on the whole surface, and windows are opened locally to lead electrodes out. Through aluminum oxide, silicon dioxide, silicon oxynitride, silicon nitride with different refractive indexes and a back surface passivation layer with a laminated structure of the materials, the back surface recombination rate is greatly reduced, the back reflectivity is improved, the CTM of a module is reduced, and the light attenuation and heat-assisted light attenuation and the anti-PID performance of the cell are improved. The structure can be made on a boron/gallium-doped p-type monocrystalline silicon, p-type polycrystalline silicon or p-type monocrystalline-silicon-like substrate, and a passivation method based on the composite dielectric film passivation structure can be used to manufacture PERC cells, double-sided PERC+ cells and imbricate PERC cells. Based on the preparation process steps and sequence, the corresponding preparation mode and the process parameter range of the laminated structure, the making of the cell can be well completed.
Owner:TONGWEI SOLAR ENERGY CHENGDU CO LID +2

Device for measuring object stress by utilizing graphene membrane, and preparation method and testing method of device

The invention discloses a device for measuring object stress by utilizing a graphene membrane, and a preparation method and a testing method of the device. The testing method is characterized in that graphene is arranged on a flexible stretchable substrate by utilizing a growth and transfer technology of the graphene and is tightly adhered to the surface of a to-be-measured object or a single crystal silicon substrate which is provided with a through hole, a characteristic peak of a Raman spectrum of the graphene can be subjected to shifting and splitting when the to-be-measured object is subjected to deformation or gas pressure difference exists between the internal part and the external part of the through hole, and sensing on strain or gas pressure can be realized basing on shifting and splitting amount of the characteristic peak. According to the device, the preparation method and the testing method, disclosed by the invention, the technical design is simple, the performance is stable, non-contact with the to-be-measured object is realized, and the complexity of an electrical measurement method which is in need of arranging leading wires can be avoided; the strain loading range is large, and the stress measurement accuracy degree is high.
Owner:西安超宇微晶新材料技术有限公司

Double side photovoltaic battery wall component and manufacturing process thereof

The invention belongs to the field of photoelectricity and building materials and particularly relates to a double-side photovoltaic battery curtain wall assembly and the fabrication method thereof. The double-side photovoltaic battery curtain wall assembly comprises an upper glass layer, a bottom glass layer, and solar battery slices, wherein the upper glass layer, the bottom glass layer and the solar battery slices are hermetically bonded with each other through EVA; the solar battery slice is a double-side monocrystalline silicon solar battery slice; double-side monocrystalline silicon solar battery slices are connected with each other through interconnection strips; and each solar battery slice groups is connected with a terminal box through a bus bar. The fabrication method of the double-side photovoltaic battery curtain wall assembly is also provided. The invention can solve the purpose problem of double-side battery, so that the double-side batteries can be used in the photoelectrical field more generally. The double-side solar battery, i.e. the positive and the negative side of the battery slice, can generate corresponding power under the irradiation of solar light, so that the power of the photovoltaic assembly is increased indirectly, the conversion efficiency of the single battery slice is improved.
Owner:山东科明太阳能光伏有限公司

Groove type atomic gas cavity and atomic clock physical system formed by same

The invention relates to a groove type atomic gas cavity produced by applying MEMS technology and an atomic clock physical system formed by the same. The cavity is characterized in that the cavity is formed in such a manner that a silicon wafer with a groove and Pyrex glass sheets define a cavity structure through bonding; the cavity structure is used for alkali metal atom vapor and buffer gases to fill in; the cross section of the groove is in a shape of inverted trapezoid; and the groove comprises a bottom surface and side walls forming included angles with the bottom surface. The cavity is manufactured based on MEMS (micro-electro-mechanical system) technology. The silicon groove is formed through anisotropic etching of the (100) monocrystalline wafer. The groove type cavity is manufactured through silicon-glass anode bonding. The side walls of the cavity are {111} crystal planes of the silicon wafer. The cavity and the system have the following beneficial effects: by utilizing the cavity, the distance between two reflectors in the cavity is easy to enlarge through atomic cavity dimension design, thus increasing the length of the interaction space between laser and atomic gas, enhancing the signal to noise ratio of the CPT (coherent population trapping) signal and being beneficial to improvement of the frequency stability of the micro CPT atomic clock.
Owner:SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI

Semiconductor substrate, semiconductor device, and manufacturing methods for them

InactiveUS20050245046A1Improve performanceLess varied in characteristicTransistorStatic indicating devicesLOCOSEngineering
The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film. On this account, on fabricating the semiconductor device having a high-performance integration system by forming the non-singlecrystalline Si semiconductor element and the singlecrystalline Si semiconductor element on the large insulating substrate, the process for making the singlecrystalline Si is simplified. Further, the foregoing arrangement provides a semiconductor substrate and a fabrication method thereof, which ensures device isolation of the minute singlecrystalline Si semiconductor element without highly-accurate photolithography, when the singlecrystalline Si semiconductor element is transferred onto the large insulating substrate.
Owner:SHARP KK

NAND memory and preparing method thereof

The invention relates to a NAND memory and a preparing method thereof. The NAND memory comprises a plurality of NAND strings and a monocrystalline silicon layer formed on the plurality of NAND strings. The monocrystalline silicon layer is in contact connection with the NAND strings. Each of the said NAND strings comprises a plurality of conductors/insulator lamination layers, a semi-conductor channel which extends at the vertical direction and traverses through the plurality of conductors/insulator lamination layers; a tunnel layer formed between the plurality of conductors/insulator lamination layers and the semi-conductor channel; and a memory cell layer formed between the tunnel layer and the plurality of conductors/insulator lamination layers. The invention is advantageous in that through separating the preparation of array devices and peripheral devices, it can be prevented that the producing of one device will affect that of the other device; the problem of the prior art that thetemperature is limited due to the fact that the producing of the latter layer is affected by the producing of the former layer can be resolved; good peripheral device performance can be obtained; asthe array device is superposed on the peripheral device, high device density can be realized.
Owner:YANGTZE MEMORY TECH CO LTD

Zr-Co-Re thin film getter provided with protection layer, and preparation method thereof

The invention relates to a Zr-Co-Re thin film getter provided with a protection layer, and a preparation method thereof. The Zr-Co-Re thin film getter is composed of a getter layer and the protection layer; main components of the getter layer are Zr, Co, and one or more selected form rare earth elements La, Ce, Pr, and Nd; and main component of the protection layer is Ni. Pulsed laser deposition film plating is adopted, and deposition of the double-layer structured thin film getter containing the protection layer and the getter layer on texture monocrystalline silicon is carried out. The texture substrate is capable of increasing effective area of the getter thin film, and so that inspiratory flow rate and inspiratory capacity are increased. The surface of the getter layer is plated with a Ni protection layer; Ni is capable of realizing dissociation of hydrogen, and increasing absorption amount of hydrogen; and the Ni protection layer is capable of inhibiting absorption of oxygen and reducing activation temperature. Activation of the Zr-Co-Re thin film getter can be realized in roasting processes at a temperature of 180 to 350 DEG C; after roasting, the Zr-Co-Re thin film getter possesses excellent inspiration performance at room temperature, can be used for internal gas residue removing of high vacuum microelectronic devices.
Owner:GENERAL RESEARCH INSTITUTE FOR NONFERROUS METALS BEIJNG

Method for detecting microdefects of quasi monocrystalline silicon sheets

The invention discloses a method for detecting microdefects of quasi monocrystalline silicon sheets. The method includes a manually and mechanically polishing step of manually and mechanically polishing aquasi monocrystalline silicon sheet to be etched and flushing the quasi monocrystalline silicon sheet with deionized water; a chemical etch polishing step of chemically etching and polishing the silicon sheet subjected to the mechanical polishing and rinsing the silicon sheet with deionized water; a preferential microdefect etching step of carrying out preferential microdefect etching on the silicon sheet subjected to the chemically etching and polishing, rinsing the silicon sheet with deionized water and drying the silicon sheet in a baking oven; and a microdefect observation process of carrying out minority carrier lifetime and iron-boron opposite scanning for the etched silicon chip, observing the minority carrier lifetime scanning color distribution by a metallographic microscope, accurately positioning the microdefect positions, classifying the defect types, positioning and cutting the silicon chip into pieces, and marking the pieces. The method is rapid, accurate, energy-saving, environmental-friendly, pollution-free and highly practical.
Owner:连云港市产品质量监督检验中心

Growth process for N-type solar energy silicon single crystal with minority carrier service life of larger than or equal to 1,000 microseconds

InactiveCN101724899ASolve the problem of low lifespanPractical growing methodPolycrystalline material growthBy pulling from meltCrystal orientationSingle crystal
The invention relates to a growth process for N-type solar energy silicon single crystal with minority carrier service life of larger than or equal to 1,000 microseconds. The appearance is in 6-8 inches, the (100) crystal orientation resistivity range is between 1 omega.cm and 20 omega.cm, the minority carrier service life of the surface and the section is larger than or equal to 1,000 microseconds, the clearance oxygen content [Oi] is smaller than or equal to 17.5ppma, and the substituted carbon content [Cs] is smaller than or equal to 0.5ppma. Phosphorus-doped block-shaped polycrystalline silicon is used as a raw material to prepare the N-type solar energy silicon single crystal. The process comprises the steps of: charging, heating, leading diameter, maintaining equal diameter, collecting, cooling, heating by a program, stably heating and melting the material; after a thermal field in melting silicon is stable, leading the thin diameter, lifting the tail part of a single crystal to the upper edge of a guide cylinder with the cooling time of not larger than three hours. The crystal growth process is practical, has high efficiency and low cost, can prepare the N-type single crystal silicon which is completely larger than or equal to 1,000 microseconds from the head part to the tail part by a CZ method, and creates an industrialized foundation for efficiency improvement of an efficient solar battery.
Owner:任丙彦 +1
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