355 results about "Mos capacitor" patented technology

A voltage controlled LC resonance oscillation circuit has a plurality of capacitive elements connected to an output node. These capacitive elements are applied with voltages at opposing terminals for selecting an oscillating frequency band, so that the oscillating frequency band can be changed step by step in accordance with the selection voltage. The capacitive elements include at least one variable capacitive element such as a MOS capacitor, the capacitance of which is varied in accordance with a voltage applied thereto. The MOS capacitor is similar in structure to a MOS transistor. The variable capacitive element can be supplied at a terminal opposite to the output node with a voltage from a variable voltage source, for example, in place of the selection voltage. The voltage controlled LC resonance oscillation circuit can measure the output amplitude and oscillating frequency without affecting the characteristics thereof, and reduce the parasitic capacitance.

A shared-pixel-type image sensor includes a semiconductor substrate, four photoelectric conversion elements disposed adjacent to one another in one direction on the semiconductor substrate, two first transmission elements transmitting charges accumulated in two adjacent ones of the photoelectric conversion elements to a first floating diffusion region, respectively, two second transmission elements transmitting charges accumulated in the other two adjacent photoelectric conversion elements to a second floating diffusion region electrically coupled with the first floating diffusion region, respectively, MOS capacitors that are electrically coupled with the first or second floating diffusion region, a reset element resetting the charges of the first and second floating diffusion regions to a reference value, and a drive element and an select element outputting the charges of the first or second floating diffusion region.

An on-chip capacitive device comprises a semiconductor substrate, a MOS capacitor formed on the semiconductor substrate, and a metal interconnect capacitor formed at least in part in a region above the MOS capacitor. The MOS capacitor and the metal interconnect capacitor are connected in parallel to form a single capacitive device. The capacitance densities of the MOS capacitor and the metal interconnect capacitor are, thereby, combined. Advantageously, significant capacitance density gains can be achieved without additional processing steps.

A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. The physical size of the MOS capacitor is relatively large (approximately 10 time greater) when compared to a physical size of the storage MOS transistor to establish a large coupling ratio (approximately 90% between the second plate of the MOS capacitor and the floating gate node. When a voltage is applied to the second plate of the MOS capacitor and a voltage applied to the source region or drain region of the MOS transistor establishes a voltage field within the gate oxide of the MOS transistor such that Fowler-Nordheim edge tunnel is initiated.

The invention relates to methods for manufacturing semiconductor devices. Processes are disclosed for implementing suspended single crystal silicon nano wires (NWs) using a combination of anisotropic and isotropic etches and spacer creation for sidewall protection. The core dimensions of the NWs are adjustable with the integration sequences: they can be triangular, rectangular, quasi-circular, or an alternative polygonal shape. Depending on the length of the NWs, going from the sub-micron to millimeter range, the NWs may utilize support from anchors to the side, during certain processing steps. By changing the lithographic dimensions of the anchors compared to the NWs, the anchors may be reduced or eliminated during processing. The method covers, among other things, the integration of Gate-All-Around NW (GAA-NW) MOSFETs on a bulk semiconductor. The GAA structure may consist of a silicon core fabricated as specified in the invention, surrounded by any usable gate dielectric, and finally by a gate material, such as polysilicon or metal. The source and drain of the GAA-NW may be connected to the bulk semiconductor to avoid self heating of the device over a wide range of operating conditions. The GAA-NW MOS capacitor can also be used for the integration of a Gate-All-Around optical phase modulator (GAA modulator). The working principle for the optical modulator is modulation of the refractive index by free carrier accumulation or inversion in a MOS capacitive structure, which changes the phase of the propagating light.

A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.

A highly linearized capacitor structure is formed by a first capacitor, that is coupled between a first terminal and a common node, combine with a second capacitor, that is coupled between a second terminal and the common node. When a bias voltage is applied, the capacitance values of the first and second capacitors combine and a capacitance variation of the first capacitor is compensated by a capacitance variation of the second capacitor to reduce and linearize overall capacitance variation in the combined capacitor structure.

A MOS capacitor in a charge pump includes a MOS device with at least one body bias region and a device body of a same conductivity type for providing maximum capacitance over a wide voltage range. The MOS capacitor also includes a gate forming a first terminal of the MOS capacitor, and the at least one body bias region forms a second terminal of the MOS capacitor. The MOS capacitor further includes a multiple-well structure formed with the device body and a deep well in a substrate for enhanced noise immunity.

The retinal prosthesis test device is comprised of a thin wafer of glass made from nanochannel glass (NGC) with very small channels perpendicular to the plane of the wafer filled with an electrical conductor forming microwires. One surface of the glass is ground to a spherical shape consistent with the radius of curvature of the inside of the retina. The NGC is hybridized to a silicon de-multiplexer and a video image is serially input to a narrow, flexible micro-cable and read into a 2-D array of unit cells in a pixel-by-pixel manner which samples the analog video input and stores the value as a charge on a MOS capacitor. After all unit cells have been loaded with the pixel values for the current frame, a biphasic pulse is sent to each unit cell which modulates the pulse in proportion to the pixel value stored therein. Because the biphasic pulses flow in parallel to each unit cell from a global external connection, the adjacent retinal neurons are all stimulated simultaneously, analogous to image photons stimulating photoreceptors in a normal retina. A permanent retinal implant device uses a NGC array hybridized to a silicon chip, the image is simultaneously generated within each cell through a photon-to-electron conversion using a silicon photodiode. The photons propagate directly through into the backside of the device. Electrical power and any control signals are transmitted through an inductively driven coil or antenna on the chip. The device collects the charge in storage capacitors via the photon-to-electron conversion process, stimulates the neural tissue with biphasic pulses in proportion to the stored charges, and resets the storage capacitors to repeat the process.

A technology capable of reducing the fraction defective of a MOS capacitor without the need to perform a screening is provided.

A MOS capacitor MOS1 and a MOS capacitor MOS2 are coupled in series between a high potential and a low potential to form a series capacitive element. Then, a polysilicon capacitor PIP1 and a polysilicon capacitor PIP2 are coupled in parallel with the series capacitive element. Specifically, a high-concentration semiconductor region HS1 constituting a lower electrode of the MOS capacitor MOS1 and a high-concentration semiconductor region HS2 constituting a lower electrode of the MOS capacitor MOS2 are coupled. Further, an electrode E1 constituting an upper electrode of the MOS capacitor MOS1 is coupled to the low potential (for example, GND) and an electrode E3 constituting an upper electrode of the MOS capacitor MOS2 is coupled to the high potential (for example, power source potential).

A charge pump circuit includes MOS capacitors configured to operate in the accumulation region, resulting in a substantially constant capacitance over the operational range. In a particularly preferred embodiment, a char ge pump uses multiple stages of p-channel MOS capacitors. In accordance with a further aspect of the present invention, oxide thicknesses of the p-channel MOS capacitors are optimized in accordance with the requirements of each stage.

A technique for forming a MOS capacitor (100) that can be utilized as a decoupling capacitor is disclosed. The MOS capacitor (100) is formed separately from the particular circuit device (170) that it is to service. As such, the capacitor (100) and its fabrication process can be optimized in terms of efficiency, etc. The capacitor (100) is fabricated with conductive contacts (162) that allow it to be fused to the device (170) via conductive pads (172) of the device (170). As such, the capacitor (100) and device (170) can be packaged together and valuable semiconductor real estate can be conserved as the capacitor (100) is not formed out of the same substrate as the device (170). The capacitor (100) further includes deep contacts (150, 152) whereon bond pads (180, 182) can be formed that allow electrical connection of the capacitor (100) and device (170) to the outside world.

An integrator circuit includes an input conductor for conducting an input current, a first amplifier stage having a first input coupled to the input conductor and a second input coupled to receive a reference voltage and a second amplifier stage having a output and an input coupled to an output of the first amplifier stage. An integrating capacitor is coupled between the first input of the first amplifier stage and the output of the second amplifier stage, and a compensation capacitor comprised of an MOS capacitor is coupled between the input and the output of the second amplifier stage. The integrator circuit is especially adapted for use in a CT scanner data acquisition system.

Capacitors include a first electrical terminal that has fins formed from doped semiconductor on a top layer of doped semiconductor on a semiconductor-on-insulator substrate; a second electrical terminal that has an undoped material having bottom surface shape that is complementary to the first electrical terminal, such that an interface area between the first electrical terminal and the second electrical terminal is larger than a capacitor footprint; and a dielectric layer separating the first and second electrical terminals.

In a low-pass filter, the filter characteristics equivalent to those of a conventional low-pass filter are maintained, the size of a capacitive element is decreased, and the low-pass filter operates stably. Further, a MOS capacitor is used as a capacitive element. For such purposes, in a low-pass filter including a first capacitive element, and a resistive element and a second capacitive element which are connected in series to the first capacitive element, a first electric current is supplied to the first input terminal connected to one end of the first capacitive element, and a second electric current is supplied to the second input terminal connected to the other end of the first capacitive element. Herein, the capacitance value of the first capacitive element is set according to the magnitude of the first electric current. Further, the resistive element is provided with a power supply that is connected in series to the resistive element, and a voltage equal to or higher than the threshold voltage of a MOS transistor is always applied between the second input terminal and the ground.

A novel semiconductor variable capacitor is presented. The semiconductor structure is simple and is based on a semiconductor variable MOS capacitor structure suitable for integrated circuits, which has at least three terminals, one of which is used to modulate the equivalent capacitor area of the MOS structure by increasing or decreasing its DC voltage with respect to another terminal of the device, in order to change the capacitance over a wide ranges of values. Furthermore, the present invention decouples the AC signal and the DC control voltage avoiding distortion and increasing the performance of the device, such as its control characteristic. The present invention is simple and only slightly dependent on the variations due to the fabrication process. It exhibits a high value of capacitance density and, if opportunely implemented, shows a linear dependence of the capacitance value with respect to the voltage of its control terminal.

A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.

The present invention provides a silicon wave-guide (3), with a silicon oxide cladding (2, 4) on a silicon substrate (1). At predetermined positions along the length of the wave-guide, are created metal oxide semiconductor (MOS) structures. A poly-silicon, or any other conductive layer (5), is deposited and patterned above the upper cladding (4) and electrical contacts are made to the substrate (1), the silicon wave-guide (3), and the poly-silicon layer (5). Upon the application of a potential difference between at least two of the layers from the group comprising the substrate (1), the silicon wave-guide (3), and the poly-silicon layer (5), the free carrier concentration at the top and/or bottom layer of the silicon wave-guide (3) is changed by the electric field. The change in the electric field results in a change in the index of refraction, and the change in the index of refraction causes a change in the optical mode propagating in the wave-guide (3). The propagation is controlled by controlling the changes in the electric field, which can be enhanced by localized changes in the optical properties of the wave-guide (3) induced by ion implantation (6) or trapping of photo-carriers.

A method of MOS capacitance invalidation point fixation comprises: a measuring MOS capacitance is formed; a medium layer and a metal layer are deposited on the top of the MOS capacitance and a MOS capacitance measuring structure is obtained; the MOS capacitance measuring structure is measured and invalidation point position information is obtained. The method of depositing the metal layer on the top of the measuring MOS capacitance comprises depositing a first assisting metal layer and a second assisting metal layer or depositing a metal layer, having regular figures, on the top of the measuring MOS capacitance. A reseau formed by double-level metal wire or regular figure in the single-layer metal layer is used as coordinates of the optical detection figure, thus providing exact invalidation point position information. The manufacturing processes of the regular figures in the double-layer metal wire or the single-layer metal layer are simple and do not separately need to add production steps or lead in new materials. The method neither increases the production cost nor has bad influences on the properties of the devices obtained finally.