17 results about "Mos capacitor" patented technology

Various embodiments of solid state transducer (“SST”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light.

An optical device (200, 300) comprising the following: a substrate (201,301); a heterogeneous metal oxide semiconductor MOS capacitor formed on the substrate, wherein the MOS capacitor comprises: an optical fiber (202, 302); a first cathode (204, 304) comprising a first material in which an optical waveguide is formed; an anode (206, 306) formed in the optical waveguide, the anode comprising a second material that differs from the first material; and a dielectric (218, 318) arranged between the first cathode and the anode, wherein the dielectric comprises an oxide of the first material and an oxide of the second material, where the heterogeneous MOS capacitor is defined between the anode and the first cathode; and a semiconductor component layer that is arranged between the substrate and the heterogeneous MOS capacitor and is formed in the optical waveguide, characterized by the fact that The semiconductor component layer and the anode form a resistance element that is integrated into the optical waveguide.

The invention belongs to the field of integrated circuits, and discloses a low-voltage high-precision instrumentation amplifier analog IC (integrated circuit) chip which takes a high-performance reference current source circuit without an operational amplifier as a biasing circuit. In the low-voltage design, in order to solve the problem that the signal-to-noise ratio of the instrument amplifier is gradually deteriorated, a rail-to-rail input and output structure is adopted. According to the invention, the folded cascode structure provides a large gain and also serves as a resistor to be connected with the Miller compensation capacitor to form an unconventional RC network, so that the zero point problem is ingeniously solved, the additional chip area is not increased, and the response speed of the instrument amplifier is also improved; the MOS capacitor is used as the compensation capacitor, compared with a traditional metal capacitor, the MOS capacitor has the advantages of being high in integration level, small in area and the like, and the chip area is greatly reduced while the compensation effect is achieved.

A MOS capacitor type optical modulator includes a silicon-on-insulator (SOI) substrate, a first doped region in a silicon device layer of the SOI substrate, and a second doped region laterally separated from the first doped region by a vertically extending insulator layer to form a lateral MOS capacitor region. The first doped region, the second doped region, and the insulator layer are formed of different materials.

The application provides a voltage type global shutter photosensitive detector based on a composite dielectric gate capacitor and a method. In a unit of the detector, a global shutter structure is arranged between a composite dielectric gate MOS capacitor and a reading transistor, and specifically includes a switch transistor and a switch capacitor. The structure of the switch transistor includes a bottom insulating dielectric layer, a control gate and a source-drain electrode. The source of the switch transistor is connected with the composite dielectric gate MOS capacitor. The drain of the switch transistor is connected with the switch capacitor in series. Charge signals are coupled from the composite dielectric gate MOS capacitor to the switch capacitor, so that the charge signals are converted into voltage signals. The control gate of the reading transistor is connected with the source of the switch transistor. Voltage signals are input from the control gate end of the reading transistor, and are read out by the drain of the reading transistor. The application can realize a global exposure function on the basis of a traditional photosensitive detector, and can effectively solve the analog domain noise caused by dark current at a photosensitive interface.

This invention discloses a silicon carbide MOS device and its fabrication method, belonging to the field of semiconductor power device technology. It solves the problems of complex and demanding gate oxide layer processes, which often involve ultra-high temperature oxidation or high-temperature annealing in different atmospheres. The device comprises a lower surface electrode, a SiC epitaxial wafer, a gate oxide layer, and a polysilicon electrode stacked sequentially. Pentium-valent and / or trivalent elements implanted in the polysilicon electrode diffuse to the gate oxide layer. The method involves oxidizing the SiC epitaxial wafer, using the upper surface oxide layer as the gate oxide layer, and forming a polysilicon layer on the surface of the upper surface oxide layer. Pentium-valent and / or trivalent elements are implanted into the polysilicon layer, followed by activated annealing, allowing the pentavalent and / or trivalent elements to diffuse to the gate oxide layer. A patterning process is then performed on the polysilicon layer to form the polysilicon electrode, resulting in a silicon carbide MOS device (mainly including MOSFET devices and MOS capacitors). This silicon carbide MOS device and method can be used in power electronic devices.

Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source / drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.

The invention discloses a two-stage charge pump circuit, a driving circuit and electronic equipment, and belongs to the technical field of charge pump circuit design, the two-stage charge pump circuit comprises two-stage charge pump units which are in cascade connection, and the first-stage charge pump unit comprises a first-stage clock driving circuit, a first coupling capacitor and a second coupling capacitor which are mutually connected; the second-stage charge pump unit comprises a second-stage clock driving circuit, a third coupling capacitor and a fourth coupling capacitor which are connected with one another; the voltage input end of the second-stage clock driving circuit is connected with the voltage output end of the first-stage clock driving circuit; all the coupling capacitors are MOS capacitors. The two-stage charge pump circuit aims to overcome the defects of a two-stage charge pump circuit in the prior art in the aspects of voltage withstanding of a second-stage capacitor, chip area and manufacturing cost, so that the MOS capacitor can meet the voltage withstanding requirement at the second stage, and reliable operation of the circuit is ensured while the chip area is saved and the power consumption and the manufacturing cost are reduced.

Provided is a method for manufacturing a stack structure. The method for manufacturing a stack structure includes: preparing a substrate; forming a two-dimensional semiconductor material on the substrate; and oxidizing the two-dimensional semiconductor material using oxygen plasma to form a high-k material layer including the high-k material. The stack structure manufactured through the above-described method may be easily applied to a MOS capacitor, a field effect transistor (FET), an impact ionization super-tilt switching device, a dye-sensitized solar cell, an architectural film (particularly, a film used for window coating), and the like.

An optical device (200, 300) comprising the following: a substrate (201,301); a heterogeneous metal oxide semiconductor MOS capacitor formed on the substrate, wherein the MOS capacitor comprises: an optical fiber (202, 302); a first cathode (204, 304) comprising a first material in which an optical waveguide is formed; an anode (206, 306) formed in the optical waveguide, the anode comprising a second material that differs from the first material; and a dielectric (218, 318) arranged between the first cathode and the anode, wherein the dielectric comprises an oxide of the first material and an oxide of the second material, where the heterogeneous MOS capacitor is defined between the anode and the first cathode; and a semiconductor component layer that is arranged between the substrate and the heterogeneous MOS capacitor and is formed in the optical waveguide, characterized by the fact that the optical waveguide (202, 302) comprises a first region and a second region that define a pn junction diode formed in the optical waveguide (202, 302).

The invention provides a limited-time programmable nonvolatile memory and a preparation and operation method thereof, a P-type pocket region and an N-type drain doping region are arranged in a drain region, and the P-type pocket region and the N-type drain doping region are provided with a longitudinal interface below a side wall laminated structure, so that electronic writing is realized when an N-type memory transistor is positively conducted; when the N-type storage transistor is not turned on in the forward direction, hole writing is achieved. Compared with a traditional memory, the limited-time programmable nonvolatile memory has the advantages that charges in the limited-time programmable nonvolatile memory are stored in the silicon nitride layer in the side wall laminated structure, and an additional MOS (Metal Oxide Semiconductor) capacitor is not needed, so that the area of a memory unit can be effectively reduced; meanwhile, the limited-time programmable nonvolatile memory provided by the embodiment of the invention only has the process of writing 0 and 1 to the memory unit, and does not need an erasing action, so that the circuit design is effectively simplified.

An integrated circuit (IC), including: a metal-oxide-semiconductor (MOS) capacitor coupled between a first voltage rail and a node, wherein the MOS capacitor generates a leakage current while in operation, the leakage current flowing between the first voltage rail and the node; and a capacitor leakage-current compensation circuit coupled between the node and a second voltage rail, wherein the capacitor leakage-current compensation circuit is configured to generate a compensation current flowing between the node and the second voltage rail, the compensation current flowing in the same direction as the leakage current between the first voltage rail and the second voltage rail.

An integrated circuit (IC), including: a metal-oxide-semiconductor (MOS) capacitor coupled between a first voltage rail and a node, wherein the MOS capacitor generates a leakage current while in operation, the leakage current flowing between the first voltage rail and the node; and a capacitor leakage-current compensation circuit coupled between the node and a second voltage rail, wherein the capacitor leakage-current compensation circuit is configured to generate a compensation current flowing between the node and the second voltage rail, the compensation current flowing in the same direction as the leakage current between the first voltage rail and the second voltage rail.

The N-path filter includes a plurality of switched-capacitor circuits, respectively controlled by a plurality of logic signals, and connected to a plurality of shunt common nodes. Each switched-capacitor circuit includes a corresponding switch and a corresponding balanced metal-oxide-semiconductor (MOS) capacitor. The corresponding switch is configured to controllably connect a shunt common node to a corresponding intermediate node according to a corresponding logic signal of the logic signals. The corresponding balanced MOS capacitor is connected to the corresponding intermediate node, wherein the corresponding balanced MOS capacitor exhibits a capacitance at the corresponding intermediate node with reference to a power node and a ground node.

The present invention relates to a vertically charge transferring pixel sensor and a manufacturing method therefor. In the vertically charge transferring pixel sensor, deep trench isolation (DTI) structures are used to divide a substrate to form a plurality of substrate pixel units, and the DTI structures pass through the substrate to physically isolate the substrate pixel units from each other, so that optoelectronic crosstalk between pixels corresponding to the substrate pixel units can be avoided, improving the device performance. In addition, a shallow trench isolation structure is used to divide each substrate pixel unit into a photosensitive region, a charge reading region, and a substrate lead-out region. In a pixel formed corresponding to a substrate pixel unit, the substrate pixel unit and a gate structure constitute a MOS capacitor, the substrate pixel unit is a substrate electrode of the MOS capacitor, and the substrate lead-out region is a connection terminal of the substrate pixel unit. The substrate lead-out region may be connected to a corresponding external signal from a front side of the substrate, so that a voltage is applied to the substrate electrode by means of the substrate lead-out region.

Embodiments of the present application relate to the field of semiconductor, and particularly relate to a MOS capacitor layout, a forming method thereof and a verification method. The MOS capacitor layout comprises: a working layer, the working layer comprises an active layer, a gate layer, a source layer located on one side of the gate layer, and a drain layer located on the other side of the gate layer, and the gate layer, the source layer and the drain layer are located directly above the active layer; and a capacitor identification layer, the capacitor identification layer covers at least part of the working layer. The embodiments of the present application are beneficial to improving the efficiency of LVS consistency verification.

An integrated circuit (IC), including: a metal-oxide-semiconductor (MOS) capacitor coupled between a first voltage rail and a node, wherein the MOS capacitor generates a leakage current while in operation, the leakage current flowing between the first voltage rail and the node; and a capacitor leakage-current compensation circuit coupled between the node and a second voltage rail, wherein the capacitor leakage-current compensation circuit is configured to generate a compensation current flowing between the node and the second voltage rail, the compensation current flowing in the same direction as the leakage current between the first voltage rail and the second voltage rail.