64 results about "Mos capacitor" patented technology

According to the MTP device and the preparation method thereof, an MOS capacitor composed of a substrate, a gate oxide layer and a floating gate in a traditional MTP device is replaced with a capacitor located on the substrate and composed of the floating gate, an insulating layer and a conductive plug, so that the potential of the floating gate is controlled through capacitive coupling between the floating gate and the conductive plug; according to the MTP device disclosed by the invention, the capacitor is completely isolated from the substrate, so that the MTP device is not influenced by the potential of the substrate during programming and erasing operation, the operation range of the MTP device is further effectively expanded, namely the programming efficiency and the erasing efficiency of the MTP device are improved, and the reliability of the MTP device is improved. And meanwhile, higher capacitance coupling efficiency is realized in a smaller area, and the reduction of the chip area is facilitated.

Various embodiments of solid state transducer (“SST”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light.

The invention provides a method for reducing the interface state density of a SiC-MOS device and an MOS capacitor. The method comprises the following steps: providing a silicon carbide substrate; forming a silicon dioxide oxide layer on the silicon carbide substrate; pure oxygen annealing is carried out by adopting a rapid annealing process; pure nitrogen annealing is carried out by adopting a rapid annealing process; forming a gate electrode on the silicon dioxide oxide layer; and forming a substrate electrode at the bottom of the silicon carbide substrate to obtain the SiC-MOS capacitor. According to the invention, the two-step annealing process of low-pressure pure oxygen annealing and pure nitrogen annealing is carried out on the silicon dioxide (SiO2) / silicon carbide (SiC) interface, so that the device has relatively low interface state density and relatively high flat-band voltage stability.

A semiconductor device includes: a filter circuit including: a resistor; a MOS capacitor; and a MOM capacitor stacked on at least one of the resistor or the MOS capacitor, wherein the following inequalities are satisfied:Mc≥β−γ / β+γ×Mr Mr≤√{square root over (1 / 2πftαβ)}  [Math. 1]where ft denotes a cutoff frequency of the filter circuit, Mr denotes a resistor area of a resistor-provided region in which the resistor is provided, Mc denotes a MOS capacitor area of a MOS capacitor-provided region in which the MOS capacitor is provided, α denotes a resistivity of the resistor, β denotes a MOS capacitance rate of the MOS capacitor, and γ denotes a MOM capacitance rate of the MOM capacitor.

An optical device (200, 300) comprising the following: a substrate (201,301); a heterogeneous metal oxide semiconductor MOS capacitor formed on the substrate, wherein the MOS capacitor comprises: an optical fiber (202, 302); a first cathode (204, 304) comprising a first material in which an optical waveguide is formed; an anode (206, 306) formed in the optical waveguide, the anode comprising a second material that differs from the first material; and a dielectric (218, 318) arranged between the first cathode and the anode, wherein the dielectric comprises an oxide of the first material and an oxide of the second material, where the heterogeneous MOS capacitor is defined between the anode and the first cathode; and a semiconductor component layer that is arranged between the substrate and the heterogeneous MOS capacitor and is formed in the optical waveguide, characterized by the fact that The semiconductor component layer and the anode form a resistance element that is integrated into the optical waveguide.

A MOS capacitor includes a substrate of a first conductivity type including a fin surrounded by an isolation region. The fin protrudes from a top surface of the isolation region. A counter-doping region of a second conductivity type is disposed in the fin and serves as a first electrode plate of the MOS capacitor. A capacitor dielectric layer covers a sidewall and a top surface of the fin. A metal gate covers the capacitor dielectric layer and serves as a second electrode plate of the MOS capacitor.

The invention discloses a digital control oscillator circuit based on a three-level tuning mechanism and a working method, and relates to the field of electronic engineering and signal processing. The working method of the digital control oscillator circuit comprises the following three steps: 1) a coarse adjustment stage: adopting a switched capacitor bank to realize preliminary adjustment of frequency, realizing large-range adjustment of the frequency, and providing reference frequency for subsequent fine adjustment; 2) second-stage adjustment: introducing an MOS capacitor to carry out finer capacitance fine adjustment, which is more direct than coarse adjustment, can quickly respond to the system, and optimizes the response speed and precision of the frequency; and 3) a fine adjustment stage: two MOS capacitors with controllable size difference are adopted for fine adjustment, the core is that the two MOS capacitors are controlled at the same time to realize complementation, and capacitance change can be generated by utilizing fine parasitic capacitance difference between the two MOS capacitors. Through the above three-stage adjustment mechanism, the digitally controlled oscillator can maintain low phase noise, realize seamless transition from coarse adjustment to fine adjustment, and accurately control frequency output.

Provided is a method for manufacturing a stack structure. The method for manufacturing a stack structure includes: preparing a substrate; forming a two-dimensional semiconductor material on the substrate; and oxidizing the two-dimensional semiconductor material using oxygen plasma to form a high-k material layer including the high-k material. The stack structure manufactured through the above-described method may be easily applied to a MOS capacitor, a field effect transistor (FET), an impact ionization super-tilt switching device, a dye-sensitized solar cell, an architectural film (particularly, a film used for window coating), and the like.

The present invention provides a DA conversion device and the like that use the range of low voltage dependency of a MOS capacitor to make it possible to reduce nonlinearity of an output voltage. A charge scaling type DA conversion device comprising a high-order bit side capacitor array and a low-order bit side capacitor array that are connected via an attenuation capacitor comprises a control circuit that applies a voltage, to a plurality of capacitors of the high-order bit side capacitor array and a plurality of capacitors of the low-order bit side capacitor array, so that all of the capacitors have a positive bias voltage or a negative bias voltage at the times of reset and conversion of the DA conversion device, wherein at least one of a reference voltage of the low-order bit side capacitor array and a reset voltage is set to a value different from a reference voltage of the high-order bit side capacitor array.

A metal oxide semiconductor (MOS) capacitor may include: a substrate including a semiconductor material; an oxide layer formed over the first surface of the substrate; a resistive layer formed over at least a portion of the oxide layer; and a conductive layer formed on at least a portion of the resistive layer. Accordingly, the MOS capacitor may include a resistor and a capacitor formed in series with each other.

The invention belongs to the field of integrated circuits, and discloses a low-voltage high-precision instrumentation amplifier analog IC (integrated circuit) chip which takes a high-performance reference current source circuit without an operational amplifier as a biasing circuit. In the low-voltage design, in order to solve the problem that the signal-to-noise ratio of the instrument amplifier is gradually deteriorated, a rail-to-rail input and output structure is adopted. According to the invention, the folded cascode structure provides a large gain and also serves as a resistor to be connected with the Miller compensation capacitor to form an unconventional RC network, so that the zero point problem is ingeniously solved, the additional chip area is not increased, and the response speed of the instrument amplifier is also improved; the MOS capacitor is used as the compensation capacitor, compared with a traditional metal capacitor, the MOS capacitor has the advantages of being high in integration level, small in area and the like, and the chip area is greatly reduced while the compensation effect is achieved.

The invention discloses an anti-radiation integrated device based on a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process platform, an anti-radiation structure and a preparation method. The device comprises a low-voltage MOS (Metal Oxide Semiconductor) device, a low-voltage BJT (Bipolar Junction Transistor) device, a resistor and an MOS capacitor which are integrated on a substrate of one type, high-dielectric-constant dielectric regions are arranged in interlayer dielectric layers of the low-voltage MOS device, the low-voltage BJT device, the resistor and the MOS capacitor respectively, and the high-dielectric-constant dielectric regions and the interlayer dielectric layers below the high-dielectric-constant dielectric regions form a stacked structure. And a metal copper buried layer is arranged on the upper surface of each high-dielectric-constant medium region, and the high-dielectric-constant medium regions and the metal copper buried layers form a laminated structure. The preparation method comprises the following steps: growing an epitaxial layer on a substrate, forming a well region through ion implantation, forming a buried oxide layer through high-energy oxygen ion implantation, forming a doped region through ion implantation, growing a gate oxide medium through wet oxidation after high-temperature annealing, sequentially depositing a high-dielectric-constant material, a copper buried layer and aluminum, and respectively etching. And depositing an oxide to form an interlayer medium, etching a through hole, finally depositing aluminum, and etching to form a metal electrode.

The invention belongs to the technical field of integrated circuits, and particularly relates to a simple current mode relaxation oscillator. According to the invention, the input comparator generates a pair of different high and low flip thresholds, the MOS capacitor is charged through the IPTAT source current, when the voltage reaches the upper flip threshold, the IPTAT sink current discharges the capacitor, and when the voltage reaches the lower flip threshold, the voltage returns to the stage of charging the capacitor through the IPTAT source current. A triangular wave is output through periodic charging and discharging of an IPTAT current to a capacitor, and finally a standard rectangular wave is obtained by adding two stages of buffers behind to shape the waveform. The circuit has the advantages that compared with a traditional current mode relaxation oscillator, two comparators and a high-low threshold generation circuit used for comparator input are omitted, in addition, the capacitor is an MOS capacitor, and the complexity and the area of the circuit are greatly reduced.

The embodiment of the invention relates to a universal gate protection diode. An embodiment metal oxide semiconductor (MOS) device includes: a MOS capacitor having a well and a gate, the MOS capacitor disposed in a semiconductor substrate of a first doping type; and a gate protection diode disposed in the semiconductor substrate. The gate protection diode includes a first region doped with a first doping type and coupled to a gate of the MOS capacitor. The gate protection diode includes a second region different from the well of the MOS capacitor and doped with a second doping type different from the first doping type.

A unit pixel includes a first photoelectric converter, a first transfer transistor disposed between to the first photoelectric converter and a first node, a connection transistor disposed between and connected to a second node and the first node, a second transfer transistor disposed between and connected to a third node and the second node, a second photoelectric converter connected to the third node, and a storage metal-oxide semiconductor (MOS) capacitor connected to the third node. The storage MOS capacitor stores charges from the second photoelectric converter. For a first time period, first charges accumulated in the first photoelectric converter are transferred to the first node, for a second time period, second charges accumulated in the first photoelectric converter are transferred to the first node and the second node, and for a third time period, third charges accumulated in the second photoelectric converter are transferred to the first to third nodes.

A circuit and method for establishing a balanced negative voltage to a near-end and far-end of a bitline having a plurality of memory cells connected to the bitline is disclosed. A MOS capacitor and a metal capacitor are connected in parallel. The MOS capacitor is connected to the near-end of the bitline through a first switch transistor. The metal capacitor is connected to the near-end of the bitline through the first switch transistor and the far end of the bitline through a second switch transistor. A falling negative boost voltage is applied to the MOS capacitor and the metal capacitor. When the switch transistors are turned on during a write operation, the MOS capacitor and the metal capacitor are both coupled to the voltage at the near-end and far-end and drive the voltage to approximately equal the boost voltage, thereby providing a balanced voltage to the bitline.

A MOS capacitor type optical modulator includes a silicon-on-insulator (SOI) substrate, a first doped region in a silicon device layer of the SOI substrate, and a second doped region laterally separated from the first doped region by a vertically extending insulator layer to form a lateral MOS capacitor region. The first doped region, the second doped region, and the insulator layer are formed of different materials.

The invention provides a three-dimensional capacitor structure of a high-voltage charge pump and a preparation method thereof, and the structure comprises an MOS capacitor which comprises a substrate, a first capacitor medium, and a polysilicon electrode; the three-dimensional vertical natural capacitor comprises at least two capacitor layers which are vertically stacked, each capacitor layer comprises a plurality of first metal electrode plates and second metal electrode plates which are arranged at intervals, and a second capacitor medium is arranged between every two adjacent first metal electrode plates and second metal electrode plates; an insulating layer is arranged between two adjacent capacitor layers, a conductive hole is formed in the insulating layer, and the first metal electrode plate and the second metal electrode plate in the two adjacent capacitor layers are connected with each other through the conductive hole; the first metal electrode plate is connected with a substrate of the MOS capacitor, and the second metal electrode plate is connected with a polycrystalline silicon electrode of the MOS capacitor. Through circuit layout and an innovative capacitor structure, the performance of the charge pump can be maintained, and meanwhile, the occupied chip area of the charge pump can be greatly reduced.

The embodiment of the invention relates to a semiconductor device. The semiconductor device comprises a substrate; at least one lower interconnection layer disposed on the substrate; a first upper interconnection layer on the at least one lower interconnection layer; the second upper interconnection layer is located on the first upper interconnection layer; an external connection pad included in the second upper interconnect layer; and a metal oxide semiconductor (MOS) capacitor disposed on the substrate and vertically overlapping the external connection pad, in which the at least one lower interconnect layer includes: a main decoupling capacitor region vertically overlapping the MOS capacitor; and an additional decoupling capacitor region surrounding the main decoupling capacitor region.

The application provides a voltage type global shutter photosensitive detector based on a composite dielectric gate capacitor and a method. In a unit of the detector, a global shutter structure is arranged between a composite dielectric gate MOS capacitor and a reading transistor, and specifically includes a switch transistor and a switch capacitor. The structure of the switch transistor includes a bottom insulating dielectric layer, a control gate and a source-drain electrode. The source of the switch transistor is connected with the composite dielectric gate MOS capacitor. The drain of the switch transistor is connected with the switch capacitor in series. Charge signals are coupled from the composite dielectric gate MOS capacitor to the switch capacitor, so that the charge signals are converted into voltage signals. The control gate of the reading transistor is connected with the source of the switch transistor. Voltage signals are input from the control gate end of the reading transistor, and are read out by the drain of the reading transistor. The application can realize a global exposure function on the basis of a traditional photosensitive detector, and can effectively solve the analog domain noise caused by dark current at a photosensitive interface.

The present invention is provided with a filter circuit (104) having resistors (201a, 201b), MOS capacitors (202a, 202b), and an MOM capacitor (203) laminated on the resistors (201a, 201b) or / and the MOS capacitors (202a, 202b). Given the cutoff frequency of a filter circuit (104) is ft, the resistance area of a resistance formation region (600) in which resistors (201a, 201b) are formed is Mr, the MOS capacitance area of an MOS capacitance formation region (500) in which MOS capacitors (202a, 202b) are formed is Mc, the resistivity of the resistors (201a, 201b) is alpha, the MOS permittivity of the MOS capacitors (202a, 202b) is beta, and the MOM permittivity of the MOM capacitor (203) is gamma, # imgabs0 # is satisfied.

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

This invention discloses a silicon carbide MOS device and its fabrication method, belonging to the field of semiconductor power device technology. It solves the problems of complex and demanding gate oxide layer processes, which often involve ultra-high temperature oxidation or high-temperature annealing in different atmospheres. The device comprises a lower surface electrode, a SiC epitaxial wafer, a gate oxide layer, and a polysilicon electrode stacked sequentially. Pentium-valent and / or trivalent elements implanted in the polysilicon electrode diffuse to the gate oxide layer. The method involves oxidizing the SiC epitaxial wafer, using the upper surface oxide layer as the gate oxide layer, and forming a polysilicon layer on the surface of the upper surface oxide layer. Pentium-valent and / or trivalent elements are implanted into the polysilicon layer, followed by activated annealing, allowing the pentavalent and / or trivalent elements to diffuse to the gate oxide layer. A patterning process is then performed on the polysilicon layer to form the polysilicon electrode, resulting in a silicon carbide MOS device (mainly including MOSFET devices and MOS capacitors). This silicon carbide MOS device and method can be used in power electronic devices.

Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source / drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.

The utility model provides a current mirror layout structure. Grid electrodes of PM14, PM15, PM16, PM17, PM21 and PM22 are connected and then connected with an ENP port net1, a grid electrode of PM20 is connected with a drain electrode of PM16 and then connected with an ENP port net2, and a grid electrode of PM19 is connected with a drain electrode of PM15 and then connected with an ENP port net3. The grid electrode of the PM18 is connected with the ENP port, and the drain electrode of the PM18 is connected with the grid electrodes of the PM14, the PM15, the PM16, the PM17, the PM21 and the PM22; and PM18 is an enabling tube. According to the utility model, the enabling tube PM18 and the PM22 serving as the capacitor are placed independently, so that the matching performance of the current mirror main body is prevented from being damaged; pM20 and PM16 are regarded as a unit A, PM19 and PM15 are regarded as another unit B, and the unit A and the unit B are symmetrically placed; pM22, PM21, PM17 and PM14 are horizontally placed so as to ensure that the transistor orientations of the PM22, PM21, PM17 and PM14 are consistent with those of the unit A and the unit B, and the influence of the change of carrier mobility caused by stress and inclination of the transistor is avoided; a current mirror layout is surrounded by a substrate ring, an MOS capacitor PM22 is placed on the outermost side, and a substrate of an enabling tube PM18 and a substrate of a current mirror are partially overlapped.

The invention discloses an anti-radiation reinforcing structure and method for a composite dielectric gate photosensitive detector. According to the specific structure of the detector, a basic unit of a detector array comprises a composite dielectric gate MOS capacitor and a composite dielectric gate MOSFET which are formed above the same semiconductor substrate, and a gate of the composite dielectric gate MOSFET is of a closed gate structure and used for separating a source electrode and a drain electrode of the composite dielectric gate MOSFET; the drain electrode is arranged inside the closed gate structure, and the source electrode is arranged outside the closed gate structure. According to the detector reinforcing structure provided by the invention, the influence of irradiation ionization transient large current, leakage current, dark current and crosstalk on the performance of the detector can be remarkably reduced, and the anti-irradiation capability of a device is remarkably improved.

The invention discloses a two-stage charge pump circuit, a driving circuit and electronic equipment, and belongs to the technical field of charge pump circuit design, the two-stage charge pump circuit comprises two-stage charge pump units which are in cascade connection, and the first-stage charge pump unit comprises a first-stage clock driving circuit, a first coupling capacitor and a second coupling capacitor which are mutually connected; the second-stage charge pump unit comprises a second-stage clock driving circuit, a third coupling capacitor and a fourth coupling capacitor which are connected with one another; the voltage input end of the second-stage clock driving circuit is connected with the voltage output end of the first-stage clock driving circuit; all the coupling capacitors are MOS capacitors. The two-stage charge pump circuit aims to overcome the defects of a two-stage charge pump circuit in the prior art in the aspects of voltage withstanding of a second-stage capacitor, chip area and manufacturing cost, so that the MOS capacitor can meet the voltage withstanding requirement at the second stage, and reliable operation of the circuit is ensured while the chip area is saved and the power consumption and the manufacturing cost are reduced.

The invention provides a power supply clamping circuit and a chip, and the power supply clamping circuit introduces a gain amplifier on the basis of an existing power supply clamping circuit, so that when an electrostatic discharge (ESD) event arrives, the gain amplifier can amplify the capacitance value of an MOS capacitor which is bridged between the input end and the output end of the gain amplifier based on the Miller effect, and the power supply clamping circuit has the advantages that the power supply clamping circuit is simple in structure and low in cost. The opening time of the discharge pipe is ensured to be sufficient, so that the electrostatic discharge event is completely discharged. Besides, when no electrostatic discharge event exists, the gain amplifier does not work so as to avoid affecting normal work of the chip, and at the moment, the MOS capacitor can be kept at the original small capacitance value so as to ensure low leakage current. The chip is provided with the power supply clamping circuit, so that ESD events can be reliably coped with, and the safety of the chip is ensured.

Provided is a method for manufacturing a stack structure. The method for manufacturing a stack structure includes: preparing a substrate; forming a two-dimensional semiconductor material on the substrate; and oxidizing the two-dimensional semiconductor material using oxygen plasma to form a high-k material layer including the high-k material. The stack structure manufactured through the above-described method may be easily applied to a MOS capacitor, a field effect transistor (FET), an impact ionization super-tilt switching device, a dye-sensitized solar cell, an architectural film (particularly, a film used for window coating), and the like.

An optical device (200, 300) comprising the following: a substrate (201,301); a heterogeneous metal oxide semiconductor MOS capacitor formed on the substrate, wherein the MOS capacitor comprises: an optical fiber (202, 302); a first cathode (204, 304) comprising a first material in which an optical waveguide is formed; an anode (206, 306) formed in the optical waveguide, the anode comprising a second material that differs from the first material; and a dielectric (218, 318) arranged between the first cathode and the anode, wherein the dielectric comprises an oxide of the first material and an oxide of the second material, where the heterogeneous MOS capacitor is defined between the anode and the first cathode; and a semiconductor component layer that is arranged between the substrate and the heterogeneous MOS capacitor and is formed in the optical waveguide, characterized by the fact that the optical waveguide (202, 302) comprises a first region and a second region that define a pn junction diode formed in the optical waveguide (202, 302).