33 results about "Mos capacitor" patented technology

Various embodiments of solid state transducer (“SST”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light.

A semiconductor device includes: a filter circuit including: a resistor; a MOS capacitor; and a MOM capacitor stacked on at least one of the resistor or the MOS capacitor, wherein the following inequalities are satisfied:Mc≥β−γ / β+γ×Mr Mr≤√{square root over (1 / 2πftαβ)}  [Math. 1]where ft denotes a cutoff frequency of the filter circuit, Mr denotes a resistor area of a resistor-provided region in which the resistor is provided, Mc denotes a MOS capacitor area of a MOS capacitor-provided region in which the MOS capacitor is provided, α denotes a resistivity of the resistor, β denotes a MOS capacitance rate of the MOS capacitor, and γ denotes a MOM capacitance rate of the MOM capacitor.

An optical device (200, 300) comprising the following: a substrate (201,301); a heterogeneous metal oxide semiconductor MOS capacitor formed on the substrate, wherein the MOS capacitor comprises: an optical fiber (202, 302); a first cathode (204, 304) comprising a first material in which an optical waveguide is formed; an anode (206, 306) formed in the optical waveguide, the anode comprising a second material that differs from the first material; and a dielectric (218, 318) arranged between the first cathode and the anode, wherein the dielectric comprises an oxide of the first material and an oxide of the second material, where the heterogeneous MOS capacitor is defined between the anode and the first cathode; and a semiconductor component layer that is arranged between the substrate and the heterogeneous MOS capacitor and is formed in the optical waveguide, characterized by the fact that The semiconductor component layer and the anode form a resistance element that is integrated into the optical waveguide.

The present invention provides a DA conversion device and the like that use the range of low voltage dependency of a MOS capacitor to make it possible to reduce nonlinearity of an output voltage. A charge scaling type DA conversion device comprising a high-order bit side capacitor array and a low-order bit side capacitor array that are connected via an attenuation capacitor comprises a control circuit that applies a voltage, to a plurality of capacitors of the high-order bit side capacitor array and a plurality of capacitors of the low-order bit side capacitor array, so that all of the capacitors have a positive bias voltage or a negative bias voltage at the times of reset and conversion of the DA conversion device, wherein at least one of a reference voltage of the low-order bit side capacitor array and a reset voltage is set to a value different from a reference voltage of the high-order bit side capacitor array.

The invention belongs to the field of integrated circuits, and discloses a low-voltage high-precision instrumentation amplifier analog IC (integrated circuit) chip which takes a high-performance reference current source circuit without an operational amplifier as a biasing circuit. In the low-voltage design, in order to solve the problem that the signal-to-noise ratio of the instrument amplifier is gradually deteriorated, a rail-to-rail input and output structure is adopted. According to the invention, the folded cascode structure provides a large gain and also serves as a resistor to be connected with the Miller compensation capacitor to form an unconventional RC network, so that the zero point problem is ingeniously solved, the additional chip area is not increased, and the response speed of the instrument amplifier is also improved; the MOS capacitor is used as the compensation capacitor, compared with a traditional metal capacitor, the MOS capacitor has the advantages of being high in integration level, small in area and the like, and the chip area is greatly reduced while the compensation effect is achieved.

The embodiment of the invention relates to a universal gate protection diode. An embodiment metal oxide semiconductor (MOS) device includes: a MOS capacitor having a well and a gate, the MOS capacitor disposed in a semiconductor substrate of a first doping type; and a gate protection diode disposed in the semiconductor substrate. The gate protection diode includes a first region doped with a first doping type and coupled to a gate of the MOS capacitor. The gate protection diode includes a second region different from the well of the MOS capacitor and doped with a second doping type different from the first doping type.

A MOS capacitor type optical modulator includes a silicon-on-insulator (SOI) substrate, a first doped region in a silicon device layer of the SOI substrate, and a second doped region laterally separated from the first doped region by a vertically extending insulator layer to form a lateral MOS capacitor region. The first doped region, the second doped region, and the insulator layer are formed of different materials.

The embodiment of the invention relates to a semiconductor device. The semiconductor device comprises a substrate; at least one lower interconnection layer disposed on the substrate; a first upper interconnection layer on the at least one lower interconnection layer; the second upper interconnection layer is located on the first upper interconnection layer; an external connection pad included in the second upper interconnect layer; and a metal oxide semiconductor (MOS) capacitor disposed on the substrate and vertically overlapping the external connection pad, in which the at least one lower interconnect layer includes: a main decoupling capacitor region vertically overlapping the MOS capacitor; and an additional decoupling capacitor region surrounding the main decoupling capacitor region.

The application provides a voltage type global shutter photosensitive detector based on a composite dielectric gate capacitor and a method. In a unit of the detector, a global shutter structure is arranged between a composite dielectric gate MOS capacitor and a reading transistor, and specifically includes a switch transistor and a switch capacitor. The structure of the switch transistor includes a bottom insulating dielectric layer, a control gate and a source-drain electrode. The source of the switch transistor is connected with the composite dielectric gate MOS capacitor. The drain of the switch transistor is connected with the switch capacitor in series. Charge signals are coupled from the composite dielectric gate MOS capacitor to the switch capacitor, so that the charge signals are converted into voltage signals. The control gate of the reading transistor is connected with the source of the switch transistor. Voltage signals are input from the control gate end of the reading transistor, and are read out by the drain of the reading transistor. The application can realize a global exposure function on the basis of a traditional photosensitive detector, and can effectively solve the analog domain noise caused by dark current at a photosensitive interface.

This invention discloses a silicon carbide MOS device and its fabrication method, belonging to the field of semiconductor power device technology. It solves the problems of complex and demanding gate oxide layer processes, which often involve ultra-high temperature oxidation or high-temperature annealing in different atmospheres. The device comprises a lower surface electrode, a SiC epitaxial wafer, a gate oxide layer, and a polysilicon electrode stacked sequentially. Pentium-valent and / or trivalent elements implanted in the polysilicon electrode diffuse to the gate oxide layer. The method involves oxidizing the SiC epitaxial wafer, using the upper surface oxide layer as the gate oxide layer, and forming a polysilicon layer on the surface of the upper surface oxide layer. Pentium-valent and / or trivalent elements are implanted into the polysilicon layer, followed by activated annealing, allowing the pentavalent and / or trivalent elements to diffuse to the gate oxide layer. A patterning process is then performed on the polysilicon layer to form the polysilicon electrode, resulting in a silicon carbide MOS device (mainly including MOSFET devices and MOS capacitors). This silicon carbide MOS device and method can be used in power electronic devices.

Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source / drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.

The invention discloses a two-stage charge pump circuit, a driving circuit and electronic equipment, and belongs to the technical field of charge pump circuit design, the two-stage charge pump circuit comprises two-stage charge pump units which are in cascade connection, and the first-stage charge pump unit comprises a first-stage clock driving circuit, a first coupling capacitor and a second coupling capacitor which are mutually connected; the second-stage charge pump unit comprises a second-stage clock driving circuit, a third coupling capacitor and a fourth coupling capacitor which are connected with one another; the voltage input end of the second-stage clock driving circuit is connected with the voltage output end of the first-stage clock driving circuit; all the coupling capacitors are MOS capacitors. The two-stage charge pump circuit aims to overcome the defects of a two-stage charge pump circuit in the prior art in the aspects of voltage withstanding of a second-stage capacitor, chip area and manufacturing cost, so that the MOS capacitor can meet the voltage withstanding requirement at the second stage, and reliable operation of the circuit is ensured while the chip area is saved and the power consumption and the manufacturing cost are reduced.

The invention provides a power supply clamping circuit and a chip, and the power supply clamping circuit introduces a gain amplifier on the basis of an existing power supply clamping circuit, so that when an electrostatic discharge (ESD) event arrives, the gain amplifier can amplify the capacitance value of an MOS capacitor which is bridged between the input end and the output end of the gain amplifier based on the Miller effect, and the power supply clamping circuit has the advantages that the power supply clamping circuit is simple in structure and low in cost. The opening time of the discharge pipe is ensured to be sufficient, so that the electrostatic discharge event is completely discharged. Besides, when no electrostatic discharge event exists, the gain amplifier does not work so as to avoid affecting normal work of the chip, and at the moment, the MOS capacitor can be kept at the original small capacitance value so as to ensure low leakage current. The chip is provided with the power supply clamping circuit, so that ESD events can be reliably coped with, and the safety of the chip is ensured.

Provided is a method for manufacturing a stack structure. The method for manufacturing a stack structure includes: preparing a substrate; forming a two-dimensional semiconductor material on the substrate; and oxidizing the two-dimensional semiconductor material using oxygen plasma to form a high-k material layer including the high-k material. The stack structure manufactured through the above-described method may be easily applied to a MOS capacitor, a field effect transistor (FET), an impact ionization super-tilt switching device, a dye-sensitized solar cell, an architectural film (particularly, a film used for window coating), and the like.

An optical device (200, 300) comprising the following: a substrate (201,301); a heterogeneous metal oxide semiconductor MOS capacitor formed on the substrate, wherein the MOS capacitor comprises: an optical fiber (202, 302); a first cathode (204, 304) comprising a first material in which an optical waveguide is formed; an anode (206, 306) formed in the optical waveguide, the anode comprising a second material that differs from the first material; and a dielectric (218, 318) arranged between the first cathode and the anode, wherein the dielectric comprises an oxide of the first material and an oxide of the second material, where the heterogeneous MOS capacitor is defined between the anode and the first cathode; and a semiconductor component layer that is arranged between the substrate and the heterogeneous MOS capacitor and is formed in the optical waveguide, characterized by the fact that the optical waveguide (202, 302) comprises a first region and a second region that define a pn junction diode formed in the optical waveguide (202, 302).

The invention provides a capacitor structure and a preparation method thereof, and the preparation method comprises the steps: forming an insulating dielectric layer on a well region on the surfaces of the side wall and the bottom wall of a trench, then filling the trench with a trench polysilicon layer, forming a gate oxide layer on the trench polysilicon layer, and then forming a gate polysilicon layer on the gate oxide layer, and finally, through the first to third conductive plugs and the first to second patterned metal layers, a second capacitor is connected in parallel to the trench capacitor (first capacitor) to obtain a parallel capacitor structure, so that the capacitor density is greatly increased under the condition that the surface area of the capacitor structure is not increased; the problem that the density of an MIM capacitor and a planar MOS capacitor compatible with a COMS device at present does not meet the high-density requirement of a decoupling capacitor in an integrated circuit is solved.

The invention provides a limited-time programmable nonvolatile memory and a preparation and operation method thereof, a P-type pocket region and an N-type drain doping region are arranged in a drain region, and the P-type pocket region and the N-type drain doping region are provided with a longitudinal interface below a side wall laminated structure, so that electronic writing is realized when an N-type memory transistor is positively conducted; when the N-type storage transistor is not turned on in the forward direction, hole writing is achieved. Compared with a traditional memory, the limited-time programmable nonvolatile memory has the advantages that charges in the limited-time programmable nonvolatile memory are stored in the silicon nitride layer in the side wall laminated structure, and an additional MOS (Metal Oxide Semiconductor) capacitor is not needed, so that the area of a memory unit can be effectively reduced; meanwhile, the limited-time programmable nonvolatile memory provided by the embodiment of the invention only has the process of writing 0 and 1 to the memory unit, and does not need an erasing action, so that the circuit design is effectively simplified.

Embodiments of the present disclosure are related to a semiconductor device including a substrate; at least one lower interconnection layer disposed on a substrate; a first upper interconnection layer on the at least one lower interconnection layer; a second upper interconnection layer on the first upper interconnection layer; an external connection pad, the second upper interconnection layer including the external connection pad; and a metal oxide semiconductor (MOS) capacitor disposed on said substrate vertically overlapping with the external connection pad, wherein the at least one lower interconnection layer including a main decoupling capacitor region vertically overlapping with the MOS capacitor; and additional decoupling capacitor region surrounding the main decoupling capacitor region.

An integrated circuit (IC), including: a metal-oxide-semiconductor (MOS) capacitor coupled between a first voltage rail and a node, wherein the MOS capacitor generates a leakage current while in operation, the leakage current flowing between the first voltage rail and the node; and a capacitor leakage-current compensation circuit coupled between the node and a second voltage rail, wherein the capacitor leakage-current compensation circuit is configured to generate a compensation current flowing between the node and the second voltage rail, the compensation current flowing in the same direction as the leakage current between the first voltage rail and the second voltage rail.

The present invention discloses a histogram peak detection circuit for a laser ranging system, comprising a selection circuit, a histogram circuit, a data screening circuit, and a peak readout circuit. The present invention is suitable for use in scenarios where the ambient light noise level is high. By using a reference voltage V ref Adjustment of the discharge current can cope with varying ambient light noise intensities. This invention uses MOS capacitor discharge to segment the TDC output and generate a histogram. The reuse of the histogram circuit significantly reduces the number of histogram cells, effectively reducing the layout area and improving circuit integration. Furthermore, the detection output of the histogram peak not only improves the reliability and accuracy of the detection results, but also saves large-scale storage components, further enhancing the feasibility of on-chip integration of the histogram algorithm.

An integrated circuit (IC) structure, including a semiconductor-on-insulator (SOI) substrate, the SOI substrate including a buried insulator layer over a base semiconductor layer, and a semiconductor-on-insulator (SOI) layer over the buried insulator layer. The IC structure further includes a gate over a gate dielectric layer over the SOI layer. The IC structure includes an n-type metal-oxide semiconductor (n-MOS) capacitor. The n-MOS capacitor includes an n-well under the buried insulator layer, and an n-type semiconductor adjacent a first side of the gate. The IC structure also includes a p-type metal-oxide semiconductor (p-MOS) capacitor adjacent the n-MOS capacitor and includes a p-well adjacent the n-well and a p-type semiconductor adjacent a second side of the gate. The gate is electrically connected only to the n-MOS capacitor and the p-MOS capacitor.

An integrated circuit (IC), including: a metal-oxide-semiconductor (MOS) capacitor coupled between a first voltage rail and a node, wherein the MOS capacitor generates a leakage current while in operation, the leakage current flowing between the first voltage rail and the node; and a capacitor leakage-current compensation circuit coupled between the node and a second voltage rail, wherein the capacitor leakage-current compensation circuit is configured to generate a compensation current flowing between the node and the second voltage rail, the compensation current flowing in the same direction as the leakage current between the first voltage rail and the second voltage rail.

The invention provides an adjustment circuit, a circuit device and an oscillator, which can realize small area and low noise of the circuit. A regulation circuit (30) includes: an N-type output transistor provided between a first power supply node and an output node of a regulation voltage (VREG); an operational amplifier (OP) having a first input terminal to which the reference voltage is input and a second input terminal to which a feedback voltage (VFB) based on the regulated voltage (VREG) is input; and a low-pass filter circuit (40) that outputs, to the gate of the output transistor (TRQ), a drive voltage (VD) obtained by filtering the output voltage of the operational amplifier (OP). The low-pass filter circuit (40) includes a MOS capacitor that is provided between the gate of the output transistor (TRQ) and the second power supply node, and is configured from a transistor having a withstand voltage lower than that of the output transistor (TRQ).

To provide a regulator circuit and the like that can achieve both a smaller circuit area and a lower noise level.SOLUTION: A regulator circuit 30 includes: an N-type output transistor provided between a first power supply node and an output node of a regulated voltage VREG; an operational amplifier OP in which a reference voltage is input to a first input terminal and a feedback voltage VFB, based on the regulated voltage VREG, is input to a second input terminal; and a low-pass filter circuit 40 that outputs a filtered drive voltage VD obtained by filtering the output voltage of the operational amplifier OP to a gate of the output transistor TRQ. The low-pass filter circuit 40 includes a MOS capacitor which is located between the gate of the output transistor TRQ and a second power supply node, and is configured using a transistor with a lower withstanding voltage than the output transistor TRQ.SELECTED DRAWING: Figure 1

A physically unclonable device according to an embodiment of the present disclosure comprises: a plurality of inverters disposed on a first path to which a first signal is input; a plurality of inverters disposed on a second path to which a second signal is input; a first MOS capacitor disposed on the first path; and a second MOS capacitor disposed on the second path, wherein a first voltage is applied to a MOS capacitor located on the path corresponding to whichever of the first signal or the second signal arrives later at an output terminal of the first path or an outer terminal of the second path. Accordingly, a physically unclonable device that does not require separate error correction can be achieved.

The N-path filter includes a plurality of switched-capacitor circuits, respectively controlled by a plurality of logic signals, and connected to a plurality of shunt common nodes. Each switched-capacitor circuit includes a corresponding switch and a corresponding balanced metal-oxide-semiconductor (MOS) capacitor. The corresponding switch is configured to controllably connect a shunt common node to a corresponding intermediate node according to a corresponding logic signal of the logic signals. The corresponding balanced MOS capacitor is connected to the corresponding intermediate node, wherein the corresponding balanced MOS capacitor exhibits a capacitance at the corresponding intermediate node with reference to a power node and a ground node.

The invention belongs to the technical field of clock signal synchronization, and particularly relates to an adjustable delay circuit, which comprises a current starvation driving module used for outputting a driving signal with preset current magnitude according to an input signal of the adjustable delay circuit; the current enhancement driving module is used for enhancing the current of the driving signal; the RC adjusting module is used for adjusting an RC time constant of the adjustable delay circuit, so that the driving signal is output after being delayed for preset time; the RC adjusting module comprises an adjustable resistor; the adjustable capacitor comprises at least one long delay capacitor and a plurality of MOS (Metal Oxide Semiconductor) capacitors, and the long delay capacitor and each MOS capacitor are respectively provided with a corresponding transmission gate, so that the long delay capacitor and each MOS capacitor are connected to the adjustable delay circuit or disconnected from the adjustable delay circuit; and the capacitance value of the long delay capacitor is at least greater than the capacitance value of any MOS capacitor. According to the adjustable delay circuit provided by the invention, the high-precision and wide-range delay adjustment requirements can be met by adjusting the resistance, the capacitance and the driving capability.

An embodiment metal oxide semiconductor (MOS) device includes an MOS capacitor having a well and a gate disposed a semiconductor substrate of a first doping type; and a gate protection diode disposed the semiconductor substrate. The gate protection diode includes a first region doped with the first doping type and coupled to the gate of the MOS capacitor. The gate protection diode includes a second region distinct from the well of the MOS capacitor and doped with a second doping type different from the first doping type.

The invention discloses a radiation dosimeter based on a vertical charge transfer imaging device and a method thereof. The radiation dosimeter comprises a radiation detection unit, the radiation detection unit is composed of two composite dielectric gate detectors, each composite dielectric gate detector comprises a composite dielectric gate MOS capacitor part and a composite dielectric gate MOSFET part, and the composite dielectric gate MOS capacitor part and the composite dielectric gate MOSFET part are each provided with a main control gate; source electrodes of the MOSFET parts of the two composite dielectric gate detectors are connected together, and drain electrodes of the MOSFET parts of the two composite dielectric gate detectors are led out independently. And the MOS capacitor part of each composite dielectric gate detector is additionally provided with a secondary control gate for electric programming and electric erasing. The radiation dosimeter provided by the invention can realize real-time, high-precision and self-calibration radiation dose detection.

A metal-oxide-semiconductor (MOS) capacitor can include a substrate including a semiconductor material, an oxide layer formed on a first surface of the substrate, a resistive layer formed on at least a portion of the oxide layer, and a conductive layer formed on at least a portion of the resistive layer. Thus, the MOS capacitor can include a resistor and a capacitor formed in series with each other.