5 results about "Voltage dependence" patented technology

The present disclosure relates to a molecular memory device comprising a molecular memory unit that includes a first conducting layer, a second conducting layer, and an organic layer interposed between the two conducting layers. The organic layer comprises a compound selected from Formula I, Formula II, their salts, stereoisomers, solvates, or combinations thereof. These compounds exhibit multiple redox states and voltage-dependent geometric isomerism, enabling enhanced electronic switching behavior and multilevel data storage capabilities. The organic materials are sensitive to external stimuli such as voltage, light irradiation, and pH variations, allowing multifunctional integration of sensing, memory, and computing functionalities within a single device architecture. This present disclosure provides a scalable, energy-efficient, and cost-effective platform for advanced memory and neuromorphic computing applications.

The present invention provides a DA conversion device and the like that use the range of low voltage dependency of a MOS capacitor to make it possible to reduce nonlinearity of an output voltage. A charge scaling type DA conversion device comprising a high-order bit side capacitor array and a low-order bit side capacitor array that are connected via an attenuation capacitor comprises a control circuit that applies a voltage, to a plurality of capacitors of the high-order bit side capacitor array and a plurality of capacitors of the low-order bit side capacitor array, so that all of the capacitors have a positive bias voltage or a negative bias voltage at the times of reset and conversion of the DA conversion device, wherein at least one of a reference voltage of the low-order bit side capacitor array and a reset voltage is set to a value different from a reference voltage of the high-order bit side capacitor array.

The present disclosure relates to managing capacitor voltage dependence. A system for reducing voltage dependence effects of a first capacitor caused by a first voltage can include a first capacitor that can include a first physical separation between a first capacitor terminal conductor of the first capacitor and a second capacitor terminal conductor of the first capacitor. The system can also include a second capacitor that can include a second physical separation between a first capacitor terminal conductor of the second capacitor and a second capacitor terminal conductor of the second capacitor, wherein the second physical separation is different than the first physical separation. The system can also include a compensation circuit that can be arranged to receive and at least partially offset voltage dependent signal contributions from each of the first and second capacitors for output to a signal processing circuit.

The application discloses a long short-term memory neural network circuit based on spintronics and a control method, which comprises an input circuit, a weight circuit and an activation function circuit. The input circuit utilizes a magnetic domain wall-magnetic tunnel junction device to realize time integration of the current time input and the previous time state by analog control of the magnetic domain wall position. The weight circuit comprises a cross array composed of multi-state magnetic domain wall-magnetic tunnel junction devices, wherein the synaptic weight is non-volatile stored as a discrete magnetic domain wall position defined by a photolithography notch. The weight circuit performs a matrix vector multiplication operation in the analog domain. The activation function circuit comprises a random magnetic tunnel junction device, which provides a nonlinear activation function by utilizing the voltage-dependent probability flipping characteristics of the random magnetic tunnel junction device. The application does not need a memristor and a conventional CMOS logic to realize the core LSTM operation, thereby significantly reducing the hardware area, power consumption and delay.

To provide a DA conversion device or the like capable of reducing a non-linearity of an output voltage by using a range in which voltage dependency of a MOS capacitor is low.SOLUTION: A charge scaling type DA conversion device comprising an upper bit side capacitor array and a lower bit side capacitor array connected via a damping capacitor includes a control circuit for applying a positive bias voltage or a negative bias voltage to all of a plurality of capacitors of an upper bit side capacitor array and a plurality of capacitors of a lower bit side capacitor array at a time of resetting and conversion of a DA conversion device. At least one of a reference voltage of the lower bit side capacitor array and a reset voltage is set to a value different from the reference voltage of the upper bit side capacitor array.SELECTED DRAWING: Figure 1