75 results about "Logic level" patented technology

A fault detection circuit provides hardware-based fault detection to a system including power electronics. The fault detection circuit includes sensor interfaces and scaling amplifiers to scale sensor outputs for comparison to reference voltages at respective comparators. Logic levels output from the comparators are received at logic gate circuits and used to determine a master logic level that is used to control a gate driver, thereby directing response to the detection of a fault by the fault detection circuit. The fault detection circuit can be included in a motor controller such as a motor controller of a hydraulic power pack.

A duty cycle correction device and a duty cycle correction method thereof are disclosed. A duty cycle adjustment circuit adjusts a duty cycle of an input clock signal to output an output clock signal. An integrator circuit generates an integral signal according to the output clock signal. A correction control circuit periodically controls the duty cycle adjustment circuit to adjust an adjustment amount of the duty cycle according to a change of a logic level of the integral signal.

The application relates to the field of integrated circuit design, in particular to a double-tail dynamic comparator based on a feedback structure, which comprises a preamplifier, a latch and a positive feedback structure which are cascaded with each other; the preamplifier comprises input ends VIP and VIN, output ends fn and fp, and is used for amplifying comparison signals of the input ends; the latch is used for carrying out digital judgment on the amplified comparison signals and latching a judgment logic level; and the positive feedback structure is used for providing a discharge path for fn and fp and increasing a differential voltage between fn and fp. The application introduces the design of the positive feedback structure, adds a new discharge path to the output node of the amplifier to accelerate the pre-amplification speed, and increases the differential voltage between the output nodes fn and fp, so as to reduce the regeneration time of the latch, inhibit the influence of non-ideal factors on the comparator when the input differential signal is small, and accelerate the comparison speed.

A method and an apparatus for memory testing are provided. The method includes following steps: after multiple dies are idle for a first time, performing a first stage test on the dies, and setting multiple flags corresponding to the dies that fail the first stage test to a first logic level; after the dies are idle for a second time, performing a second stage test on the dies, and regarding the dies that pass the second stage test and have the corresponding flags set to the first logic level as suspected good dies and keeping the suspected good dies idle; and after the suspected good dies are idle for a third time, performing a third stage test on the suspected good dies.

The present disclosure relates to a semiconductor device and a method of operating a semiconductor device. The semiconductor device includes a charge pump circuit configured to generate an output voltage by pumping an input voltage according to a first master clock and a second master clock; a voltage detection circuit configured to generate a comparison signal by comparing the output voltage with a reference voltage; and a drive control circuit configured to: selectively invert the first external clock and the second external clock at a start time of an active period of the comparison signal to receive the inverted clocks as first internal clocks and second internal clocks; generate the first master clock and the second master clock according to the first internal clocks and the second internal clocks while controlling a transition order such that the second master clock transitions after the first master clock transitions during the active period of the comparison signal; and store logic levels of the first master clock and the second master clock as a first preliminary clock and a second preliminary clock, respectively, at an end time of the active period of the comparison signal.

This application provides a cascaded reverse conduction control circuit and a power converter, belonging to the field of electronic circuit technology. The pulse width modulation signal is transmitted to the action module via a first driving module. The output terminal of the action module is connected to the gate of a first high-voltage depletion-type transistor (HMT). The sampling terminal of the action module is connected to the first terminal of a detection module. The second terminal of the detection module is connected to the drain of the first HMT. The third terminal of the detection module and the action module are both connected to the source of a low-voltage enhancement-type transistor (LVMT). Logic levels are transmitted to the gate of the LVMT via a second driving module. The detection module detects the voltage and current directions of the cascaded structure. Driven by the detection module, the action module controls the first HMT to conduct. This application simplifies the reverse conduction control strategy for gallium nitride (GaN) power devices and reduces the cost of reverse conduction control for GaN power devices.

This invention discloses a bidirectional power supply fault early warning method based on a hardware protection mechanism, belonging to the field of fault early warning technology. The method includes the following steps: acquiring parameters and signals; calculating the approximation sequence; identifying switching intervals; extracting and shielding micro-triggers; weighted accumulation to obtain an exponent; and threshold comparison for early warning. This invention acquires real-time operating electrical parameters and logic level signals, generates a protection approximation sequence, and identifies energy flow switching intervals. When the logic level signal is not locked and flips, micro-trigger features are extracted and time-domain shielded to obtain an effective micro-trigger sequence. The protection approximation sequence is then weighted and accumulated to obtain a hardware stress residual exponent. Finally, fault early warning is achieved by comparing with a safety threshold, realizing a shift from post-event protection to pre-event early warning. This solves the problem in existing technologies where hardware protection circuits can only cut off the circuit after a fault occurs, failing to provide early warning during device aging or performance degradation.

A fault detection circuit provides hardware-based fault detection to a system that includes power electronics. The fault detection circuit includes sensor interfaces and scaling amplifiers to scale sensor outputs for comparison with reference voltages at the respective comparators. The logic levels at the comparator outputs are received at logic gate circuits and used to determine a master logic level, which is used to drive a gate driver, thus directing a fault detection response through the fault detection circuit. The fault detection circuit can be included in a motor control device, such as a hydraulic power unit motor driver. Figure for abstract: [Fig 1]

Embodiments of the present application provide a shift logic circuit optimization method, a computer device and a storage medium. The method comprises: obtaining a first shift logic circuit, the first shift logic circuit comprising a first shift sub-circuit; determining a minimum input signal set corresponding to the first shift logic circuit, the minimum input signal set comprising the least input signals driving all logic outputs of the first shift logic circuit; constructing a second shift sub-circuit based on the minimum input signal set; and replacing the first shift sub-circuit in the first shift logic circuit with the second shift sub-circuit to obtain a second shift logic circuit. The technical solution provided by the embodiments of the present application has the advantages that the number of combination logic blocks included in the second shift logic circuit is also less than the number of combination logic blocks included in the first shift logic circuit, the number of logic levels included in the second shift logic circuit is generally shallower, the circuit complexity is lower, and it is easier to implement further optimization of the second shift logic circuit by a subsequent synthesis tool.

This utility model discloses a video signal splicing circuit and a display device. The video signal splicing circuit includes: a control module, used to split an original video signal of a first resolution into a first video signal of a second resolution and a second video signal of a second resolution; the second resolution is half of the first resolution; a data conversion module, connected to the control module, wherein the data conversion amount of the data conversion module matches the data amount of the first video signal and the second video signal, used to receive the first video signal and convert it into a first logic level signal, and also used to receive the second video signal and convert it into a second logic level signal; and a signal synthesis module, connected to the data conversion module, used to synthesize the first logic level signal and the second logic level signal into a display video signal of the first resolution, and transmit it to the display module for image display. This utility model has a low cost and achieves high-resolution image display.

The application discloses a lithium niobate on-chip reconfigurable diffraction computing system and method based on digital driving, and belongs to the technical field of optical computing. The system comprises a digital logic control module, a high-voltage digital interface module, a lithium niobate on-chip diffraction computing module and an optical input / output coupling module. The digital logic control module converts the binary logic level signal input from outside into a thermometer code control signal, which is directly converted into a binary switch driving signal through the high-voltage digital interface module, without the need for digital-to-analog conversion. The lithium niobate on-chip diffraction computing module comprises a diffraction pixel unit composed of a lithium niobate and a silicon dioxide composite waveguide. Each pixel unit is provided with equal-length sub-electrode segments segmented along the light propagation direction above the pixel unit. Discrete phase accumulation is realized through binary driving. The number of activated sub-electrode segments is proportional to the phase delay, full phase coverage in the range of 0-2pi is realized, and the modulated light wave completes diffraction computing through interference superposition.

The application discloses a power supply control system and method applied to a nerve stimulator, and the system comprises a power management module and a central control processing module, the power management module provides a direct current voltage to the central control processing module, and the central control processing module controls the working mode of the power management module through a digital logic level, wherein a diode and a pin row connected in parallel with the diode are connected between the power management module and the central control processing module, the diode is used for forming a one-way voltage passage from output to input, preventing the current of the starting power supply from flowing reversely into a direct current converter to burn the direct current converter, and reducing the voltage consumption of the passage itself, and the pin row is used for short-circuiting the pin row to eliminate the voltage drop on the diode after the system is stabilized. The application realizes the low-cost requirement of the nerve stimulator by simplifying the circuit design and using low-cost components, and designs a peripheral circuit to realize the stable working and feedback regulation functions of the system.

This application, in the field of chip development, provides a method and apparatus for reducing the number of signal logic levels. The method includes: determining critical signals and target signal points; determining logic modules based on the critical signals and target signal points; replicating the logic modules to obtain multiple logic modules, the number of which is determined according to the bit width of the critical signals; determining the input signals of each logic module; inserting a multiplexer between the output terminals of the multiple logic modules and the target signal points, and connecting the critical signals to the selection terminals of the multiplexers. This application, by replicating logic modules with multiple logic levels as a whole and connecting them through multiplexers, effectively reduces the number of logic levels in the critical path, reduces the risk of RTL code modification iterations and verification, accelerates front-end and back-end iterations and timing convergence, and effectively increases the design frequency.

This invention discloses a post-mapping optimization method for RSFQ circuits based on path balancing, comprising: parsing the topological connection relationships of nodes in the netlist and presetting the number of iterations; constructing candidate supergates and calculating P-class truth tables, classifying and storing them after P-class transformations, with each P-class truth table storing only the candidate supergate with the fewest JJs, forming a supergate library; perturbing the node hierarchy of the netlist, randomly assigning logic levels, and inserting DFFs; traversing the netlist in reverse to extract fan-out free cones, calculating Boolean function truth tables and performing P-class transformations, matching equivalent structures, and if the number of JJs in the library is smaller, performing an inverse P-class transformation and replacing them in the netlist; performing retiming optimization on the netlist, deleting D flip-flops and continuing iterations or outputting the final netlist. This method has significant advantages in reducing the number of JJs, reducing DFF overhead, and improving the optimization space and efficiency of the mapped RSFQ circuit netlist.

Each latch cell in a latch cell array is made of 12 MOS transistors including a first CMOS switch transferring write data and a second CMOS switch transferring read data. A test for rewriting a storage node on a write bit line side in each latch cell from a first logic level to a second logic level in a state in which the first and second CMOS switches are respectively controlled to be on in overlapping time periods is assumed. In this case, a disturb test circuit precharges a read bit line to the second logic level before the second CMOS switch is controlled to be on.

The utility model discloses an IH conditioner supporting single-phase and three-phase power supply switching, and relates to the technical field of IH conditioners, the IH conditioner comprises a power supply module used for supplying power, an IH driving module used for heating, a three-phase under-loss detection module and a single-phase and three-phase power supply switching module; wherein the input end of the three-phase under-loss detection module is connected with the output end of the power supply module, the output end of the three-phase under-loss detection module is connected with the input end of the single-three-phase power supply switching module, and the three-phase under-loss detection module is used for receiving electrical parameter data output by the power supply module and outputting a logic level signal based on the electrical parameter data to the single-three-phase power supply switching module; and the input end of the single-three-phase power supply switching module is connected with the output end of the power supply module, the output end of the single-three-phase power supply switching module is connected with the IH driving module, and the single-three-phase power supply switching module is used for receiving the logic level signal output by the three-phase under-loss detection module and outputting a frequency conversion signal to the IH driving module based on the logic level signal. The method has the beneficial effects that the working reliability of the IH conditioner is improved, and the user experience is improved.

A memory device, a current-to-voltage converter, and a data line pre-charge method are provided. The current-to-voltage converter includes a first pre-charge circuit, a second pre-charge circuit, and a pull-down circuit. The first pre-charge circuit is configured to pre-charge a voltage on a data line to a preset voltage according to a sensing enable signal at a first logic level during a pre-charge period of a data sensing operation; The second pre-charge circuit is configured to generate a feedback voltage according to the voltage on the data line and pull up the voltage on the data line according to the feedback voltage during the pre-charge period. The pull-down circuit is configured to discharge the data line according to the sensing enable signal at a second logic level.

A selection summing latch circuit for a decision feedback equalizer includes a selection summing unit, a latch amplifier, a sampler and a resetter. When a sampling clock is at a high level, the selection summing unit is configured to selectively select a positive reference voltage or a negative reference voltage to sum with an input signal according to the logic levels of a positive selection signal terminal and a negative selection signal terminal to obtain a summation result, the latch amplifier is configured to latch and amplify the summation result and output an output result to a positive output signal terminal and a negative output signal terminal, and the sampler is configured to sample the selection summing unit. The resetter is configured to reset the positive output signal terminal and the negative output signal terminal when the sampling clock is at a low level.

To provide a liquid dispensing device that can achieve both improved accuracy in determining the condition of the dispensing section and reduced inspection time for the condition of the dispensing section. [Solution] A liquid dispensing device comprising: a transport unit for transporting a medium; a dispensing unit for dispensing liquid into the medium; a residual vibration detection circuit that acquires a residual vibration signal corresponding to residual vibrations generated in the dispensing unit and outputs a residual vibration detection signal corresponding to the residual vibration signal; a first conversion circuit including a comparison circuit that outputs a comparison result signal whose logic level changes according to the comparison result between the voltage value of the residual vibration detection signal and a reference voltage value; a second conversion circuit including an A / D conversion circuit that outputs a detection voltage signal obtained by converting the residual vibration detection signal into a digital signal; and a determination circuit for determining the state of the dispensing unit, wherein the determination circuit has a first determination mode for determining the state of the dispensing unit according to the comparison result signal and a second determination mode for determining the state of the dispensing unit according to the detection voltage signal.

This utility model discloses an electromagnet extension circuit and an electromagnet control system, relating to the field of electronic circuits. It addresses the problem that the number of reserved I / O interfaces in a main control device is often insufficient to control multiple electromagnets. The extension is achieved by using the differential signal interface typically reserved in the main control device. An RS485 level conversion isolation circuit converts the input differential signal into a single-ended digital logic level signal, which is then input to the microcontroller's port. This allows the main control device to communicate with the microcontroller using differential signals. After receiving commands, the microcontroller controls the MOSFET driver unit through its signal output. The microcontroller receives commands from the main control device and distributes them to the outputs of different MOSFET driver units to control multiple electromagnets, reducing the main control device's requirement for a large number of I / O interfaces. The electromagnet current monitoring unit then controls the output enable port of the MOSFET driver unit based on the monitoring results, forming a closed-loop feedback control to prevent electromagnet damage due to overcurrent.

This invention relates to a mining positioning card and its charging protection method, belonging to the field of mining positioning card charging safety technology. The positioning card includes a charging detection module, a power management module, a battery pack unit, a main controller unit, and other functional units. The charging detection module receives power input from the charger, supplies power to the power management module, and detects the charging current and voltage. Based on the charging status, it outputs a first logic level signal to the power management module. The main controller unit performs protocol matching with the charger and outputs a second logic level signal to the power management module based on the protocol matching result. The power management module combines the first and second logic level signals to determine whether the battery pack unit is charging. This invention can protect the positioning card's mainboard components from damage caused by high voltage and high current, avoid affecting battery performance and lifespan, and ensure the positioning card operates normally, stably, and reliably underground.

The application relates to a PWM collision signal processing device, a method and a vehicle. The device comprises a level conversion circuit, a differential signal conversion circuit and a microcontroller, wherein the level conversion circuit is used for receiving a PWM collision signal and converting the PWM collision signal into a single-ended PWM signal in the form of a logic level; the differential signal conversion circuit is connected with the level conversion circuit and is used for converting the single-ended PWM signal into a differential signal for transmission; and the microcontroller is connected with the differential signal conversion circuit and is used for performing collision detection or identifying a short-circuit fault based on the differential signal. The application suppresses electromagnetic interference through single-ended-to-differential transmission, and distinguishes a collision state from a wire harness short-circuit fault based on differential signal characteristics by the microcontroller, so that the technical problems that a PWM collision signal is prone to interference and a wire harness short circuit is prone to triggering a false judgment of an MCU are solved.

This invention relates to the field of data storage technology and discloses a method for testing the signal quality of the I / O interface of a memory module. The method includes: verifying the signal integrity of the I / O interface in the memory module based on eye diagram analysis; after verifying signal integrity, quantitatively comparing the morphological characteristics of the input and output eye diagrams, and determining whether morphological changes have occurred during signal transmission. These morphological changes include at least logic level flipping errors, timing recognition errors, and signal quality degradation. If the morphological characteristics of the input and output eye diagrams are consistent, the test is successful; if they are inconsistent, the test fails. This invention achieves visualized and quantitative verification of signal integrity through eye diagram analysis, covering multiple dimensions such as voltage, timing, and noise, providing a more comprehensive reflection of signal transmission quality compared to single-parameter testing.

A fault detection circuit provides hardware-based fault detection for a system that includes power electronics. The fault detection circuit includes sensor interfaces and scaling amplifiers to scale sensor outputs for comparison with reference voltages at respective comparators. The logic levels output by the comparators are received by logic gate circuits and used to determine a master logic level, which controls a gate driver, thus controlling the response to a fault detection by the fault detection circuit. The fault detection circuit can be included in a motor control system, such as the motor control unit of a hydraulic power unit.

It can suitably generate signals at any desired timing. [Solution] The timing generator comprises a counter, a control unit, a plurality of basic pulse generation units, and one or more latch output units. The counter performs a counting operation based on a clock signal. The control unit controls the operating state of each basic pulse generation unit by setting an operation start counter value for each of the basic pulse generation units. When the counter value input from the counter becomes the operation start counter value, the basic pulse generation unit enters an operating state and controls the logic level of at least one of the latch output units. The latch output unit outputs a timing signal corresponding to the control by at least one of the basic pulse generation units.

The application discloses a kind of capacitive coupling dynamic encoding isolation method and system, through the dual mechanism of dynamic encoding mapping and adaptive filtering reconstruction, the influence of parasitic pulse string on signal integrity is significantly reduced, ensure that the zero error rate and high reliability of data transmission in high voltage transient environment, while maintaining the high response speed of system, avoid the signal delay caused by traditional filtering means, greatly improve the running stability of power electronic system in complex electromagnetic environment, effectively solve the problem that receiving end misjudges logic level due to fixed threshold and simple filtering cannot cope with dynamic common-mode transient voltage interference in prior art.