607 results about "Logic level" patented technology

An amplification circuit is configured to differentially amplify an input signal and a reference voltage to generate an output signal when a clock signal has a first logic level. The amplification circuit is configured to precharge the output signal when the clock signal has a second logic level. The amplification circuit is configured to adjust a current driving force that precharges the output signal based on the reference voltage.

The invention discloses a circuit level optimization method based on NAND and XOR majority logic, which comprises the following steps of: analyzing target design circuit information to obtain an NAND graph AIG; logic optimization with the optimization node number as the target is executed on the AIG; the AIG after node number optimization is logically converted into an XOR majority logic diagram XMG; logic optimization with the optimization logic hierarchy as the target is executed on the XMG obtained through logic conversion; the XMG after logic hierarchy optimization is logically converted into an AIG; logic optimization with the optimization logic hierarchy as the target is executed on the AIG obtained through logic conversion; and executing time delay-oriented process mapping on the AIG after logic hierarchy optimization, and generating and outputting a process gate-level netlist. According to the method, the logic optimization processes of the AIG and the XMG are effectively combined, the local optimization problem in optimization is improved, the adaptability to a specific design target is enhanced, the optimization efficiency and effect of large-scale circuit design are improved, and a better circuit after logic optimization is obtained.

System and method for controlling synchronous rectification. For example, a system for controlling synchronous rectification includes: a first control-signal generator configured to generate a first control signal; a second control-signal generator configured to receive the first control signal for a first switching cycle and generate a second control signal for a second switching cycle based at least in part on the first control signal for the first switching cycle, the first switching cycle preceding the second switching cycle; and a driver configured to receive the first control signal and generate a drive voltage based at least in part on the first control signal; wherein the second control-signal generator is further configured to: process information associated with the first control signal; determine a first time duration when the first control signal remains at a first logic level during the first switching cycle.

The invention discloses a 23T4M anti-radiation TCAM storage unit circuit which comprises a pre-charging module, an RH reading circuit module, a programmable logic module, a reconfigurable magnetic tunnel junction storage module, a discharging module and an output module. In the RH reading circuit module, the grid electrode of a transistor N7 is connected with the drain electrode of a transistor N8, the grid electrode of the transistor N8 is connected with the drain electrode of the transistor N7, a cross coupling structure is formed, a node S0 and a node S1 are controlled by a node Q and a node QB, meanwhile, the node S0 and the node S1 control the charging and discharging paths of the node Q and the node QB respectively, and after any node is overturned by high-energy particles, the charging and discharging paths of the node Q and the node QB are controlled by the node S0 and the node S1. All the nodes are maintained or charged to recover to the original logic level. According to the method, data upset at a single sensitive node can be completely resisted, and meanwhile, the search error rate of the TCAM is improved.

The invention relates to the technical field of digital-analog hybrid integrated circuit design, and particularly provides a FlexRay bus receiver with low noise and wide common-mode input range, which is characterized in that a common-mode voltage division module receives a differential signal output by a bus and carries out voltage division, and then a pre-amplification module carries out amplitude limiting amplification on the signal after voltage division; the hysteresis comparator module generates threshold hysteresis and generates a logic level signal based on the signal after amplitude limiting amplification, and the digital logic receiving module receives and processes the logic level signal, generates a receiving data signal and transmits the receiving data signal to an external controller. According to the invention, the differential signal pair received on the FlexRay bus is subjected to voltage division and amplitude limiting amplification, so that a wider common-mode input range is provided, the problem of large ground potential difference is solved, and the capability of suppressing common-mode noise and the communication stability are improved. Meanwhile, the hysteresis comparator module suppresses noise false triggering by generating threshold hysteresis, and the anti-noise capability of the receiver is remarkably improved.

The power stage of the switching converter includes a high-side switch and a low-side switch that are operated by respective drive signals, respectively. The current sensing block generates a sensing current signal that undergoes blanking processing for a first time duration at the beginning of a longer phase of the high-side phase and the low-side phase. The sense current signal is de-blanked at the end of the first duration. The current sensing block generates a first pulse synchronized with the starting point of the longer phase, and the pulse width of the first pulse is equal to the first duration. The gate driver receives the first pulse and generates a delay pulse synchronized with the start point of the longer phase, the pulse width of the delay pulse being equal to the sum of the first duration and the second duration, the gate driver generating a drive signal (for the switch driven in the longer phase), the drive signal has a first logic level for a duration of at least a pulse width of the delayed pulse.

The invention provides a DFT test mode control circuit and method and a chip, and relates to the technical field of integrated circuit testing, and the circuit comprises a time sequence verification module which accesses a test clock signal and is used for recording a rising edge count value and comparing the rising edge count value with a pre-designed value to obtain a time sequence comparison result; the signal verification module is connected with a test data signal and is used for recording an actual sampling value and comparing the actual sampling value with a preset sampling value to obtain a signal comparison result; the test control module outputs a preset logic level signal to control the circuit to be tested to enter a DFT test mode when the rising edge count value is equal to a pre-designed value and the actual sampling value is equal to a preset sampling value. According to the circuit, signal resources output by existing ports are utilized to form a multi-verification mechanism for triggering a test mode, the reliability of the to-be-tested circuit entering the test mode is improved, ports do not need to be independently arranged, the number of the ports is reduced, the chip cost is reduced, and DFT test can be carried out when a chip does not have all test ports.

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an error check and scrub (ECS) circuit, a row hammer management circuit and a refresh control circuit. The ECC engine generates an error generation signal based on a result of an ECC decoding. The ECS circuit generates scrubbing addresses and outputs at least one of the scrubbing addresses as an error address based on the error generation signal. The row hammer management circuit stores an error flag with a first logic level in count cells, compares counted values with different reference number of times based on a logic level of the error flag and outputs a hammer address. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to the memory cell row corresponding to the hammer address.

A power stage of a switching converter contains a high-side switch and a low-side switch respectively operated by corresponding drive signals. A current-sense block generates a sensed-current signal which is blanked for a first duration upon start of a longer phase of a high-side phase and a low-side phase. The sensed-current signal is un-blanked upon end of the first duration. The current-sense block generates a first pulse starting synchronous with the start of the longer phase and with pulse-width equaling the first duration. A gate driver receives the first pulse and generates a delayed pulse starting synchronous with the start of the longer phase and with pulse-width equaling a sum of the first duration and a second duration. The gate driver generates drive signal (for the switch being driven with the longer phase) with a first logic level for a duration of at least the pulse-width of the delayed pulse.

A display device includes a pixel circuit and a stage of a scan driver. The stage of the scan driver is electrically coupled to the pixel circuit. The stage of the scan driver is configured to output a first scan signal and a second scan signal to the pixel circuit. A first enable voltage of the first scan signal is at a first logic level, and a first disable voltage of the first scan signal is at a second logic level. A second enable voltage of the second scan signal is at the second logic level.

In the present disclosure, a buffer outputs a gate drive signal indicating the same logic level as an element control signal, and an inverting buffer outputs a base drive signal indicating the opposite logic level to the element control signal. The resistance is interposed between the output of the buffer and the gate of an IGBT. A PNP bipolar transistor has its emitter connected to the gate of the IGBT and its collector connected to reference potential. A diode is interposed between the output of the buffer and a base of the PNP bipolar transistor. An output of the inverting buffer is connected to the base of the PNP bipolar transistor through a resistance.

A memory device includes a syndrome calculator configured to generate an error location signal based on first data and an error correction code; an error corrector configured to generate second data by correcting an error in the first data according to the error location signal; and a data mask (DM) calculation circuit configured to generate a DM signal according to logic high bits of the first data and change a logic level of the DM signal according to at least one of an increase signal and a decrease signal, by activating the increase signal when an error bit is detected in logic low bits of the first data and activating the decrease signal when the error bit is detected in the logic high bits of the first data, based on the error location signal.

The invention provides a multichannel HART (Highway Addressable Remote Transducer) dynamic communication system. The multichannel HART dynamic communication system comprises a modulation circuit and a demodulation circuit, the demodulation circuit of each channel comprises a hysteresis Schmitt trigger module and an analog quantity acquisition module which are parallel, the hysteresis Schmitt trigger module is configured to separate HART signals to obtain FSK signals in the HART signals, and the analog quantity acquisition module is configured to acquire the FSK signals in the HART signals. The FSK signal is converted into a digital pulse signal through the hysteresis Schmitt trigger and then is output to the controller, and the logic level of the digital pulse signal corresponds to the first frequency and the second frequency of the FSK signal; and the analog quantity acquisition module is configured to separate the HART signal to obtain a 4-20mA direct current component in the HART signal, convert the 4-20mA direct current component into a digital signal and output the digital signal to the controller.

Methods, systems, and devices for establishing memory system read window budget (RWB) are described. A memory system may receive a command from a host system requesting an RWB for an edge of a distribution of a logic level of a set of logic levels. The memory system may determine an expected pattern of data corresponding to a set of memory cells and may store the expected pattern in memory. The memory system may perform a voltage sweep operation, including setting a read voltage to different levels across the edge for reading the set of memory cells. The memory system may count a quantity of expected bits resulting from a logic function of the expected pattern and the read data for each level, and may output a voltage offset corresponding to level at which a difference of the quantity of expected bits and an initial quantity satisfies a threshold.

A data input and output circuit includes a data input circuit configured to precharge first and second input and output lines after the end of a power-up operation and configured to generate first and second input data by driving the first and second input and output lines from each of which transfer data having a set logic level, among first and second transfer data, are output after the start of a write operation. The data input and output circuit also includes a data output circuit configured to generate first and second internal data based on logic levels of the first and second input data.

The invention relates to the technical field of automatic control theory application and data center thermal management, and discloses a data center emergency refrigeration control method based on state space model prediction, which comprises the following steps: establishing a thermodynamic cycle state space equation; the refrigeration flow set value change rate and the water return side pressure change amount are obtained, and the dynamic heat exchange sensitivity is determined; monitoring feedback current characteristics of the driving unit, inverting cooling path resistance distribution and updating gain matrix elements; calculating a state prediction information sequence according to the temperature vector prediction deviation, and adjusting a time domain step length; the dynamic heat exchange sensitivity is introduced into prediction logic, controlled variable dynamic pressure retardation is compensated, an emergency refrigeration frequency control instruction is output, fluid fluctuation is converted into sensitivity compensation of a logic level, non-linear dynamic pressure damping of the emergency working condition is effectively impacted, the problems of control overshoot and logic instability caused by physical lag are solved, and the reliability of the system is improved. And the refrigeration response precision at the emergency conversion moment is improved.

A transmitting device is configured to generate a first encoded symbol and a second encoded symbol by encoding a first burst and a second burst, respectively. The transmitting device is configured to generate a first transmitting symbol and a second transmitting symbol by selectively inverting the first and second encoded symbols on the basis of a logic level of a bit with a specific sequence number of each of a previously generated transmitting symbol and the first burst.

A processing device may add at least one logic level metric count module to a circuit design, load the circuit design into an emulation system, and apply an emulation workload to the emulation system to which the circuit design is loaded. The processing device may then obtain at least one logic level metric count from the at least one logic level metric count module, the at least one logic level metric count associated with at least a portion of the emulation workload, and present at least one power utilization estimate for the circuit design, where the at least one power utilization estimate for the circuit design is based upon the at least one logic level metric count.

The invention is suitable for the technical field of processors, and particularly relates to a speculative wake-up-based data forwarding optimization system and method and related equipment. According to the method and the device, the data forwarding flag bit and the data forwarding pipeline number are set for the to-be-executed instruction, and whether the to-be-executed instruction needs to be subjected to data forwarding or not is judged according to the data forwarding flag bit; if yes, the instruction to be executed needs to obtain the corresponding source operand from the front instruction, data forwarding needs to be carried out, and the source operand is read from the corresponding pipeline of the assembly line according to the serial number of the data forwarding pipeline; and if the data forward flag bit is the second data forward flag bit, the instruction to be executed does not need to acquire the source operand from the front instruction and is directly read from the physical register, so that resource conflicts are reduced. Compared with the prior art, the method has the advantages that the logic level of the data forwarding behavior can be effectively reduced, and the running efficiency and performance of the processor are improved.

The invention relates to the technical field of data storage, and discloses a method for testing the signal quality of an IO interface of a memory module, and the method comprises the steps: verifying the signal integrity of the I / O interface in the memory module based on an eye diagram analysis method; after the signal is verified to be complete, the morphological characteristics of the input eye pattern and the output eye pattern are quantitatively compared, whether morphological characteristic changes occur in the signal transmission process or not is judged, and the morphological characteristic changes at least comprise logic level flipping errors, time sequence recognition errors and signal quality degradation; if the morphological characteristics of the input eye pattern are consistent with the morphological characteristics of the output eye pattern, the test is successful; and if the morphological characteristics of the input eye pattern are inconsistent with the morphological characteristics of the output eye pattern, determining that the test fails. Visual and quantitative verification of signal integrity is realized through eye pattern analysis, multi-dimensional indexes such as voltage, time sequence and noise are covered, and the signal transmission quality is reflected more comprehensively compared with a single parameter test.

A variable-gain multistage broadband low-noise amplifier comprises N (N > = 2) stages of amplifying circuits, the first stage of amplifying circuit and the second stage of amplifying circuit are connected through a first inter-stage matching circuit, a main circuit switch and an inter-stage matching circuit are sequentially connected between the subsequent stages of amplifying circuits in series, the input end is connected with an input matching circuit in series to be connected to the first stage of amplifying circuit, and the second stage of amplifying circuit is connected with a second stage of amplifying circuit. The Nth-stage amplification circuit is connected in series with a main switch and an output matching circuit in sequence to a signal output end; from the second stage, each stage of amplifying circuit and the main switch are integrally connected with a bypass switch in parallel; a source degeneration inductance scheme is adopted for input matching, and the noise performance is optimized; the overall gain flatness is improved through inter-stage matching; a multi-stage LC structure is adopted for output matching, and broadband matching in different gain modes is achieved; according to the invention, control of each switch is realized through logic level signals, switching of multiple gain modes is realized, the designed bandwidth reaches more than 10GHz, and the overall gain flatness and the noise coefficient in different gain modes are kept consistent.

The invention discloses a circuit and a method for demodulating current received by an instrument bus host, and relates to the technical field of instruments. The current demodulation circuit comprises an adder, the first input end of the adder is connected with an instrument bus MBUS to receive MBUS signals, the second input end of the adder receives reference voltage signals, and the output end of the adder outputs summing voltage signals; the resistor and capacitor charging and discharging device is connected with the output end of the summator so as to process the summing voltage signal; and the reverse input end of the comparator receives the MBUS signal, and the positive input end of the comparator receives the summing voltage signal processed by the resistor-capacitor charging and discharging device so as to determine the logic level corresponding to the MBUS signal based on the signal level of the output end of the comparator. According to the invention, the problem that the MBUS host receiving circuit cannot be compatible with all MBUS meters is solved.

The invention belongs to the technical field of integrated circuits, and particularly relates to a dynamic comparator suitable for a low-voltage high-speed analog-to-digital converter, the dynamic comparator adopts a three-stage latch circuit structure to realize rapid comparison of weak input signals so as to generate corresponding digital signals, and the method specifically comprises the following steps of: in a pre-amplification stage, pre-amplification is carried out; the positive feedback effect of the cross-coupled transistor pair is utilized to efficiently convert a tiny input voltage difference (lt; 10mV) into a recognizable voltage difference, and then through two-stage regeneration of the main latch module and the auxiliary latch module, a logic level is quickly output to complete quantization judgment. The auxiliary latch stage is additionally arranged on the basis of a traditional cross coupling latch circuit, the working speed of the comparator is effectively increased under the condition that only small area overhead is introduced, and the probability that the dynamic comparator has a metastable state is greatly reduced.

Examples of the present application relate to the field of semiconductors, and disclose a page buffer and an operation method thereof, a memory device and a memory system. The page buffer includes latch circuits, wherein the latch circuits includes: a latch control configuration circuit connected with a first data node and a second data node, and configure the first data node and the second data node to different logic levels respectively in response to a configuration signal, wherein a logic level of the first data node is opposite to a logic level of the second data node; and a latch transmission circuit connected with the first data node, the second data node, and a sense node, and configured to: couple the second data node with the sense node in response to a transmission signal, to transmit a configuration result of the latch control configuration circuit to the sense node.

The invention discloses a configurable dynamic vehicle-mounted dimming method and system for tunnel lamp illumination, and the method comprises the following steps: dividing a target tunnel into a plurality of dimming sections, further dividing a dimming loop in each dimming section, and carrying out the deployment of an illumination unit and an incoming vehicle detector based on a division result; a dimming counting interval of a logic level is constructed, a dynamic mapping relation is established between the dimming counting interval and a dimming loop of a physical level, and the dimming counting interval is a minimum logic unit used for vehicle tracking and counting; an independent vehicle counter is configured for each dimming counting interval, and a counting updating rule is set; configuring a security policy for counting function activation and dimming execution; and responding to the triggering of the coming vehicle detector, updating the vehicle count in the dimming counting interval in real time, and adjusting the brightness of the dimming loop based on the security policy. Compared with the prior art, the configurable dynamic vehicle-mounted dimming method and the configurable dynamic vehicle-mounted dimming system have remarkable progress in the aspects of energy conservation and safety.

The invention discloses an unmanned aerial vehicle chip sensitive data access control method based on a trusted execution environment, and relates to the technical field of unmanned aerial vehicle security. If data encryption is carried out, real-time confusion processing is carried out on power consumption, electromagnetic signals and execution time of the unmanned aerial vehicle chip; the trusted execution environment isolates a processing space of sensitive data from a logic level to prevent unauthorized access; the real-time confusion processing performs dynamic interference aiming at the core physical characteristics of the side channel attack, so that an attacker cannot derive an encryption key or algorithm logic through a physical signal of a monitoring chip; according to the method, the chip presents highly unpredictable physical characteristics in the encryption process through the synergistic effect of the power consumption, the electromagnetic signal and the execution time, the side channel attack difficulty is remarkably improved, and multi-level guarantee is provided for safe processing of sensitive data of the unmanned aerial vehicle.

The invention discloses a filter system used for BDC ripple detection, which comprises a DC power supply, a ripple motor, a current sensing amplifier, a filter, an MCU central processing unit, a comparator and an LDO linear voltage regulator, the current sensing amplifier of the filter system senses current ripples, and the filter carries out filtering and amplification to obtain the ripple ripples. And then converting into a rising edge and a falling edge (PWM waves) of a 3.3 V digital logic level series which can be acquired by the MCU through a comparator, and finally, determining the speed and the position of the BDC through counting analysis of the MCU and feeding back so as to control the ripple motor.

According to an embodiment, a bootstrap drive circuit for driving a bootstrap switch in a DC-DC converter is proposed. The bootstrap drive circuit includes a non-overlapping circuit, a first and a second capacitor, and a first and a second n-channel transistor. The non-overlapping circuit is configured to receive an input signal, the input signal being a function of a pulse width modulated (PWM) signal, wherein the input signal and the PWM signal are characterized by a first logic level, generate a first control signal from the input signal at a first output terminal of the non-overlapping circuit, the first control signal having the first logic level, and generate a second control signal from the input signal at a second output terminal of the non-overlapping circuit, the second control signal being characterized by a second logic level different from the first logic level.

The present invention discloses a level conversion circuit, through a bias voltage V BIAS circuit, and the logic level signals in the low voltage domain are input from the source terminals of NMOS transistors M 21 and M 22 to strengthen the current output capabilities of NMOS transistors M 21 and M 22 and improve the speed of the level conversion circuit, enabling it to operate at a lower supply voltage. When the level conversion circuit is enabled, the bias transistor M BIAS has no body effect, while the NMOS transistors M 21 or M 22 have body effects. By utilizing the threshold voltage difference brought about by the body effect of MOS transistors, the NMOS transistors M 21 or M 22 are turned off, enabling the level conversion circuit to have zero static power consumption; the bias transistor M BIAS and the NMOS transistors M 21 , M 22 are all thick-gate NMOS transistors with good matching properties. Therefore, the speed and static leakage current of the level conversion circuit vary less with the process. When there are a large number of level conversion circuits, the same bias circuit can be shared to reduce the circuit power consumption.

A Phase Change Memory (PCM) device includes sets of cells in which a binary logic level is written by a write operation. Each cell is included in a respective set of cells in the sets of cells. The write operation includes: performing write verify operations on the cells to identify an actual logic level stored in the cells; checking if the identified actual logic level matches a certain the binary logic level; in response to the checking determining that in at least one cell the actual logic level fails to match the binary logic level, correcting the actual logic level to match the binary logic level by performing: a set write operation in case the binary logic level is a high logic level, or a reset write operation in case the binary logic level is a low logic level.