166 results about "Logic level" patented technology

The invention relates to the technical field of automatic control theory application and data center thermal management, and discloses a data center emergency refrigeration control method based on state space model prediction, which comprises the following steps: establishing a thermodynamic cycle state space equation; the refrigeration flow set value change rate and the water return side pressure change amount are obtained, and the dynamic heat exchange sensitivity is determined; monitoring feedback current characteristics of the driving unit, inverting cooling path resistance distribution and updating gain matrix elements; calculating a state prediction information sequence according to the temperature vector prediction deviation, and adjusting a time domain step length; the dynamic heat exchange sensitivity is introduced into prediction logic, controlled variable dynamic pressure retardation is compensated, an emergency refrigeration frequency control instruction is output, fluid fluctuation is converted into sensitivity compensation of a logic level, non-linear dynamic pressure damping of the emergency working condition is effectively impacted, the problems of control overshoot and logic instability caused by physical lag are solved, and the reliability of the system is improved. And the refrigeration response precision at the emergency conversion moment is improved.

The invention relates to the technical field of data storage, and discloses a method for testing the signal quality of an IO interface of a memory module, and the method comprises the steps: verifying the signal integrity of the I / O interface in the memory module based on an eye diagram analysis method; after the signal is verified to be complete, the morphological characteristics of the input eye pattern and the output eye pattern are quantitatively compared, whether morphological characteristic changes occur in the signal transmission process or not is judged, and the morphological characteristic changes at least comprise logic level flipping errors, time sequence recognition errors and signal quality degradation; if the morphological characteristics of the input eye pattern are consistent with the morphological characteristics of the output eye pattern, the test is successful; and if the morphological characteristics of the input eye pattern are inconsistent with the morphological characteristics of the output eye pattern, determining that the test fails. Visual and quantitative verification of signal integrity is realized through eye pattern analysis, multi-dimensional indexes such as voltage, time sequence and noise are covered, and the signal transmission quality is reflected more comprehensively compared with a single parameter test.

According to an embodiment, a bootstrap drive circuit for driving a bootstrap switch in a DC-DC converter is proposed. The bootstrap drive circuit includes a non-overlapping circuit, a first and a second capacitor, and a first and a second n-channel transistor. The non-overlapping circuit is configured to receive an input signal, the input signal being a function of a pulse width modulated (PWM) signal, wherein the input signal and the PWM signal are characterized by a first logic level, generate a first control signal from the input signal at a first output terminal of the non-overlapping circuit, the first control signal having the first logic level, and generate a second control signal from the input signal at a second output terminal of the non-overlapping circuit, the second control signal being characterized by a second logic level different from the first logic level.

An event notification method and apparatus, a device, a computer program product, and a storage medium. A binding mechanism between queue pairs and completion queues involved in an event notification mechanism of a second protocol is modified, and it is proposed that the binding between queue pairs and completion queues be performed in accordance with the jurisdiction relationship between network connections and listening instances in a first protocol. Listening instances invoked in an event notification mechanism of the first protocol are also partially modified at the user-space logic level, and it is proposed that completion queues be registered within the listening scope of corresponding listening instances. A listening instance determines, by monitoring completion queue entries in a completion queue, whether a readiness event has occurred on a network connection established according to the first protocol. Then, on the basis of these completion queue entries, an event notification result conforming to the first protocol is generated and returned to an application. Accordingly, compatibility of the event notification mechanisms between the two protocols can be achieved without requiring modification of the program code of the application.

The utility model discloses a track circuit reader test interface switching device, and relates to the field of track circuit equipment. The utility model aims to solve the problem that the traffic safety is influenced because the number of test items of TCR equipment is small. According to the track circuit reader test interface switching device of the utility model, a CAN signal input / output end of a CAN isolation transmit-receive module is used for being connected with a CAN bus of a DB15 connector, and a logic level input / output end of the CAN isolation transmit-receive module is connected with a logic level input / output end of an MCU. The parallel port information input and output end of the MCU is connected with the parallel port information input and output end of the optocoupler, and the optocoupler outputs or receives signals through the external input and output signal test interface module.

The invention relates to the technical field of data acquisition, in particular to a data acquisition method and system with a reusable differential signal interface. The device comprises a bottom plate and a data acquisition card used for acquiring analog signals, uniform interfaces are adopted and comprise a plurality of differential signal pairs used for transmitting commands, a plurality of differential signal pairs used for transmitting data and a plurality of differential signal pairs used for transmitting clocks. According to the reusable differential signal interface disclosed by the invention, the signal integrity and reliability of long-distance transmission of signals on a bottom plate are improved through differential signals, a system can stably work in a severe electromagnetic environment, and the reusable interface can be in mixed plug-in connection with different data acquisition cards of voltage, current, strain, temperature and the like according to requirements. According to the method, step-by-step power-on is adopted, identity recognition and software configuration are only performed on a digital logic level after insertion, and simulation power supply is performed after recognition is passed, so that chain risks such as power supply impact, bus locking and even system downtime caused by insertion faults or incompatible modules are eliminated.

The signal transmission device has room for further consideration regarding drive control of the switch to be driven.SOLUTION: The signal transmission device 200X includes a transmission circuit S2 for outputting a control signal 350x, a reception circuit 400x, and an insulating circuit 500. The receiving circuit 400x receives an external signal S1x. The receiving circuit 400x drives the drive object switch S1x based on the control signal S2 in a state in which the external signal SW10 is at a first logic level, and drives and controls the drive object switch S1x based on the external signal S2 regardless of the control signal S1x in a state in which the external signal SW10 is at a second logic level.SELECTED DRAWING: Figure 11

According to one embodiment, semiconductor integrated circuit includes: first and second pulse generators that generate first and second pulse signals based on a first signal, and third and fourth pulse signal based on a second signal, respectively; first and second inversion buffers that output a third signal based on inputs of the first and third pulse signals, and a fourth signal based on inputs of the second and fourth pulse signal, respectively; wherein, when a logic level of the first or the third pulse signal changes from a first logic level to a second logic level, the first inversion buffer changes a logic level of the third signal, and when a logic level of the second or the fourth pulse signal changes from the first logic level to the second logic level, the second inversion buffer changes a logic level of the fourth signal.

The invention discloses a heat supply pipe network inspection decision method fusing multi-agent cooperation and digital twinning, and the method comprises the steps: building a heat supply pipe network digital twinning model through the cooperative interaction of a model-level agent, an equipment-level agent and a logic-level agent; performing pipe network anomaly analysis through a digital twinborn model, and generating a temporary pipe network inspection task; the method comprises the following steps: receiving a total inspection task demand including a pipe network temporary inspection task and a preset pipe network conventional inspection task through an inspection management agent, and extracting inspection key parameters; splitting and allocating a total task demand through an inspection task planning agent according to the inspection key parameters and the resource capability characteristics of each inspection device, so that the inspection device obtains an allocated inspection sub-task plan; outputting a scheduling action sequence of executing the inspection subtasks by each inspection device through the inspection task scheduling agent, and issuing the scheduling action sequence to the inspection device; and generating a heat supply pipe network inspection report through the inspection task execution feedback agent, and feeding back the heat supply pipe network inspection report.

The invention discloses a substation interface configuration operation and maintenance method and system based on functional identity recognition, and belongs to the technical field of substation operation and maintenance. According to the invention, the anti-misplug guide keys are configured for the in-cabinet interface and the out-cabinet interface through the in-cabinet interface configuration data and the out-cabinet interface configuration data, so that misplug and misplug between the interfaces on an object quantity connection layer are avoided; by generating a function identity identification code and constructing a function mapping database, digital management of function logic configuration between interfaces is realized, and the complexity and error rate of manual parameter configuration are reduced; simple and efficient substation interface configuration is realized; then the to-be-overhauled interface is identified through the substation operation and maintenance requirement, the function mapping database and the function identity identification code, the to-be-overhauled interface needing to be isolated can be accurately identified from the interface function logic level, the risk of isolation leakage or misoperation is avoided, efficient and accurate substation interface operation and maintenance are achieved, and the operation efficiency is improved. And the efficiency and the accuracy of substation interface configuration operation and maintenance are improved.

A fault detection circuit provides hardware-based fault detection to a system including power electronics. The fault detection circuit includes sensor interfaces and scaling amplifiers to scale sensor outputs for comparison to reference voltages at respective comparators. Logic levels output from the comparators are received at logic gate circuits and used to determine a master logic level that is used to control a gate driver, thereby directing response to the detection of a fault by the fault detection circuit. The fault detection circuit can be included in a motor controller such as a motor controller of a hydraulic power pack.

The disclosure provides a circuit (700) and method for correcting single event upsets, SEUs, or glitches in electronic circuits. The circuit includes rising and falling edge detection sub-circuits (710, 712) connected to a sequential circuit element output (706) which generate signals if the sequential circuit element output changes logic levels, and comparison sub-circuits (716, 724) which compare the signal from the edge detection sub-circuits with a signal generated on an active edge of a clock signal of the sequential circuit element. The comparison sub-circuits detect an SEU or glitch if their two signals do not coincide. First and second gating sub-circuits (720, 728) permit the outputs of the comparison sub-circuits to asynchronously set or reset the sequential circuit element (702).

The circuit device includes an output terminal, an output transistor, and a gate voltage control circuit. The output transistor is disposed between the first power supply node and the output terminal. After the input signal (TX) transitions from a first logic level to a second logic level, the gate voltage control circuit causes the gate voltage of the output transistor to change at a first time-voltage change rate. After the gate voltage reaches a first determination voltage, the circuit causes the gate voltage to change at a second time-voltage change rate that is smaller than the first time-voltage change rate. After the gate voltage reaches a second determination voltage, the circuit causes the gate voltage to change at a third time-voltage change rate that is larger than the second time-voltage change rate.

The embodiment of the invention provides a wide dynamic range signal acquisition method and circuit, and the method comprises the steps: a quadrupole is connected with an ion receiving electrode, the ion receiving electrode is connected with a transimpedance amplifier circuit, the transimpedance amplifier circuit is connected with a threshold comparison circuit, the threshold comparison circuit is connected with a D trigger circuit, and the D trigger circuit is connected with a dead time correction circuit. The lower computer FPGA is connected with the D flip-flop circuit; the quadrupole is used for screening ion signal output; the ion receiving electrode is used for converting the ion signal into a current signal; the transimpedance amplifier is used for converting the current signal into a voltage signal; the threshold comparison circuit is used for turning the voltage signal into a logic level; the D flip-flop circuit is used for outputting a target signal level matched with the lower computer FPGA; and the lower computer FPGA is used for receiving the target signal level and counting the signals acquired by the plurality of pulses through the dead time correction circuit. In this way, the phenomenon of counting omission under high-frequency signals is reduced, and the counting accuracy is improved.

The invention provides a direct current motor driving system integrating remote measurement and safety control, and relates to the technical field of motor driving and control, and the system comprises a PWM signal conditioning circuit which receives and conditions a PWM signal and is originally compatible with Pixhawk; the bidirectional polarity control circuit realizes positive and negative rotation of the motor through an optical isolation solid-state relay; the H-bridge driving circuit modulates the current of the motor; the current and voltage sensing circuit is used for generating current and voltage analog signals; the step-down conversion circuit supplies power to the flight controller; the logic level conversion interface is used for realizing 3.3 V / 5V level conversion; the telemetering output circuit outputs the analog signal to a flight controller ADC and transmits the analog signal to a ground station through MAVLink; and the fault protection circuit is used for triggering protection during overcurrent, overvoltage or undervoltage. Through the integrated design, the problems that a traditional driving module is poor in compatibility and lacks telemetering and protection are solved, and plug-and-play, state sensing, safe and reliable integrated driving is achieved.

A duty cycle correction device and a duty cycle correction method thereof are disclosed. A duty cycle adjustment circuit adjusts a duty cycle of an input clock signal to output an output clock signal. An integrator circuit generates an integral signal according to the output clock signal. A correction control circuit periodically controls the duty cycle adjustment circuit to adjust an adjustment amount of the duty cycle according to a change of a logic level of the integral signal.

The application relates to the field of integrated circuit design, in particular to a double-tail dynamic comparator based on a feedback structure, which comprises a preamplifier, a latch and a positive feedback structure which are cascaded with each other; the preamplifier comprises input ends VIP and VIN, output ends fn and fp, and is used for amplifying comparison signals of the input ends; the latch is used for carrying out digital judgment on the amplified comparison signals and latching a judgment logic level; and the positive feedback structure is used for providing a discharge path for fn and fp and increasing a differential voltage between fn and fp. The application introduces the design of the positive feedback structure, adds a new discharge path to the output node of the amplifier to accelerate the pre-amplification speed, and increases the differential voltage between the output nodes fn and fp, so as to reduce the regeneration time of the latch, inhibit the influence of non-ideal factors on the comparator when the input differential signal is small, and accelerate the comparison speed.

A digital hardware circuit and method for performing reduction operations that achieves constant timing depth regardless of input count. The invention replaces conventional sequential binary tree approaches with a parallel matrix comparison architecture where multiple comparator circuits simultaneously compare input signals against each other. Combinatorial logic circuits process comparison outputs to generate dominance signals indicating which input satisfies the reduction criteria, and selection logic outputs the final result. The parallel approach maintains exactly three logic levels regardless of number of processing inputs, enabling significantly higher clock frequencies than conventional methods whose timing depth increases logarithmically with input count. Applications include matrix multiplication engines, floating-point arithmetic units, and artificial intelligence accelerators where reduction operations for maximum / minimum finding, normalization, and other computations are performed millions of times per second. The constant timing depth enables operation at frequencies exceeding 1 GHz while providing scalable performance.

A measurement apparatus for measuring signals from a DUT includes a time domain receiver for receiving from the DUT a DUT time domain output signal in a time domain and providing a time domain input signal; a logic domain receiver for receiving from the DUT a DUT logic domain output signal including logic levels over time; an LO for generating an LO signal; a mixer for receiving from the DUT a DUT frequency domain output signal in a frequency domain and for mixing the DUT frequency domain output signal and the LO signal to provide a frequency downconverted frequency domain signal; a frequency domain receiver for receiving the frequency downconverted frequency domain signal and providing a frequency domain input signal; and a controller for determining control signals in response to the logic levels from the DUT logic domain output signal for controlling at least one operation of the LO.

The invention provides an intelligent low-side power switch circuit applied to a vehicle, the intelligent low-side power switch circuit is provided with a power supply interface, a ground interface, a switch interface and an output interface, and the intelligent low-side power switch circuit comprises a control module which is connected with the switch interface and the power supply interface; the field effect transistor is provided with a grid electrode, a drain electrode and a source electrode, the grid electrode is connected with the power interface and the switch interface through the control module, the drain electrode is connected with the output interface, and the source electrode is connected with the ground interface; wherein the control module controls the switch-on and switch-off of the field effect transistor according to a logic level signal of the switch interface so as to control the connection state of the output interface and the ground interface, and the protection and detection functions are realized through the control module. The technical problems that an existing large-current low-side control scheme generally adopts a mode of a special low-side driving chip and a metal oxide semiconductor field effect transistor (MOSFET), the scheme is extremely complex, the cost is high, and large-scale popularization and application are difficult are solved.

A method and an apparatus for memory testing are provided. The method includes following steps: after multiple dies are idle for a first time, performing a first stage test on the dies, and setting multiple flags corresponding to the dies that fail the first stage test to a first logic level; after the dies are idle for a second time, performing a second stage test on the dies, and regarding the dies that pass the second stage test and have the corresponding flags set to the first logic level as suspected good dies and keeping the suspected good dies idle; and after the suspected good dies are idle for a third time, performing a third stage test on the suspected good dies.

The invention discloses an analog-to-digital converter with a voltage monitoring function. The analog-to-digital converter comprises a voltage comparator and a control logic circuit. The control logic circuit is used for switching the working modes of the analog-to-digital converter, and the working modes comprise a data acquisition mode and a real-time monitoring mode. When working in a data acquisition mode, the voltage comparator is used for converting an analog electric signal input into the analog-to-digital converter into a discrete digital logic level signal so as to output a digital signal according to the digital logic level signal. When working in a real-time monitoring mode, the voltage comparator is used for comparing an input analog electric signal with a threshold setting electric signal and outputting a monitoring result signal obtained through comparison. By means of the working mode switching mode, the voltage comparator of the analog-to-digital converter is fully applied, so that the circuit complexity of a signal acquisition chip in a scene where the analog signal subjected to analog-to-digital conversion is limited by a voltage value is simplified, and the cost is reduced.

The present disclosure relates to a semiconductor device and a method of operating a semiconductor device. The semiconductor device includes a charge pump circuit configured to generate an output voltage by pumping an input voltage according to a first master clock and a second master clock; a voltage detection circuit configured to generate a comparison signal by comparing the output voltage with a reference voltage; and a drive control circuit configured to: selectively invert the first external clock and the second external clock at a start time of an active period of the comparison signal to receive the inverted clocks as first internal clocks and second internal clocks; generate the first master clock and the second master clock according to the first internal clocks and the second internal clocks while controlling a transition order such that the second master clock transitions after the first master clock transitions during the active period of the comparison signal; and store logic levels of the first master clock and the second master clock as a first preliminary clock and a second preliminary clock, respectively, at an end time of the active period of the comparison signal.

The application provides a multi-agent running management and control method and an electronic device. The method comprises the following steps: receiving a user request, and determining a current task identifier, a target agent and a running resource bound to the target agent according to the user request; constructing a target running domain at a logic level; before calling the target agent, constructing a shadow running domain at a physical level, verifying whether the loaded resource entity in the running environment is consistent with the resource data defined by the target running domain; generating a resource binding proof, verifying whether the helper identifier transmitted by the business side has the binding relationship declared in the agent registry between the actually loaded agent and the resource thereof; if the verification passes, the target agent is called to execute model reasoning. The problem that the execution environment is difficult to uniformly represent and verify in multi-user, multi-session, multi-thread and multi-agent concurrent service is solved, and the stability and response effect of multi-agent running are improved.

A CAN bus transmitter has inputs for receiving transmitted data signals, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter includes multiple CAN driver circuits with inputs coupled to their common CANH and CANL outputs and connected to the CAN bus via delay circuits. Matching of the Cgs capacitors between devices in the CANH and CANL branches provides substantially synchronized changes in the CANH and CANL output logic levels as the input logic levels change. The variable delay of this input logic level change for each of the multiple CAN driver circuits reduces the transmission of unwanted signals from the CAN bus.

This application provides a cascaded reverse conduction control circuit and a power converter, belonging to the field of electronic circuit technology. The pulse width modulation signal is transmitted to the action module via a first driving module. The output terminal of the action module is connected to the gate of a first high-voltage depletion-type transistor (HMT). The sampling terminal of the action module is connected to the first terminal of a detection module. The second terminal of the detection module is connected to the drain of the first HMT. The third terminal of the detection module and the action module are both connected to the source of a low-voltage enhancement-type transistor (LVMT). Logic levels are transmitted to the gate of the LVMT via a second driving module. The detection module detects the voltage and current directions of the cascaded structure. Driven by the detection module, the action module controls the first HMT to conduct. This application simplifies the reverse conduction control strategy for gallium nitride (GaN) power devices and reduces the cost of reverse conduction control for GaN power devices.

According to the LED control circuit, isolation of a control signal and a power signal is achieved through an optical coupler, the safety and stability of the circuit are improved, when the control signal is at a low level, an LED and a photo-transistor in the optical coupler are conducted, so that a grid electrode of an MOSFET obtains a driving voltage to be conducted, finally current is allowed to pass through the LED, the LED is lightened, and the LED is prevented from being damaged. The technical problems that a direct logic level control method may have potential safety hazards in a high-voltage or high-current environment, and direct connection between different power supplies may introduce noise and interference to affect the stability and reliability of the circuit are solved.

Disclosed is a spike neural network circuit including an axon circuit that generates a first input spike signal, a conversion table that converts a first fire probability of a first neuron corresponding to the first input spike signal into a first threshold value, and a probabilistic operator. The probabilistic operator includes a random number generator that generates a random number value based on an event that the first input spike signal is at a first logic level, a random number comparator that generates a first comparison signal by comparing the first threshold value with the random number value, and a spike generator that generates an output spike signal corresponding to the first neuron based on an event that the first comparison signal is at the first logic level.

This invention discloses a bidirectional power supply fault early warning method based on a hardware protection mechanism, belonging to the field of fault early warning technology. The method includes the following steps: acquiring parameters and signals; calculating the approximation sequence; identifying switching intervals; extracting and shielding micro-triggers; weighted accumulation to obtain an exponent; and threshold comparison for early warning. This invention acquires real-time operating electrical parameters and logic level signals, generates a protection approximation sequence, and identifies energy flow switching intervals. When the logic level signal is not locked and flips, micro-trigger features are extracted and time-domain shielded to obtain an effective micro-trigger sequence. The protection approximation sequence is then weighted and accumulated to obtain a hardware stress residual exponent. Finally, fault early warning is achieved by comparing with a safety threshold, realizing a shift from post-event protection to pre-event early warning. This solves the problem in existing technologies where hardware protection circuits can only cut off the circuit after a fault occurs, failing to provide early warning during device aging or performance degradation.

A fault detection circuit provides hardware-based fault detection to a system that includes power electronics. The fault detection circuit includes sensor interfaces and scaling amplifiers to scale sensor outputs for comparison with reference voltages at the respective comparators. The logic levels at the comparator outputs are received at logic gate circuits and used to determine a master logic level, which is used to drive a gate driver, thus directing a fault detection response through the fault detection circuit. The fault detection circuit can be included in a motor control device, such as a hydraulic power unit motor driver. Figure for abstract: [Fig 1]