274 results about "Logic level" patented technology

The invention relates to the technical field of digital-analog hybrid integrated circuit design, and particularly provides a FlexRay bus receiver with low noise and wide common-mode input range, which is characterized in that a common-mode voltage division module receives a differential signal output by a bus and carries out voltage division, and then a pre-amplification module carries out amplitude limiting amplification on the signal after voltage division; the hysteresis comparator module generates threshold hysteresis and generates a logic level signal based on the signal after amplitude limiting amplification, and the digital logic receiving module receives and processes the logic level signal, generates a receiving data signal and transmits the receiving data signal to an external controller. According to the invention, the differential signal pair received on the FlexRay bus is subjected to voltage division and amplitude limiting amplification, so that a wider common-mode input range is provided, the problem of large ground potential difference is solved, and the capability of suppressing common-mode noise and the communication stability are improved. Meanwhile, the hysteresis comparator module suppresses noise false triggering by generating threshold hysteresis, and the anti-noise capability of the receiver is remarkably improved.

A memory device includes a syndrome calculator configured to generate an error location signal based on first data and an error correction code; an error corrector configured to generate second data by correcting an error in the first data according to the error location signal; and a data mask (DM) calculation circuit configured to generate a DM signal according to logic high bits of the first data and change a logic level of the DM signal according to at least one of an increase signal and a decrease signal, by activating the increase signal when an error bit is detected in logic low bits of the first data and activating the decrease signal when the error bit is detected in the logic high bits of the first data, based on the error location signal.

The invention relates to the technical field of automatic control theory application and data center thermal management, and discloses a data center emergency refrigeration control method based on state space model prediction, which comprises the following steps: establishing a thermodynamic cycle state space equation; the refrigeration flow set value change rate and the water return side pressure change amount are obtained, and the dynamic heat exchange sensitivity is determined; monitoring feedback current characteristics of the driving unit, inverting cooling path resistance distribution and updating gain matrix elements; calculating a state prediction information sequence according to the temperature vector prediction deviation, and adjusting a time domain step length; the dynamic heat exchange sensitivity is introduced into prediction logic, controlled variable dynamic pressure retardation is compensated, an emergency refrigeration frequency control instruction is output, fluid fluctuation is converted into sensitivity compensation of a logic level, non-linear dynamic pressure damping of the emergency working condition is effectively impacted, the problems of control overshoot and logic instability caused by physical lag are solved, and the reliability of the system is improved. And the refrigeration response precision at the emergency conversion moment is improved.

The invention is suitable for the technical field of processors, and particularly relates to a speculative wake-up-based data forwarding optimization system and method and related equipment. According to the method and the device, the data forwarding flag bit and the data forwarding pipeline number are set for the to-be-executed instruction, and whether the to-be-executed instruction needs to be subjected to data forwarding or not is judged according to the data forwarding flag bit; if yes, the instruction to be executed needs to obtain the corresponding source operand from the front instruction, data forwarding needs to be carried out, and the source operand is read from the corresponding pipeline of the assembly line according to the serial number of the data forwarding pipeline; and if the data forward flag bit is the second data forward flag bit, the instruction to be executed does not need to acquire the source operand from the front instruction and is directly read from the physical register, so that resource conflicts are reduced. Compared with the prior art, the method has the advantages that the logic level of the data forwarding behavior can be effectively reduced, and the running efficiency and performance of the processor are improved.

The invention relates to the technical field of data storage, and discloses a method for testing the signal quality of an IO interface of a memory module, and the method comprises the steps: verifying the signal integrity of the I / O interface in the memory module based on an eye diagram analysis method; after the signal is verified to be complete, the morphological characteristics of the input eye pattern and the output eye pattern are quantitatively compared, whether morphological characteristic changes occur in the signal transmission process or not is judged, and the morphological characteristic changes at least comprise logic level flipping errors, time sequence recognition errors and signal quality degradation; if the morphological characteristics of the input eye pattern are consistent with the morphological characteristics of the output eye pattern, the test is successful; and if the morphological characteristics of the input eye pattern are inconsistent with the morphological characteristics of the output eye pattern, determining that the test fails. Visual and quantitative verification of signal integrity is realized through eye pattern analysis, multi-dimensional indexes such as voltage, time sequence and noise are covered, and the signal transmission quality is reflected more comprehensively compared with a single parameter test.

The invention discloses a circuit and a method for demodulating current received by an instrument bus host, and relates to the technical field of instruments. The current demodulation circuit comprises an adder, the first input end of the adder is connected with an instrument bus MBUS to receive MBUS signals, the second input end of the adder receives reference voltage signals, and the output end of the adder outputs summing voltage signals; the resistor and capacitor charging and discharging device is connected with the output end of the summator so as to process the summing voltage signal; and the reverse input end of the comparator receives the MBUS signal, and the positive input end of the comparator receives the summing voltage signal processed by the resistor-capacitor charging and discharging device so as to determine the logic level corresponding to the MBUS signal based on the signal level of the output end of the comparator. According to the invention, the problem that the MBUS host receiving circuit cannot be compatible with all MBUS meters is solved.

The invention belongs to the technical field of integrated circuits, and particularly relates to a dynamic comparator suitable for a low-voltage high-speed analog-to-digital converter, the dynamic comparator adopts a three-stage latch circuit structure to realize rapid comparison of weak input signals so as to generate corresponding digital signals, and the method specifically comprises the following steps of: in a pre-amplification stage, pre-amplification is carried out; the positive feedback effect of the cross-coupled transistor pair is utilized to efficiently convert a tiny input voltage difference (lt; 10mV) into a recognizable voltage difference, and then through two-stage regeneration of the main latch module and the auxiliary latch module, a logic level is quickly output to complete quantization judgment. The auxiliary latch stage is additionally arranged on the basis of a traditional cross coupling latch circuit, the working speed of the comparator is effectively increased under the condition that only small area overhead is introduced, and the probability that the dynamic comparator has a metastable state is greatly reduced.

The invention discloses a configurable dynamic vehicle-mounted dimming method and system for tunnel lamp illumination, and the method comprises the following steps: dividing a target tunnel into a plurality of dimming sections, further dividing a dimming loop in each dimming section, and carrying out the deployment of an illumination unit and an incoming vehicle detector based on a division result; a dimming counting interval of a logic level is constructed, a dynamic mapping relation is established between the dimming counting interval and a dimming loop of a physical level, and the dimming counting interval is a minimum logic unit used for vehicle tracking and counting; an independent vehicle counter is configured for each dimming counting interval, and a counting updating rule is set; configuring a security policy for counting function activation and dimming execution; and responding to the triggering of the coming vehicle detector, updating the vehicle count in the dimming counting interval in real time, and adjusting the brightness of the dimming loop based on the security policy. Compared with the prior art, the configurable dynamic vehicle-mounted dimming method and the configurable dynamic vehicle-mounted dimming system have remarkable progress in the aspects of energy conservation and safety.

According to an embodiment, a bootstrap drive circuit for driving a bootstrap switch in a DC-DC converter is proposed. The bootstrap drive circuit includes a non-overlapping circuit, a first and a second capacitor, and a first and a second n-channel transistor. The non-overlapping circuit is configured to receive an input signal, the input signal being a function of a pulse width modulated (PWM) signal, wherein the input signal and the PWM signal are characterized by a first logic level, generate a first control signal from the input signal at a first output terminal of the non-overlapping circuit, the first control signal having the first logic level, and generate a second control signal from the input signal at a second output terminal of the non-overlapping circuit, the second control signal being characterized by a second logic level different from the first logic level.

The invention discloses master-slave integrated MVB (Multifunction Vehicle Bus) simulation test equipment based on an FPGA (Field Programmable Gate Array) and an MCU (Microprogrammed Control Unit). An FPGA chip, an MCU chip and an MVB communication physical layer circuit are arranged in an equipment body; an MVB master logic unit and an MVB slave logic unit are integrated in the FPGA chip; the MCU chip is in communication connection with the main logic unit and the MVB slave logic unit; and the MVB communication physical layer circuit is used for realizing conversion between a logic level signal output by the FPGA chip and an EMD signal of an MVB bus. The MVB main logic control unit sends an MVB main frame according to the port traversal table stored in the port table unit; and after the MVB slave logic data and state control unit obtains the sending control right of the MVB sending control unit, the MVB slave logic unit sends or receives data with the MVB bus. The device number and cable connection are reduced, the deployment time of the test system is shortened, and the single test duration is shortened.

An event notification method and apparatus, a device, a computer program product, and a storage medium. A binding mechanism between queue pairs and completion queues involved in an event notification mechanism of a second protocol is modified, and it is proposed that the binding between queue pairs and completion queues be performed in accordance with the jurisdiction relationship between network connections and listening instances in a first protocol. Listening instances invoked in an event notification mechanism of the first protocol are also partially modified at the user-space logic level, and it is proposed that completion queues be registered within the listening scope of corresponding listening instances. A listening instance determines, by monitoring completion queue entries in a completion queue, whether a readiness event has occurred on a network connection established according to the first protocol. Then, on the basis of these completion queue entries, an event notification result conforming to the first protocol is generated and returned to an application. Accordingly, compatibility of the event notification mechanisms between the two protocols can be achieved without requiring modification of the program code of the application.

A memory structure including a three-dimensional NOR memory string and a method of operation are disclosed. In some embodiments, the memory device performs partial polarization to provide a reference signal for read operations. The reference signal implements a third logic state distinguishable from the first and second logic stages in the ferroelectric memory transistor, e.g., associated with a program state and an erase state. In another embodiment, the memory device provides a reference signal for a read operation by averaging a first signal associated with a program state of the ferroelectric memory transistor and a second signal associated with an erase state. In some embodiments, the memory device implements one or more partially polarized states to provide more than one logical bit stored in each memory cell to multi-level memory cells.

The utility model discloses a track circuit reader test interface switching device, and relates to the field of track circuit equipment. The utility model aims to solve the problem that the traffic safety is influenced because the number of test items of TCR equipment is small. According to the track circuit reader test interface switching device of the utility model, a CAN signal input / output end of a CAN isolation transmit-receive module is used for being connected with a CAN bus of a DB15 connector, and a logic level input / output end of the CAN isolation transmit-receive module is connected with a logic level input / output end of an MCU. The parallel port information input and output end of the MCU is connected with the parallel port information input and output end of the optocoupler, and the optocoupler outputs or receives signals through the external input and output signal test interface module.

The invention provides a circuit and method for setting a PWM duty ratio and a power management system. The circuit comprises a comparison module, a logic control module, a digital logic module, a voltage selection module and a PWM generation module. The comparison module comprises a demand voltage generation unit and a comparison unit. The demand voltage generation unit generates demand voltage in a certain scene, the comparison unit compares the demand voltage with voltage provided by the voltage selection module, the logic control module analyzes the comparison result to generate a digital signal, and the digital logic module determines the range of the demand voltage. The logic level signal corresponding to the required voltage is obtained and sent to the PWM generation module, so that the PWM generation module sets the duty ratio, and therefore, the interference of power supply variation and signal noise can be reduced, the control precision of the duty ratio can be improved, the setting of different required duty ratios can be realized by adjusting the external resistor, the design is simple, and the integration level is high.

The invention relates to the technical field of data acquisition, in particular to a data acquisition method and system with a reusable differential signal interface. The device comprises a bottom plate and a data acquisition card used for acquiring analog signals, uniform interfaces are adopted and comprise a plurality of differential signal pairs used for transmitting commands, a plurality of differential signal pairs used for transmitting data and a plurality of differential signal pairs used for transmitting clocks. According to the reusable differential signal interface disclosed by the invention, the signal integrity and reliability of long-distance transmission of signals on a bottom plate are improved through differential signals, a system can stably work in a severe electromagnetic environment, and the reusable interface can be in mixed plug-in connection with different data acquisition cards of voltage, current, strain, temperature and the like according to requirements. According to the method, step-by-step power-on is adopted, identity recognition and software configuration are only performed on a digital logic level after insertion, and simulation power supply is performed after recognition is passed, so that chain risks such as power supply impact, bus locking and even system downtime caused by insertion faults or incompatible modules are eliminated.

The application discloses an industrial electronic lock, which comprises a front panel, a main body and a back panel; the front panel is provided with a magnet and an input contact; the main body comprises a CPU system, an EEPROM storage chip, a FLASH chip, a relay module, a logic level module and a communication module; the back panel comprises a power module and a function output module; the input contact, the EEPROM storage chip, the FLASH chip, the relay module, the logic level module and the communication module are connected with the CPU system respectively; the relay module, the logic level module and the communication module are connected with the function output module respectively; and the power module provides power supply for the CPU system, the EEPROM storage chip, the FLASH chip, the relay module, the logic level module and the communication module. The application can realize personnel identity identification, permission management and record operation behavior, and ensures the safety of an industrial site.

The light-emitting drive circuit still needed further consideration regarding the control of the light-emitting elements when the system is stopped. [Solution] The light-emitting drive device comprises a bypass circuit and a bypass control circuit. The bypass circuit is configured to individually switch each of the multiple light-emitting elements connected in series between an inflow state and a retracted state. The bypass control circuit controls the bypass circuit so that when the enable signal is at a first logic level, it flows the drive current to each light-emitting element individually or retracts it, and when the enable signal is at a second logic level, it retracts the drive current from all light-emitting elements until the drive current falls below a predetermined current value.

The invention relates to the technical field of electronics, and discloses a dead time setting circuit, a PCB and a chip, and the dead time setting circuit comprises a high-side input unit, a low-side input unit and a shaping unit; the high-side input unit, the low-side input unit and the shaping unit are electrically connected with one another; the high-side input unit and the low-side input unit carry out delay and logic operation processing on input signals, the input signals can be integrated and optimized in the logic level while dead zone time is set, and a foundation is laid for generating stable pre-drive signals; and then, the shaping unit shapes the pre-drive signal obtained after processing of the two units, so that the instantaneous error level in the pre-drive signal can be effectively eliminated, a stable drive signal is output, and the stability of the drive signal is ensured.

A semiconductor device includes a receiver and a controller. The receiver is configured to sample a data signal and a track signal received through data lanes in response to rising edges of first and second internal clock signal pairs. The controller is configured to detect a skew status between the track signal and the first and second internal clock signal pairs, based on the number of times a specific logic level of the track signal is sampled in synchronization with each of the first and second internal clock signal pairs, and provide the receiver with a clock shift signal for calibrating a clock skew, based on the skew status.

The signal transmission device has room for further consideration regarding drive control of the switch to be driven.SOLUTION: The signal transmission device 200X includes a transmission circuit S2 for outputting a control signal 350x, a reception circuit 400x, and an insulating circuit 500. The receiving circuit 400x receives an external signal S1x. The receiving circuit 400x drives the drive object switch S1x based on the control signal S2 in a state in which the external signal SW10 is at a first logic level, and drives and controls the drive object switch S1x based on the external signal S2 regardless of the control signal S1x in a state in which the external signal SW10 is at a second logic level.SELECTED DRAWING: Figure 11

According to one embodiment, semiconductor integrated circuit includes: first and second pulse generators that generate first and second pulse signals based on a first signal, and third and fourth pulse signal based on a second signal, respectively; first and second inversion buffers that output a third signal based on inputs of the first and third pulse signals, and a fourth signal based on inputs of the second and fourth pulse signal, respectively; wherein, when a logic level of the first or the third pulse signal changes from a first logic level to a second logic level, the first inversion buffer changes a logic level of the third signal, and when a logic level of the second or the fourth pulse signal changes from the first logic level to the second logic level, the second inversion buffer changes a logic level of the fourth signal.

The application discloses a kind of based on dual-channel fusion's time series data class incremental classification method, it is related to time series data class incremental classification technical field, by the original data of several task categories, as a learning stage data, based on dual-channel fusion's time series data class incremental classification model is trained, and the based on dual-channel fusion's time series data class incremental classification model after the previous learning stage training is ended as teacher model, based on dual-channel fusion's time series data class incremental classification model of current learning stage is trained as student model, can explicitly retain prior knowledge and overcome catastrophic forgetting, and by the use of joint optimization loss function, using the mixed distillation strategy of fusion feature level and logic level knowledge distillation, more structured, more robust feature distribution is formed between incremental tasks, so that it has stronger adaptability to cross-task distribution drift.

The invention discloses a heat supply pipe network inspection decision method fusing multi-agent cooperation and digital twinning, and the method comprises the steps: building a heat supply pipe network digital twinning model through the cooperative interaction of a model-level agent, an equipment-level agent and a logic-level agent; performing pipe network anomaly analysis through a digital twinborn model, and generating a temporary pipe network inspection task; the method comprises the following steps: receiving a total inspection task demand including a pipe network temporary inspection task and a preset pipe network conventional inspection task through an inspection management agent, and extracting inspection key parameters; splitting and allocating a total task demand through an inspection task planning agent according to the inspection key parameters and the resource capability characteristics of each inspection device, so that the inspection device obtains an allocated inspection sub-task plan; outputting a scheduling action sequence of executing the inspection subtasks by each inspection device through the inspection task scheduling agent, and issuing the scheduling action sequence to the inspection device; and generating a heat supply pipe network inspection report through the inspection task execution feedback agent, and feeding back the heat supply pipe network inspection report.

The invention discloses a substation interface configuration operation and maintenance method and system based on functional identity recognition, and belongs to the technical field of substation operation and maintenance. According to the invention, the anti-misplug guide keys are configured for the in-cabinet interface and the out-cabinet interface through the in-cabinet interface configuration data and the out-cabinet interface configuration data, so that misplug and misplug between the interfaces on an object quantity connection layer are avoided; by generating a function identity identification code and constructing a function mapping database, digital management of function logic configuration between interfaces is realized, and the complexity and error rate of manual parameter configuration are reduced; simple and efficient substation interface configuration is realized; then the to-be-overhauled interface is identified through the substation operation and maintenance requirement, the function mapping database and the function identity identification code, the to-be-overhauled interface needing to be isolated can be accurately identified from the interface function logic level, the risk of isolation leakage or misoperation is avoided, efficient and accurate substation interface operation and maintenance are achieved, and the operation efficiency is improved. And the efficiency and the accuracy of substation interface configuration operation and maintenance are improved.

The invention provides an active suspension system, a control method and a storage medium, the active suspension system is provided with an edge computing controller, the edge computing controller comprises a master controller, a slave controller, a monitoring unit and an instruction switching unit, and the master controller and the slave controller are heterogeneous on the hardware level, so that the risk of common hardware defects is avoided, and the reliability of the active suspension system is improved. Besides, the master controller and the slave controller are further configured to run different control algorithms and output control instructions at the same time, so that on one hand, faults triggered by same software vulnerabilities can be avoided, and on the other hand, the control instructions output by the controller without faults can be seamlessly switched to through the instruction switching unit when faults occur. Therefore, the problems that a single-point fault risk is faced by a single-controller architecture, architecture schemes of isomorphic double controllers possibly fail at the same time on the software logic level, and reliable switching is difficult to complete at the moment that a fault occurs can be solved, and the safety is improved.

A fault detection circuit provides hardware-based fault detection to a system including power electronics. The fault detection circuit includes sensor interfaces and scaling amplifiers to scale sensor outputs for comparison to reference voltages at respective comparators. Logic levels output from the comparators are received at logic gate circuits and used to determine a master logic level that is used to control a gate driver, thereby directing response to the detection of a fault by the fault detection circuit. The fault detection circuit can be included in a motor controller such as a motor controller of a hydraulic power pack.

The disclosure provides a circuit (700) and method for correcting single event upsets, SEUs, or glitches in electronic circuits. The circuit includes rising and falling edge detection sub-circuits (710, 712) connected to a sequential circuit element output (706) which generate signals if the sequential circuit element output changes logic levels, and comparison sub-circuits (716, 724) which compare the signal from the edge detection sub-circuits with a signal generated on an active edge of a clock signal of the sequential circuit element. The comparison sub-circuits detect an SEU or glitch if their two signals do not coincide. First and second gating sub-circuits (720, 728) permit the outputs of the comparison sub-circuits to asynchronously set or reset the sequential circuit element (702).

The circuit device includes an output terminal, an output transistor, and a gate voltage control circuit. The output transistor is disposed between the first power supply node and the output terminal. After the input signal (TX) transitions from a first logic level to a second logic level, the gate voltage control circuit causes the gate voltage of the output transistor to change at a first time-voltage change rate. After the gate voltage reaches a first determination voltage, the circuit causes the gate voltage to change at a second time-voltage change rate that is smaller than the first time-voltage change rate. After the gate voltage reaches a second determination voltage, the circuit causes the gate voltage to change at a third time-voltage change rate that is larger than the second time-voltage change rate.

The embodiment of the invention provides a wide dynamic range signal acquisition method and circuit, and the method comprises the steps: a quadrupole is connected with an ion receiving electrode, the ion receiving electrode is connected with a transimpedance amplifier circuit, the transimpedance amplifier circuit is connected with a threshold comparison circuit, the threshold comparison circuit is connected with a D trigger circuit, and the D trigger circuit is connected with a dead time correction circuit. The lower computer FPGA is connected with the D flip-flop circuit; the quadrupole is used for screening ion signal output; the ion receiving electrode is used for converting the ion signal into a current signal; the transimpedance amplifier is used for converting the current signal into a voltage signal; the threshold comparison circuit is used for turning the voltage signal into a logic level; the D flip-flop circuit is used for outputting a target signal level matched with the lower computer FPGA; and the lower computer FPGA is used for receiving the target signal level and counting the signals acquired by the plurality of pulses through the dead time correction circuit. In this way, the phenomenon of counting omission under high-frequency signals is reduced, and the counting accuracy is improved.

Disclosed is a semiconductor integrated circuit device including: a switching transistor; a terminal to receive a control signal from outside; and a control circuit that controls the switching transistor based on the control signal. The control circuit includes: a reference voltage source that generates a reference voltage from the DC voltage; a differential amplifier to receive the reference voltage and a voltage of the voltage output terminal, and output a voltage applied to a control terminal of the switching transistor; and a logic circuit that generates a signal to control an operation state of the differential amplifier based on the control signal. According to an output signal of the logic circuit, the differential amplifier controls the switching transistor to be on in response to the control signal being a first logic level, and to be off in response to the control signal being a second logic level.