399 results about "Logic level" patented technology

An amplification circuit is configured to differentially amplify an input signal and a reference voltage to generate an output signal when a clock signal has a first logic level. The amplification circuit is configured to precharge the output signal when the clock signal has a second logic level. The amplification circuit is configured to adjust a current driving force that precharges the output signal based on the reference voltage.

The invention discloses a 23T4M anti-radiation TCAM storage unit circuit which comprises a pre-charging module, an RH reading circuit module, a programmable logic module, a reconfigurable magnetic tunnel junction storage module, a discharging module and an output module. In the RH reading circuit module, the grid electrode of a transistor N7 is connected with the drain electrode of a transistor N8, the grid electrode of the transistor N8 is connected with the drain electrode of the transistor N7, a cross coupling structure is formed, a node S0 and a node S1 are controlled by a node Q and a node QB, meanwhile, the node S0 and the node S1 control the charging and discharging paths of the node Q and the node QB respectively, and after any node is overturned by high-energy particles, the charging and discharging paths of the node Q and the node QB are controlled by the node S0 and the node S1. All the nodes are maintained or charged to recover to the original logic level. According to the method, data upset at a single sensitive node can be completely resisted, and meanwhile, the search error rate of the TCAM is improved.

The invention relates to the technical field of digital-analog hybrid integrated circuit design, and particularly provides a FlexRay bus receiver with low noise and wide common-mode input range, which is characterized in that a common-mode voltage division module receives a differential signal output by a bus and carries out voltage division, and then a pre-amplification module carries out amplitude limiting amplification on the signal after voltage division; the hysteresis comparator module generates threshold hysteresis and generates a logic level signal based on the signal after amplitude limiting amplification, and the digital logic receiving module receives and processes the logic level signal, generates a receiving data signal and transmits the receiving data signal to an external controller. According to the invention, the differential signal pair received on the FlexRay bus is subjected to voltage division and amplitude limiting amplification, so that a wider common-mode input range is provided, the problem of large ground potential difference is solved, and the capability of suppressing common-mode noise and the communication stability are improved. Meanwhile, the hysteresis comparator module suppresses noise false triggering by generating threshold hysteresis, and the anti-noise capability of the receiver is remarkably improved.

In the present disclosure, a buffer outputs a gate drive signal indicating the same logic level as an element control signal, and an inverting buffer outputs a base drive signal indicating the opposite logic level to the element control signal. The resistance is interposed between the output of the buffer and the gate of an IGBT. A PNP bipolar transistor has its emitter connected to the gate of the IGBT and its collector connected to reference potential. A diode is interposed between the output of the buffer and a base of the PNP bipolar transistor. An output of the inverting buffer is connected to the base of the PNP bipolar transistor through a resistance.

A memory device includes a syndrome calculator configured to generate an error location signal based on first data and an error correction code; an error corrector configured to generate second data by correcting an error in the first data according to the error location signal; and a data mask (DM) calculation circuit configured to generate a DM signal according to logic high bits of the first data and change a logic level of the DM signal according to at least one of an increase signal and a decrease signal, by activating the increase signal when an error bit is detected in logic low bits of the first data and activating the decrease signal when the error bit is detected in the logic high bits of the first data, based on the error location signal.

The invention provides a multichannel HART (Highway Addressable Remote Transducer) dynamic communication system. The multichannel HART dynamic communication system comprises a modulation circuit and a demodulation circuit, the demodulation circuit of each channel comprises a hysteresis Schmitt trigger module and an analog quantity acquisition module which are parallel, the hysteresis Schmitt trigger module is configured to separate HART signals to obtain FSK signals in the HART signals, and the analog quantity acquisition module is configured to acquire the FSK signals in the HART signals. The FSK signal is converted into a digital pulse signal through the hysteresis Schmitt trigger and then is output to the controller, and the logic level of the digital pulse signal corresponds to the first frequency and the second frequency of the FSK signal; and the analog quantity acquisition module is configured to separate the HART signal to obtain a 4-20mA direct current component in the HART signal, convert the 4-20mA direct current component into a digital signal and output the digital signal to the controller.

Methods, systems, and devices for establishing memory system read window budget (RWB) are described. A memory system may receive a command from a host system requesting an RWB for an edge of a distribution of a logic level of a set of logic levels. The memory system may determine an expected pattern of data corresponding to a set of memory cells and may store the expected pattern in memory. The memory system may perform a voltage sweep operation, including setting a read voltage to different levels across the edge for reading the set of memory cells. The memory system may count a quantity of expected bits resulting from a logic function of the expected pattern and the read data for each level, and may output a voltage offset corresponding to level at which a difference of the quantity of expected bits and an initial quantity satisfies a threshold.

The invention relates to the technical field of automatic control theory application and data center thermal management, and discloses a data center emergency refrigeration control method based on state space model prediction, which comprises the following steps: establishing a thermodynamic cycle state space equation; the refrigeration flow set value change rate and the water return side pressure change amount are obtained, and the dynamic heat exchange sensitivity is determined; monitoring feedback current characteristics of the driving unit, inverting cooling path resistance distribution and updating gain matrix elements; calculating a state prediction information sequence according to the temperature vector prediction deviation, and adjusting a time domain step length; the dynamic heat exchange sensitivity is introduced into prediction logic, controlled variable dynamic pressure retardation is compensated, an emergency refrigeration frequency control instruction is output, fluid fluctuation is converted into sensitivity compensation of a logic level, non-linear dynamic pressure damping of the emergency working condition is effectively impacted, the problems of control overshoot and logic instability caused by physical lag are solved, and the reliability of the system is improved. And the refrigeration response precision at the emergency conversion moment is improved.

A processing device may add at least one logic level metric count module to a circuit design, load the circuit design into an emulation system, and apply an emulation workload to the emulation system to which the circuit design is loaded. The processing device may then obtain at least one logic level metric count from the at least one logic level metric count module, the at least one logic level metric count associated with at least a portion of the emulation workload, and present at least one power utilization estimate for the circuit design, where the at least one power utilization estimate for the circuit design is based upon the at least one logic level metric count.

The invention is suitable for the technical field of processors, and particularly relates to a speculative wake-up-based data forwarding optimization system and method and related equipment. According to the method and the device, the data forwarding flag bit and the data forwarding pipeline number are set for the to-be-executed instruction, and whether the to-be-executed instruction needs to be subjected to data forwarding or not is judged according to the data forwarding flag bit; if yes, the instruction to be executed needs to obtain the corresponding source operand from the front instruction, data forwarding needs to be carried out, and the source operand is read from the corresponding pipeline of the assembly line according to the serial number of the data forwarding pipeline; and if the data forward flag bit is the second data forward flag bit, the instruction to be executed does not need to acquire the source operand from the front instruction and is directly read from the physical register, so that resource conflicts are reduced. Compared with the prior art, the method has the advantages that the logic level of the data forwarding behavior can be effectively reduced, and the running efficiency and performance of the processor are improved.

The invention relates to the technical field of data storage, and discloses a method for testing the signal quality of an IO interface of a memory module, and the method comprises the steps: verifying the signal integrity of the I / O interface in the memory module based on an eye diagram analysis method; after the signal is verified to be complete, the morphological characteristics of the input eye pattern and the output eye pattern are quantitatively compared, whether morphological characteristic changes occur in the signal transmission process or not is judged, and the morphological characteristic changes at least comprise logic level flipping errors, time sequence recognition errors and signal quality degradation; if the morphological characteristics of the input eye pattern are consistent with the morphological characteristics of the output eye pattern, the test is successful; and if the morphological characteristics of the input eye pattern are inconsistent with the morphological characteristics of the output eye pattern, determining that the test fails. Visual and quantitative verification of signal integrity is realized through eye pattern analysis, multi-dimensional indexes such as voltage, time sequence and noise are covered, and the signal transmission quality is reflected more comprehensively compared with a single parameter test.

The invention discloses a circuit and a method for demodulating current received by an instrument bus host, and relates to the technical field of instruments. The current demodulation circuit comprises an adder, the first input end of the adder is connected with an instrument bus MBUS to receive MBUS signals, the second input end of the adder receives reference voltage signals, and the output end of the adder outputs summing voltage signals; the resistor and capacitor charging and discharging device is connected with the output end of the summator so as to process the summing voltage signal; and the reverse input end of the comparator receives the MBUS signal, and the positive input end of the comparator receives the summing voltage signal processed by the resistor-capacitor charging and discharging device so as to determine the logic level corresponding to the MBUS signal based on the signal level of the output end of the comparator. According to the invention, the problem that the MBUS host receiving circuit cannot be compatible with all MBUS meters is solved.

The invention belongs to the technical field of integrated circuits, and particularly relates to a dynamic comparator suitable for a low-voltage high-speed analog-to-digital converter, the dynamic comparator adopts a three-stage latch circuit structure to realize rapid comparison of weak input signals so as to generate corresponding digital signals, and the method specifically comprises the following steps of: in a pre-amplification stage, pre-amplification is carried out; the positive feedback effect of the cross-coupled transistor pair is utilized to efficiently convert a tiny input voltage difference (lt; 10mV) into a recognizable voltage difference, and then through two-stage regeneration of the main latch module and the auxiliary latch module, a logic level is quickly output to complete quantization judgment. The auxiliary latch stage is additionally arranged on the basis of a traditional cross coupling latch circuit, the working speed of the comparator is effectively increased under the condition that only small area overhead is introduced, and the probability that the dynamic comparator has a metastable state is greatly reduced.

The invention discloses a configurable dynamic vehicle-mounted dimming method and system for tunnel lamp illumination, and the method comprises the following steps: dividing a target tunnel into a plurality of dimming sections, further dividing a dimming loop in each dimming section, and carrying out the deployment of an illumination unit and an incoming vehicle detector based on a division result; a dimming counting interval of a logic level is constructed, a dynamic mapping relation is established between the dimming counting interval and a dimming loop of a physical level, and the dimming counting interval is a minimum logic unit used for vehicle tracking and counting; an independent vehicle counter is configured for each dimming counting interval, and a counting updating rule is set; configuring a security policy for counting function activation and dimming execution; and responding to the triggering of the coming vehicle detector, updating the vehicle count in the dimming counting interval in real time, and adjusting the brightness of the dimming loop based on the security policy. Compared with the prior art, the configurable dynamic vehicle-mounted dimming method and the configurable dynamic vehicle-mounted dimming system have remarkable progress in the aspects of energy conservation and safety.

The invention discloses an unmanned aerial vehicle chip sensitive data access control method based on a trusted execution environment, and relates to the technical field of unmanned aerial vehicle security. If data encryption is carried out, real-time confusion processing is carried out on power consumption, electromagnetic signals and execution time of the unmanned aerial vehicle chip; the trusted execution environment isolates a processing space of sensitive data from a logic level to prevent unauthorized access; the real-time confusion processing performs dynamic interference aiming at the core physical characteristics of the side channel attack, so that an attacker cannot derive an encryption key or algorithm logic through a physical signal of a monitoring chip; according to the method, the chip presents highly unpredictable physical characteristics in the encryption process through the synergistic effect of the power consumption, the electromagnetic signal and the execution time, the side channel attack difficulty is remarkably improved, and multi-level guarantee is provided for safe processing of sensitive data of the unmanned aerial vehicle.

According to an embodiment, a bootstrap drive circuit for driving a bootstrap switch in a DC-DC converter is proposed. The bootstrap drive circuit includes a non-overlapping circuit, a first and a second capacitor, and a first and a second n-channel transistor. The non-overlapping circuit is configured to receive an input signal, the input signal being a function of a pulse width modulated (PWM) signal, wherein the input signal and the PWM signal are characterized by a first logic level, generate a first control signal from the input signal at a first output terminal of the non-overlapping circuit, the first control signal having the first logic level, and generate a second control signal from the input signal at a second output terminal of the non-overlapping circuit, the second control signal being characterized by a second logic level different from the first logic level.

The present invention discloses a level conversion circuit, through a bias voltage V BIAS circuit, and the logic level signals in the low voltage domain are input from the source terminals of NMOS transistors M 21 and M 22 to strengthen the current output capabilities of NMOS transistors M 21 and M 22 and improve the speed of the level conversion circuit, enabling it to operate at a lower supply voltage. When the level conversion circuit is enabled, the bias transistor M BIAS has no body effect, while the NMOS transistors M 21 or M 22 have body effects. By utilizing the threshold voltage difference brought about by the body effect of MOS transistors, the NMOS transistors M 21 or M 22 are turned off, enabling the level conversion circuit to have zero static power consumption; the bias transistor M BIAS and the NMOS transistors M 21 , M 22 are all thick-gate NMOS transistors with good matching properties. Therefore, the speed and static leakage current of the level conversion circuit vary less with the process. When there are a large number of level conversion circuits, the same bias circuit can be shared to reduce the circuit power consumption.

The invention discloses master-slave integrated MVB (Multifunction Vehicle Bus) simulation test equipment based on an FPGA (Field Programmable Gate Array) and an MCU (Microprogrammed Control Unit). An FPGA chip, an MCU chip and an MVB communication physical layer circuit are arranged in an equipment body; an MVB master logic unit and an MVB slave logic unit are integrated in the FPGA chip; the MCU chip is in communication connection with the main logic unit and the MVB slave logic unit; and the MVB communication physical layer circuit is used for realizing conversion between a logic level signal output by the FPGA chip and an EMD signal of an MVB bus. The MVB main logic control unit sends an MVB main frame according to the port traversal table stored in the port table unit; and after the MVB slave logic data and state control unit obtains the sending control right of the MVB sending control unit, the MVB slave logic unit sends or receives data with the MVB bus. The device number and cable connection are reduced, the deployment time of the test system is shortened, and the single test duration is shortened.

An event notification method and apparatus, a device, a computer program product, and a storage medium. A binding mechanism between queue pairs and completion queues involved in an event notification mechanism of a second protocol is modified, and it is proposed that the binding between queue pairs and completion queues be performed in accordance with the jurisdiction relationship between network connections and listening instances in a first protocol. Listening instances invoked in an event notification mechanism of the first protocol are also partially modified at the user-space logic level, and it is proposed that completion queues be registered within the listening scope of corresponding listening instances. A listening instance determines, by monitoring completion queue entries in a completion queue, whether a readiness event has occurred on a network connection established according to the first protocol. Then, on the basis of these completion queue entries, an event notification result conforming to the first protocol is generated and returned to an application. Accordingly, compatibility of the event notification mechanisms between the two protocols can be achieved without requiring modification of the program code of the application.

Disclosed are a level conversion circuit and a DC / DC converter, the level conversion circuit comprising: a current bias module configured to output a bias current; the control module is configured to output a control current based on the bias current under the control of an input signal in a low voltage domain; and the level conversion module is configured to output an output signal located in the high voltage domain based on the control current, and the logic level of the output signal is the same as that of the input signal. According to the invention, rapid level conversion can be realized, and interference of a high-voltage domain power supply can be well resisted.

A memory structure including a three-dimensional NOR memory string and a method of operation are disclosed. In some embodiments, the memory device performs partial polarization to provide a reference signal for read operations. The reference signal implements a third logic state distinguishable from the first and second logic stages in the ferroelectric memory transistor, e.g., associated with a program state and an erase state. In another embodiment, the memory device provides a reference signal for a read operation by averaging a first signal associated with a program state of the ferroelectric memory transistor and a second signal associated with an erase state. In some embodiments, the memory device implements one or more partially polarized states to provide more than one logical bit stored in each memory cell to multi-level memory cells.

The utility model discloses a track circuit reader test interface switching device, and relates to the field of track circuit equipment. The utility model aims to solve the problem that the traffic safety is influenced because the number of test items of TCR equipment is small. According to the track circuit reader test interface switching device of the utility model, a CAN signal input / output end of a CAN isolation transmit-receive module is used for being connected with a CAN bus of a DB15 connector, and a logic level input / output end of the CAN isolation transmit-receive module is connected with a logic level input / output end of an MCU. The parallel port information input and output end of the MCU is connected with the parallel port information input and output end of the optocoupler, and the optocoupler outputs or receives signals through the external input and output signal test interface module.

The invention provides a circuit and method for setting a PWM duty ratio and a power management system. The circuit comprises a comparison module, a logic control module, a digital logic module, a voltage selection module and a PWM generation module. The comparison module comprises a demand voltage generation unit and a comparison unit. The demand voltage generation unit generates demand voltage in a certain scene, the comparison unit compares the demand voltage with voltage provided by the voltage selection module, the logic control module analyzes the comparison result to generate a digital signal, and the digital logic module determines the range of the demand voltage. The logic level signal corresponding to the required voltage is obtained and sent to the PWM generation module, so that the PWM generation module sets the duty ratio, and therefore, the interference of power supply variation and signal noise can be reduced, the control precision of the duty ratio can be improved, the setting of different required duty ratios can be realized by adjusting the external resistor, the design is simple, and the integration level is high.

Controller and method for a constant-current switch-mode power converter. For example, a controller for a constant-current switch-mode power converter includes: a constant-current controller configured to receive an input voltage and generate a modulation signal based at least in part on the input voltage; and a driver configured to receive the modulation signal, generate a drive signal based at least in part on the modulation signal, and output the drive signal to a transistor coupled to an inductive coil and a resistor; wherein: the drive signal corresponds to at least one switching cycle; the switching cycle includes an on-time during which the drive signal is at a first logic level and an off-time during which the drive signal is at a second logic level; and the off-time includes a demagnetization period during which the inductive coil undergoes a demagnetization process.

The invention relates to the technical field of data acquisition, in particular to a data acquisition method and system with a reusable differential signal interface. The device comprises a bottom plate and a data acquisition card used for acquiring analog signals, uniform interfaces are adopted and comprise a plurality of differential signal pairs used for transmitting commands, a plurality of differential signal pairs used for transmitting data and a plurality of differential signal pairs used for transmitting clocks. According to the reusable differential signal interface disclosed by the invention, the signal integrity and reliability of long-distance transmission of signals on a bottom plate are improved through differential signals, a system can stably work in a severe electromagnetic environment, and the reusable interface can be in mixed plug-in connection with different data acquisition cards of voltage, current, strain, temperature and the like according to requirements. According to the method, step-by-step power-on is adopted, identity recognition and software configuration are only performed on a digital logic level after insertion, and simulation power supply is performed after recognition is passed, so that chain risks such as power supply impact, bus locking and even system downtime caused by insertion faults or incompatible modules are eliminated.

The invention relates to a unibus communication circuit applied to an automobile, which comprises a communication receiving circuit and a communication transmitting circuit, the input end of the communication receiving circuit and the output end of the communication transmitting circuit are both connected with an input / output port, and the output end of the communication receiving circuit is connected with the input port of an MCU (Microprogrammed Control Unit). The input end of the communication transmitting circuit is connected with the output port of the MCU; the voltage division circuit is adopted to divide the input voltage, the input voltage can be more stably matched with a switching circuit of the first triode Q2 to be converted into a 5V logic level, the voltage is more stable, and secondly, the signal output circuit adopts an MOS tube, so that the signal output circuit has higher anti-surge capacity, and the more harsh field electrical environment requirement is met. According to the invention, a split circuit scheme is adopted, materials which are delivered on a large scale and are widely applied in the market are selected, and compared with an integrated chip scheme, the overall cost has obvious advantages.

The application discloses an industrial electronic lock, which comprises a front panel, a main body and a back panel; the front panel is provided with a magnet and an input contact; the main body comprises a CPU system, an EEPROM storage chip, a FLASH chip, a relay module, a logic level module and a communication module; the back panel comprises a power module and a function output module; the input contact, the EEPROM storage chip, the FLASH chip, the relay module, the logic level module and the communication module are connected with the CPU system respectively; the relay module, the logic level module and the communication module are connected with the function output module respectively; and the power module provides power supply for the CPU system, the EEPROM storage chip, the FLASH chip, the relay module, the logic level module and the communication module. The application can realize personnel identity identification, permission management and record operation behavior, and ensures the safety of an industrial site.

A gate driver is provided for switching high voltage switching circuitry. The gate driver includes a logic level gate driver configured to generate a first light and a second light, which is modulated, a power supply configured to convert the first light into power and supply the power, and an optical driver coupled to the power supply and configured to turn on an off the high voltage switching circuitry based on the second light.

The light-emitting drive circuit still needed further consideration regarding the control of the light-emitting elements when the system is stopped. [Solution] The light-emitting drive device comprises a bypass circuit and a bypass control circuit. The bypass circuit is configured to individually switch each of the multiple light-emitting elements connected in series between an inflow state and a retracted state. The bypass control circuit controls the bypass circuit so that when the enable signal is at a first logic level, it flows the drive current to each light-emitting element individually or retracts it, and when the enable signal is at a second logic level, it retracts the drive current from all light-emitting elements until the drive current falls below a predetermined current value.

The invention relates to the technical field of electronics, and discloses a dead time setting circuit, a PCB and a chip, and the dead time setting circuit comprises a high-side input unit, a low-side input unit and a shaping unit; the high-side input unit, the low-side input unit and the shaping unit are electrically connected with one another; the high-side input unit and the low-side input unit carry out delay and logic operation processing on input signals, the input signals can be integrated and optimized in the logic level while dead zone time is set, and a foundation is laid for generating stable pre-drive signals; and then, the shaping unit shapes the pre-drive signal obtained after processing of the two units, so that the instantaneous error level in the pre-drive signal can be effectively eliminated, a stable drive signal is output, and the stability of the drive signal is ensured.