1139results about How to "Minimal number" patented technology

An anastomosis device formed from a Shape Memory Alloy (SME) wire that is annealed into a tight coil (e.g., flat coil, helical coil, cylindrical coil) that is subsequently substantially straightened (e.g., straight, longitudinally stretched spring-like shape) for being constrained within an elongate member of an anastomosis introducer instrument. After positioning and holding two tissue walls of adjacent lumens into apposition with a distally presented grasper of the instrument, a piercing tip of the anastomosis device is dispensed and inserted through the tissue walls before being allowed to relax to its tight coil shape, thereby forming the anastomosis attachment. The anastomosis device is released from the anastomosis introducer instrument, such as by fully dispensing its proximal end. Thereby, efficient single lumen anastomosis of gastrointestinal, bilatory, or other vessels may be achieved with a minimum of laparoscopic punctures, or perhaps performed fully as an endoscopic procedure.

A showerhead for film-depositing vacuum equipment having an effect shortening the length of injection tubes for a reactive gas is presented. The injection tubes extend from the bottom of a reactive gas showerhead module, and two different kinds of reactive gases are mixed with an injection support gas within a reactive showerhead module so as to inject the mixed gas. The showerhead for film-depositing vacuum equipment includes the reactive gas showerhead module above a cooling jacket and a purge gas showerhead module above the reactive gas showerhead module. The injection tubes of the reactive gas showerhead module pass through the cooling jacket disposed below the reactive gas showerhead module, and the injection tubes of the purge gas showerhead module pass through the reactive gas showerhead module disposed below the purge gas showerhead module, thereby enabling the purge gas to flow into a purge gas redistribution space defined above the cooling jacket.

A silicon-on-insulator (SOI) RF switch adapted for improved power handling capability using a reduced number of transistors is described. In one embodiment, an RF switch includes pairs of switching and shunting stacked transistor groupings to selectively couple RF signals between a plurality of input / output nodes and a common RF node. The switching and shunting stacked transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. In one embodiment, the transistor groupings are “symmetrically” stacked in the RF switch (i.e., the transistor groupings all comprise an identical number of transistors). In another embodiment, the transistor groupings are “asymmetrically” stacked in the RF switch (i.e., at least one transistor grouping comprises a number of transistors that is unequal to the number of transistors comprising at least one other transistor grouping). The stacked configuration of the transistor groupings enable the RF switch to withstand RF signals of varying and increased power levels. The asymmetrically stacked transistor grouping RF switch facilitates area-efficient implementation of the RF switch in an integrated circuit. Maximum input and output signal power levels can be withstood using a reduced number of stacked transistors.

In a read processing storage system, using a pool of CPU cores, the CPU cores are assigned to process either write operations, read operations, and read and write operations, that are scheduled for processing. A maximum number of the CPU cores are set for processing only the read operations, thereby lowering a read latency. A minimal number of the CPU cores are allocated for processing the write operations, thereby increasing write latency. Upon reaching a throughput limit for the write operations that causes the minimal number of the plurality of CPU cores to reach a busy status, the minimal number of the plurality of CPU cores for processing the write operations is increased.

A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read / write circuits in parallel has an architecture that reduces redundancy in the multiple read / write circuits to a minimum. The multiple read / write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I / O enabled data latches associated with the multiple read / write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.

A piezoelectric resonator with an acoustic Bragg reflector that includes alternating layers of high and low acoustic impedance materials. The high and low acoustic impedance dielectric materials make up electrically insulating layers.

A navigation method and apparatus finds a location and a route to a plurality of destinations with the minimum number of stops or the shortest overall distance. The navigation method includes the steps of: specifying a plurality of destinations in a navigation system; searching a one-stop location where two or more specified destinations exist or searching a location of each destination; displaying results of search for prompting a user to decide whether recommended locations of the destinations in the search result is acceptable; repeating the above steps of searching locations and displaying the search results until the user accepts recommended locations of the destinations; and guiding the user to the destinations accepted by the user.

An integrated “T” assembly combines into a single integrated assembly, a track portion along both sides of a divider. The T assembly may have a wide-base portion, which may include a spring-urged-pusher track, on one side of the divider and a narrow-base portion on the opposite side of the divider. An offset pusher may have an upper portion that is offset, via an angled offset portion, from a lower portion of the pusher. Additional supporting bases, any of which may include spring-urged-pusher tracks and / or a spring-urged pusher, may be used under a wide product. Left and right side finisher components may be paired with T assemblies near the sides of a merchandise-display shelf. The T assembly, base, and / or end finishers may be coupled to a front rail via a complimentary tongue and groove arrangement and / or a non-slidable engagement.