A method for invalidating translation entries without
deadlock in a multithreaded
data processing system including a plurality of processor cores (200), the method comprising: Generating a request to invalidate implementations by executing a corresponding instruction to invalidate implementations by an initiating
hardware thread from a plurality of concurrently executing hardware threads of an initiating processor core from a plurality of processor cores, Stopping (502) a propagation of instructions in the initiating
hardware thread that follow the request to invalidate translations in the program order until an acknowledgment
signal is received (508) that confirms completion of
processing of the request to invalidate translations at the initiating processor core, Receiving, in a shared
queue (320), memory-modifying requests from the plurality of concurrently executing hardware threads of the initiating processor core, wherein the plurality of memory-modifying requests includes a request to invalidate translations from an initiating
hardware thread of the plurality of hardware threads, in response to receiving the request to invalidate translations in the shared
queue, removing the request to invalidate translations from the shared
queue and buffering (604) the request to invalidate translations in sidecar logic (322), the sidecar logic including a plurality of sidecars, each of which is connected to one of the plurality of concurrently executing hardware threads and configured to buffer only a single request to invalidate translations generated by the corresponding hardware thread; while the request to invalidate translations is buffered in the sidecar logic,
broadcasting the request to invalidate translations through the sidecar logic such that the request to invalidate translations is received and processed by the plurality of processor cores; in response to an acknowledgment of completion of
processing of the invalidate translation request by the initiating processor core, removing the invalidate translation request from the sidecar by the sidecar logic; and Ensuring completion of
processing of the request to invalidate translations on all of the plurality of processor cores by a broadcast synchronization request.