441 results about "Coprocessor" patented technology

The invention relates to the technical field of firmware protection, in particular to a firmware protection method and system based on a security coprocessor. The method comprises the following steps: acquiring characteristic data of the coprocessor; extracting hardware entropy source data according to the coprocessor feature data; generating a hardware trust root key based on the hardware entropy source data; performing partition processing on the firmware based on the hardware trust root key to obtain firmware partition data; constructing hierarchical verification structure data according to the firmware partition data; implementing firmware starting security verification based on the hierarchical verification structure data to obtain integrity verification data; establishing a secure communication channel between the processors according to the integrity verification data; executing a bidirectional authentication process based on the secure communication channel, and generating session key data; a firmware runtime environment is monitored based on the session key data. According to the method, the hardware entropy source is extracted by measuring the physical characteristics of the coprocessor, and an unforgeable hardware trust root is established, so that the security is improved fundamentally.

The invention discloses a power supply real-time compensation technology and application based on digital signal processing, and relates to the technical field of power electronics, and the power supply real-time compensation technology comprises a split-phase parallel processing architecture: a three-phase independently configured DSP core, each core integration comprises a real-time harmonic detection module, a dynamic sliding window FFT-RT algorithm is adopted, and the window length is adjustable in a set range; the bandwidth of the self-adaptive variable parameter filter can be dynamically adjusted in a set range; the FPGA coprocessor is specially used for PWM generation; an input stage of the harmonic prediction and decomposition module is synchronously acquired by a multi-source sensor; the processing layer comprises an improved VMD decomposition unit and a variational mode decomposition order; the edge prediction network is used for deploying a lightweight LSTM model, embedding a DSP core and predicting a harmonic spectrum in a future short period; and the multi-target dynamic optimization layer is used for setting a dynamic weight distributor and performing real-time adjustment according to the load sudden change rate. According to the invention, through split-phase parallel architecture, harmonic prediction and dynamic optimization, the response speed, multi-target cooperation and reliability improvement in the field of power supply real-time compensation are realized.

The invention provides a multi-screen cabin entertainment system, and relates to the technical field of embedded systems and intelligent cabins, and the multi-screen cabin entertainment system is characterized in that an application layer is deployed with a plurality of cabin entertainment applications, and when the application layer is started, content rendering requests are sent out respectively; the hardware layer is provided with a development board, is provided with a CPU core cluster and a coprocessor, and is connected with different cabin display screens through different video output interfaces. The system layer respectively distributes an independent thread and an independent frame buffer area for each content rendering request on the CPU core cluster, and establishes a mapping relation between each frame buffer area and each video output interface; and sending operation result data of each independent thread to a coprocessor for rendering, correspondingly storing a rendering result in a frame buffer area, and then sending the rendering result to a cabin display screen for display through a video output interface. The method has the advantages that on the premise that the number of hardware coprocessors is not increased, complete separation of multi-screen rendering threads and frame buffer is achieved, and multiple cockpit entertainment applications can run at the same time and do not interfere with one another.

The invention belongs to the technical field of intelligent hardware control methods, and discloses a low-power-consumption intelligent hardware control method which comprises the following steps: acquiring working state parameters and user interaction information of intelligent hardware, and generating an equipment state feature vector; judging whether a dormancy condition is met or not according to the equipment state feature vector; when the sleep condition is satisfied, sending a network communication agent instruction; the coprocessor configures an internal timer and awakens signal output after receiving the instruction; the master control stores a system operation state, configures a wake-up source and then enters a deep sleep state; the coprocessor cuts off the power supply of the inactive module; when a timer of the coprocessor reaches a preset network heartbeat cycle, a wake-up signal is sent to the master controller; and the master control recovers the system state, updates the feature vector and re-decides whether to sleep or not. And through multi-dimensional state perception and a master-slave cooperation architecture, and through refined power management and a dynamic reevaluation mechanism, the equipment power consumption is obviously reduced on the premise of ensuring the user experience.

An end-to-end rendering system enforces policy-constrained, symbolic presentation of artificial-intelligence (AI) outputs prior to any pixel emission. An AI accelerator emits inference tokens as (token identifier, confidence, domain tag) tuples into an output FIFO. A graphics processor with a command processor and SIMD co-processor executes a policy engine that runs a deterministic finite automaton (DFA) stored in non-transitory memory. The DFA consumes the tuples and produces, before any frame-buffer writes, a permit / deny decision and a visibility mask that constrain presentation attributes. A glyph selector maps permitted tuples to entries in a constrained glyph dictionary specifying a glyph identifier, semantic class, and allowed substitutions. A provenance tagger computes a cryptographic hash over at least the glyph identifier, a DFA-state policy identifier, a session nonce, and a checksum of the tuples to create an evidence capsule bound to the glyph. A device-aware renderer, consulting a device profile registry and a rendering grammar, emits a renderable asset for the glyph only when permitted by the visibility mask and grammar. A justification ledger records, for each displayed glyph, the evidence capsule and a monotonic timestamp. Executed entirely within the graphics processor, the pipeline prevents unauthorized tokens from entering the display path, enables cryptographically verifiable traceability of visible content, and reduces bandwidth by representing outputs as glyph identifiers rather than text or raster imagery, while allowing runtime policy updates without modifying the underlying inference model.

The invention provides a controllable SCADA (supervisory control and data acquisition) industrial production control platform based on an industrial internet architecture. The controllable SCADA industrial production control platform comprises a field layer, an edge layer, a communication layer, a cloud / fog computing layer and a data management layer, wherein the field layer is composed of a sensor array, an execution mechanism, a PLC controller and an RTU terminal; the sensor array comprises a temperature sensor, a pressure sensor, a flow sensor and a position sensor, and adopts 4-20mA current loop signal output; the execution mechanism comprises an electric valve, a servo motor and a variable frequency driver, and communicates with the PLC through a Modbus RTU protocol; the PLC controller is provided with a dual-core processor and is provided with 16 digital quantity input / output channels and 8 analog quantity input channels; the RTU terminal is internally provided with a LoRa wireless communication module; the edge layer comprises an edge computing node and a protocol conversion gateway; the edge computing node is provided with an FPGA coprocessor and supports an edge reasoning framework; and multi-protocol conversion is realized through the protocol conversion gateway.

The invention provides an SIMT-based neural network processor and a task execution method thereof, and the method comprises the steps that a general processor queries a state register of a coprocessor, and the state register stores the resource condition of the coprocessor; the universal processor completes splitting from a thread block to a thread bundle according to the resource condition, and the universal processor forwards a thread bundle instruction to a thread bundle distributor of the coprocessor; and the thread beam distributor decodes instructions in the thread beams in sequence and schedules the instructions to instruction queues of different calculation cores, and the thread beams sequentially perform thread beam scheduling, instruction emission and instruction execution according to the sequence, so that all calculations of a neural network task are completed in parallel, and a running result of the neural network task is obtained. According to the method, a general processor for task splitting is introduced in front of the thread beam scheduler or a specific compiler is directly used, so that dynamic scheduling of the threads can be realized, and a scheme for dynamically expanding the number of the threads according to data precision becomes a feasible architecture option.

The invention discloses a vector coprocessor and a vector calculation method, and relates to the technical field of processors. The vector coprocessor comprises an arbitration module, a distributor module, a function module and a data path; the arbitration module is used for receiving the calculation tasks from the main processor, screening vector tasks from the calculation tasks and filtering non-vector tasks in the calculation tasks; the dispatcher module is used for determining the parallelism degree and the task queue of the vector tasks and dispatching the vector tasks according to the parallelism degree and the task queue; the function module is used for decomposing the vector task into a plurality of subtasks and determining a data path corresponding to each subtask; distributing the subtasks to the data paths, and reducing the calculation results corresponding to the data paths to generate target results corresponding to the vector tasks; and the data path is used for calculating the subtasks and sending a calculation result to the functional module. Data redundancy storage is avoided, and the working efficiency of the processor in vector calculation is improved.

Certain examples described herein relate to at least a cryptographic system and a method of operating a cryptographic system. The cryptographic system may be implemented as a co-processor for performing post-quantum cryptographic functions. The cryptographic system has a set of bus interfaces for coupling to an external computing system, a cryptographic math unit and a control unit. The cryptographic math unit in certain examples is adapted to provide one or more masked modes of operation that secure the cryptographic operations against side-channel and non-invasive attacks. The method of operating a cryptographic system involves annotating secret data and tracking those annotations through one or more arithmetic operations.

The invention discloses an embedded image decoding display system based on an ARM, and relates to the technical field of computers, and the system comprises a dynamic sensing module which is used for monitoring the CPU occupancy rate, the cache hit rate and the memory bandwidth utilization rate of an ARM processor in real time, establishing a three-dimensional resource vector containing a dynamic weight coefficient, and calculating a threshold boundary; the adaptive decoding engine comprises an optimization unit which is used for reconstructing a bit stream processing channel and a register data exchange mechanism based on an SIMD expansion instruction of an ARMv8.2 instruction set; the prediction unit is used for predicting instruction-level hotspot distribution of the decoding task by adopting a TinyLSTM model and generating an instruction transmitting strategy; the hardware optimization module is used for executing a heterogeneous collaboration strategy of the NEON coprocessor and the MaliGPU, and the heterogeneous collaboration strategy comprises the following steps: dividing DCT / IDCT (discrete cosine transform / inverse discrete cosine transform) calculation granularity; determining a mixing precision conversion assembly line of the GPU shader according to the color gamut of the display equipment; and the display driving module is used for implementing a decoding parameter dynamic confusion algorithm in the security domain and forming a tamper-proof closed loop with the optimization unit.

The invention discloses a pulse neural network hardware accelerator and a data processing method, and the accelerator is characterized in that a low-power-consumption three-stage pipeline CPU module is used for receiving input data, scheduling an SNN network acceleration instruction, and sending the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; the asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels and an on-chip network, the pulse data encoding and decoding module encodes input data into a pulse form and sends the pulse form into the neuromorphic kernels, and the neuromorphic kernels are used for performing calculation based on the data in the pulse form; the network-on-chip is used for communication between the neuromorphic kernels, and the connection between neurons before and after synapses in the neuromorphic kernels is realized by adopting a synaptic cross array. According to the invention, the data processing acceleration performance can be greatly improved.

According to the safety coprocessor hybrid encryption method based on the SM2 / 3 / 4 domestic cryptographic algorithm, a novel hybrid encryption system based on the SM2 / 3 / 4 and considering encryption safety, efficiency and key management convenience is constructed on the basis of the characteristics of the SM2 algorithm, the SM3 algorithm and the SM4 algorithm, and the encryption / decryption and signature / verification process is achieved. And aiming at the efficiency problem of a domestic SM algorithm, an encryption / decryption and signature / verification scheme is designed and realized through pure software analysis and software and hardware (SW / HW) collaboration, so that optimal division of software and hardware is realized, and the algorithm efficiency is greatly improved.

The invention discloses a financial auditing system based on artificial intelligence, which belongs to the technical field of artificial intelligence and comprises a heterogeneous data dynamic adaptation device, a trusted data pipeline system and a central auditing processing unit. The heterogeneous data dynamic adaptation device comprises a multi-protocol PHY chip set, an FPGA programmable logic array, a protocol sensing antenna array and an AI coprocessor. The protocol sensing antenna array is annularly arranged on the inner wall of the device shell and comprises at least 12 miniature receiving and transmitting modules with adjustable directions; a protocol reverse learning model is arranged in the AI coprocessor, and a protocol analysis scheme is dynamically generated by analyzing electromagnetic radiation characteristics of an interface. According to the financial auditing system based on artificial intelligence, real-time dynamic data adaptation and credible traceability of a cross-heterogeneous financial system can be achieved, the problems of format conflict, semantic ambiguity and transmission delay of multi-source heterogeneous data in the auditing process are solved, and meanwhile verifiability and non-tampering performance of the data extraction process are ensured.

An embodiment of the present application provides a data processing method, a data processing device, a processor and related devices thereof. The method is applied to a main processor core bound to a network card and configured with a cryptographic coprocessor. By receiving packets to be processed sequentially sent by a network end, network layer processing is then performed to obtain a data vector; the data vector is sequentially recorded in a circular buffer so that the main processor core and the slave processor core can obtain the data vector; after obtaining the data vector, the cryptographic coprocessor is used to perform encryption / decryption processing on the data indicated by the data vector to obtain first result data, and the result information is fed back to the circular buffer; based on the indication of the data vector in the circular buffer, the result data is sent to the network end; the result data includes the first result data and second result data obtained by the slave processor core performing encryption / decryption processing on the data indicated by the data vector using an encryption / decryption program, thereby realizing the full utilization of computing resources.

The invention relates to the technical field of computer encryption, and discloses a fully homomorphic encryption system based on a coprocessor architecture, which comprises a main processor, a coprocessor realized by an FPGA (Field Programmable Gate Array) and an upper computer, in the coprocessor, a data transmission and storage module is connected with a block random access memory through an on-chip bus to store data; the encryption module is used for encoding and encrypting the data; the KNN algorithm implementation module is used for performing distance calculation and sorting on ciphertext or plaintext data; the decryption module is used for decrypting and decoding the encrypted classification result based on a key issued by the upper computer; and the FPGA main processing module is used for controlling data input selection and comparing classification results. Through the control of the FPGA main processing module, the standardized data processing flow and the hardware collaborative architecture, the problem of difficulty in chip branch prediction is solved, and the stability and the safety of data processing are improved.

The invention discloses a quantum cognitive simulation system and method based on classical computation, and belongs to the technical field of quantum computation.A data processing module receives original data of external data input equipment, converts the original data into quantum state data after processing, and transmits the quantum state data to a quantum cognitive simulation computation module; the quantum cognitive simulation calculation module performs quantum cognitive simulation calculation by using a CPU cluster, a GPU array and a coprocessor, and stores a result in the storage module or directly transmits the result to the output module; and the output module performs format conversion on the calculation result and outputs the result to external display / control equipment. The quantum cognitive simulation system and method based on classical calculation aim at overcoming the defects of a traditional cognitive model in the aspects of processing decision fuzziness, context dependency and high-dimensional calculation efficiency, the effects of quantum superposition, interference, entanglement and the like can be efficiently simulated, quantitative calculation of related functions of human consciousness is achieved, and the quantum cognitive simulation system and method based on classical calculation can be applied to the field of quantum computing. And the performance in an actual application scene is optimized.

The invention relates to the technical field of converters, in particular to a three-phase converter control method and system, a medium and equipment. The method comprises the steps that a main processor transmits sampling original data of a three-phase converter to a first storage area; the coprocessor reads the sampled original data, performs operation to obtain operation result data, and transmits the operation result data to the second storage area; the coprocessor runs at a period higher than the preset control frequency of the main processor, and immediately triggers the operation of the sampled original data after completing the collection of the sampled original data; the main processor performs control loop calculation, reads the operation result data when the newest operation result data is needed, and loads the newest operation result data for updating operation; the main processor runs the control program at the preset control frequency, and the control program triggering time is set in a minimum allowable time window before the control output quantity loading moment. Through the above arrangement, real-time sampling is effectively realized, CPU load is optimized, and the control performance of the converter is improved.

The invention belongs to the technical field of clock chips, and discloses an intelligent calibration multi-channel clock chip system and a control method, the system comprises a coprocessor, an initial phase-locked loop, a selector and a plurality of clock output branches; the clock output branch comprises a numerical control circuit and a frequency divider which are connected with each other; the initial phase-locked loop is used for receiving an input clock signal, performing frequency multiplication on the input clock signal to obtain a reference clock signal, and sending the reference clock signal to the numerical control circuit of the at least one clock output branch through the selector; and the numerical control circuit is used for eliminating the distributed transmission delay difference in the reference clock signal by adopting a digital compensation algorithm, generating a target clock signal according to the reference clock signal after the delay difference is eliminated, and sending the target clock signal to the corresponding frequency divider. According to the invention, the absolute synchronization error of each clock output branch can be reduced, and the application scene diversity and flexibility of the clock chip are improved.

The invention belongs to the technical field of data processing. The invention discloses a matrix multiplication calculation task processing system, method and device, a storage medium, a program product and a chip, and the system comprises a storage module which is used for storing a preset weight matrix in advance; the linear transformation control module comprises a finite-state machine used for matrix multiplication operation scheduling and is used for generating an input request signal so that the matrix multiplication calculation task processing system can receive an input matrix; the operation module is used for executing matrix multiplication operation on the input matrix and a preset weight matrix to obtain a matrix multiplication operation result and generate an output matrix; and the data flow control module is used for controlling a plurality of groups of data flows formed by the input data in the input matrix according to rows to sequentially enter the operation module according to the input request signal until all the data in the input matrix execute and complete the matrix multiplication operation. The problems that in the prior art, a matrix multiplication accelerator lacks flexibility in a linear layer implementation task of artificial intelligence hardware, the data migration cost is high, and the energy efficiency ratio is low are solved, and the method is suitable for self-defined extension based on an RISC-V instruction set architecture, can be used as a coprocessor of an RISC-V processor, and can be used as a coprocessor of the RISC-V processor. And linear layer calculation in the neural network is accelerated, especially in an artificial intelligence task, the calculation efficiency can be remarkably improved, the power consumption can be reduced, and the real-time processing requirement can be met.

The invention provides a mode switching method and electronic equipment, the mode switching method is applied to the electronic equipment, the electronic equipment comprises a main processor, a coprocessor and an internal memory, operation modes of the electronic equipment comprise a power-saving mode and a working mode, the coprocessor works in the power-saving mode, the main processor does not work, and the internal memory does not work in the working mode. In the working mode, the main processor and the coprocessor work, and the method comprises the steps that first operation is received, and the first operation is used for switching the operation mode of the electronic equipment from the power-saving mode to the working mode; controlling the main processor to be powered on; and obtaining first data from the internal memory, wherein the first data is business data of the main processor stored when the operation mode of the electronic equipment is switched from the working mode to the power saving mode. By adopting the method and the device, the running mode of the electronic equipment can provide due function effects, and the function availability is improved, so that the user experience is improved.

Disclosed in the present application are a storage format conversion method, system and apparatus, and an electronic device and a storage medium, which are applied to the technical field of storage. The method is applied to a coprocessor. The method comprises: acquiring row storage page data and configuration information, which are sent by a main processor, wherein the configuration information comprises format information of each column field in a row storage page; parsing the row storage page data according to the configuration information, so as to obtain a column descriptor, wherein the column descriptor comprises a first offset address and field length of each column field in the row storage page; performing calculation according to the column descriptor, so as to obtain filling information related to a column storage page, wherein the filling information comprises a first offset address and column length of each data column in the column storage page, and column fields with the same field attribute form a data column; filling the column storage page according to the filling information, so as to generate column storage page data; and feeding back the column storage page data to the main processor. The row-column storage format conversion of variable-length field data can be supported, thereby improving the applicability of a row-column conversion method.

The invention provides an electronic book borrowing management system based on OPAC bidirectional hitching, and relates to the technical field of library informatization. Comprising the steps that a hardware acceleration layer constructs a dynamic resource distribution matrix through an FPGA coprocessor and calculates a matrix norm in real time, and request queue scanning and a redundant copy generation algorithm per 100 ms are achieved in combination with an ASIC anti-conflict controller; a system service layer deploys a dynamic priority scheduling engine, realizes intelligent resource distribution based on a cross-campus coordination coefficient and an edge cloud coordination strategy, records borrowing operation through a block chain evidence storage service and executes automatic copyright division auditing; the user interaction layer provides a bidirectional association retrieval interface and a priority borrowing channel based on credit scores. According to the system, the resource scheduling efficiency in a high-concurrency scene is improved through matrix norm calculation accelerated by hardware, an elastic copy allocation mechanism and an anti-conflict algorithm solidified in ASIC, and cross-campus resource collaboration and accurate copyright revenue allocation are realized in combination with geographic position scoring and block chain technologies.

The invention provides a synchronous communication device and method based on multiple coprocessors, equipment and a storage medium. The device comprises a main processor which is configured to send a communication instruction to a primary buffer; the cache controller is configured to distribute the communication instruction from the first-level cache to the first second-level cache and the second second-level cache; the first coprocessor is configured to read the communication instruction from the first second-level buffer and configure the communication instruction to the first terminal node; the second coprocessor is configured to read the communication instruction from the second secondary buffer and configure the communication instruction to a second terminal node; and the synchronous triggering module is configured to control the first terminal node and the second terminal node to perform synchronous communication according to the communication instruction to obtain a communication result. Therefore, the first coprocessor and the second coprocessor can simultaneously configure the corresponding terminal nodes, so that the instruction sending time is shortened, and optical fiber bus communication for spaceflight control can be accelerated through the multiple coprocessors.

The invention provides an SIMON encryption and decryption hardware acceleration system and method based on a Loongson soft core, and the system comprises a LoongArch processor soft core which is used for control, task scheduling and data interaction with external equipment; the SIMON encryption / decryption coprocessor module is used for executing an SIMON lightweight block encryption algorithm, completing key expansion and round function calculation and realizing encryption and decryption functions; the SRAM module is used for caching an original text, a ciphertext and intermediate data generated in the encryption and decryption process and supporting efficient data access; and the AXI bus interface module is used for high-speed data interaction between the SIMON encryption / decryption coprocessor module and the processor core and between the SIMON encryption / decryption coprocessor module and the SRAM module, and supports burst read-write operation. The method has high efficiency, flexibility and low power consumption, and can be widely applied to data encryption and transmission scenes of an embedded system and Internet of Things equipment.

Implementations of systems and methods for coordinating the sleep mode of a vehicle processor and coprocessor. The systems and methods may include determining whether each of a plurality of subsystems is in an operational state that permits entering the sleep state, transmitting, from the processor to the coprocessor, a trigger message, and switching the plurality of subsystems into the sleep state. The systems and methods may identify by the coprocessor whether each of the plurality of subsystems has switched to the sleep state, start a first timer with a predetermined time period, and switch the processor and coprocessor to the sleep state within the predetermined time period in response to identifying whether each of the plurality of subsystems has switched to the sleep state.

The invention provides an edge-computing-oriented low-power-consumption neural network coprocessor chip architecture, which comprises a core computing layer, a data processing layer and a power consumption and security management layer, and is characterized in that the core computing layer comprises an event-driven computing engine, a storage and computing integrated array and a dynamic reconfigurable internet. Compared with the prior art, the system has the following beneficial effects that by adding the core calculation layer, the data processing layer and the power consumption and safety management layer, the core calculation layer realizes non-zero feature selective activation through the data change threshold comparison circuit, the invalid calculation power consumption is reduced, the data carrying energy consumption is eliminated, and the task scheduler is matched to realize the dynamic path configuration of the calculation unit; the data processing layer matches a data stream with a calculation rhythm, realizes 30%-70% compression ratio of weight data and dynamically switches a calculation mode through a configuration register, and the power consumption and safety management layer dynamically adjusts threshold voltage according to a load, realizes optimal balance of power consumption and performance and outputs 32 / 16 / 8-bit flexible precision data, and can realize low-power-consumption operation.

The invention provides an extensible near-memory computing coprocessor architecture for a computing system. The architecture comprises a main processor; the storage module comprises a plurality of storage particles, and the storage module is configured to store calculation data required by the main processor; the at least one near memory coprocessor is integrated with all the storage particles through 2D, and the interface protocol of the near memory coprocessor architecture is the same as the interface protocol of the storage particles; the near-memory coprocessor is configured to perform near-memory computation on a storage-intensive computation task and store a result of the near-memory computation into the storage particle. Through the framework, the problem that the efficiency is low when an existing processor framework processes memory access intensive tasks is solved.

The invention discloses a security encryption method, device, equipment and medium for a vehicle-gauge-level HSM, and relates to the technical field of vehicle network security, and the method comprises the steps: obtaining a target algorithm parameter corresponding to a target encryption task in an algorithm parameter register after receiving the target encryption task, and determining a corresponding encryption algorithm type; if the target algorithm type is a post quantum cryptography algorithm type, a true random number generation component of a vehicle gauge level HSM is called through a post quantum cryptography coprocessor to generate a true random seed, and a target encryption task is executed based on the target algorithm parameter and the true random seed; in the process of executing the target encryption task, second-order mask operation is carried out on the fast number theory transformation operation, whether error injection attacks exist or not is continuously detected in the sampling process, and operation results of the key steps are stored through a preset composite register set.

The invention discloses a coprocessor design method suitable for implementation of an identification cryptographic algorithm, and belongs to the technical field of information security and integrated circuits. According to the method, a hardware instruction set and a coprocessor architecture are designed by analyzing and disassembling a basic operator of the identification cryptographic algorithm based on bilinear pairing operation; each hierarchical operation unit is realized by a hardware instruction layer, so that bilinear pairing operation and a complete algorithm protocol can be efficiently realized, each parameterized curve can be realized in a matched manner, the actual requirements of different performance and power consumption indexes can be met, and the flexibility is relatively high.

A communication method and a related apparatus, which relate to the technical field of communications. The method can be applied to a computing node, and comprises: receiving priority indication information of a computing task to be processed, wherein the priority indication information indicates the processing priority of a computing node for the computing task, and the priority indication information is obtained on the basis of at least one of a task requirement of the computing task and subscription data of a terminal device; and on the basis of the priority indication information, scheduling the computing task to a first position of a first queue or a second queue of the computing node, or directly scheduling the computing task to a third queue, wherein the first queue is one of a plurality of different priority queues of the computing node, the second queue is a queue in the computing node that waits to access a coprocessor resource, and the third queue is a queue in a coprocessor in the computing node. The present application can ensure the quality of service for important users or computing tasks requiring a low latency.