546 results about "Coprocessor" patented technology

The invention relates to the technical field of firmware protection, in particular to a firmware protection method and system based on a security coprocessor. The method comprises the following steps: acquiring characteristic data of the coprocessor; extracting hardware entropy source data according to the coprocessor feature data; generating a hardware trust root key based on the hardware entropy source data; performing partition processing on the firmware based on the hardware trust root key to obtain firmware partition data; constructing hierarchical verification structure data according to the firmware partition data; implementing firmware starting security verification based on the hierarchical verification structure data to obtain integrity verification data; establishing a secure communication channel between the processors according to the integrity verification data; executing a bidirectional authentication process based on the secure communication channel, and generating session key data; a firmware runtime environment is monitored based on the session key data. According to the method, the hardware entropy source is extracted by measuring the physical characteristics of the coprocessor, and an unforgeable hardware trust root is established, so that the security is improved fundamentally.

The invention discloses a power supply real-time compensation technology and application based on digital signal processing, and relates to the technical field of power electronics, and the power supply real-time compensation technology comprises a split-phase parallel processing architecture: a three-phase independently configured DSP core, each core integration comprises a real-time harmonic detection module, a dynamic sliding window FFT-RT algorithm is adopted, and the window length is adjustable in a set range; the bandwidth of the self-adaptive variable parameter filter can be dynamically adjusted in a set range; the FPGA coprocessor is specially used for PWM generation; an input stage of the harmonic prediction and decomposition module is synchronously acquired by a multi-source sensor; the processing layer comprises an improved VMD decomposition unit and a variational mode decomposition order; the edge prediction network is used for deploying a lightweight LSTM model, embedding a DSP core and predicting a harmonic spectrum in a future short period; and the multi-target dynamic optimization layer is used for setting a dynamic weight distributor and performing real-time adjustment according to the load sudden change rate. According to the invention, through split-phase parallel architecture, harmonic prediction and dynamic optimization, the response speed, multi-target cooperation and reliability improvement in the field of power supply real-time compensation are realized.

The invention relates to the technical field of integrated circuits, in particular to a processing system of a single-precision configurable matrix operation unit based on RISC-V instruction expansion, which comprises an RISC-V processor used for executing a software program and identifying a user-defined expansion instruction, and the RISC-V processor is connected with the single-precision configurable matrix operation unit through a user-defined coprocessor interface; the single-precision configurable matrix operation unit comprises an instruction response and decoding module and an instruction retirement and write-back module, and the instruction response and decoding module is used for receiving an instruction function code, source operation data and a destination register number and decoding the instruction function code; after decoding is completed, different execution units are selected according to a decoding result to send corresponding control signals; and after the execution unit completes the corresponding task, the instruction retirement and write-back module returns an execution result and a completion signal to the RISC-V processor, so that execution of a self-defined extension instruction is completed. According to the system, the matrix operation speed can be accelerated through bottom hardware under limited hardware resource consumption.

The invention provides a multi-screen cabin entertainment system, and relates to the technical field of embedded systems and intelligent cabins, and the multi-screen cabin entertainment system is characterized in that an application layer is deployed with a plurality of cabin entertainment applications, and when the application layer is started, content rendering requests are sent out respectively; the hardware layer is provided with a development board, is provided with a CPU core cluster and a coprocessor, and is connected with different cabin display screens through different video output interfaces. The system layer respectively distributes an independent thread and an independent frame buffer area for each content rendering request on the CPU core cluster, and establishes a mapping relation between each frame buffer area and each video output interface; and sending operation result data of each independent thread to a coprocessor for rendering, correspondingly storing a rendering result in a frame buffer area, and then sending the rendering result to a cabin display screen for display through a video output interface. The method has the advantages that on the premise that the number of hardware coprocessors is not increased, complete separation of multi-screen rendering threads and frame buffer is achieved, and multiple cockpit entertainment applications can run at the same time and do not interfere with one another.

The invention belongs to the technical field of intelligent hardware control methods, and discloses a low-power-consumption intelligent hardware control method which comprises the following steps: acquiring working state parameters and user interaction information of intelligent hardware, and generating an equipment state feature vector; judging whether a dormancy condition is met or not according to the equipment state feature vector; when the sleep condition is satisfied, sending a network communication agent instruction; the coprocessor configures an internal timer and awakens signal output after receiving the instruction; the master control stores a system operation state, configures a wake-up source and then enters a deep sleep state; the coprocessor cuts off the power supply of the inactive module; when a timer of the coprocessor reaches a preset network heartbeat cycle, a wake-up signal is sent to the master controller; and the master control recovers the system state, updates the feature vector and re-decides whether to sleep or not. And through multi-dimensional state perception and a master-slave cooperation architecture, and through refined power management and a dynamic reevaluation mechanism, the equipment power consumption is obviously reduced on the premise of ensuring the user experience.

An end-to-end rendering system enforces policy-constrained, symbolic presentation of artificial-intelligence (AI) outputs prior to any pixel emission. An AI accelerator emits inference tokens as (token identifier, confidence, domain tag) tuples into an output FIFO. A graphics processor with a command processor and SIMD co-processor executes a policy engine that runs a deterministic finite automaton (DFA) stored in non-transitory memory. The DFA consumes the tuples and produces, before any frame-buffer writes, a permit / deny decision and a visibility mask that constrain presentation attributes. A glyph selector maps permitted tuples to entries in a constrained glyph dictionary specifying a glyph identifier, semantic class, and allowed substitutions. A provenance tagger computes a cryptographic hash over at least the glyph identifier, a DFA-state policy identifier, a session nonce, and a checksum of the tuples to create an evidence capsule bound to the glyph. A device-aware renderer, consulting a device profile registry and a rendering grammar, emits a renderable asset for the glyph only when permitted by the visibility mask and grammar. A justification ledger records, for each displayed glyph, the evidence capsule and a monotonic timestamp. Executed entirely within the graphics processor, the pipeline prevents unauthorized tokens from entering the display path, enables cryptographically verifiable traceability of visible content, and reduces bandwidth by representing outputs as glyph identifiers rather than text or raster imagery, while allowing runtime policy updates without modifying the underlying inference model.

The invention provides a controllable SCADA (supervisory control and data acquisition) industrial production control platform based on an industrial internet architecture. The controllable SCADA industrial production control platform comprises a field layer, an edge layer, a communication layer, a cloud / fog computing layer and a data management layer, wherein the field layer is composed of a sensor array, an execution mechanism, a PLC controller and an RTU terminal; the sensor array comprises a temperature sensor, a pressure sensor, a flow sensor and a position sensor, and adopts 4-20mA current loop signal output; the execution mechanism comprises an electric valve, a servo motor and a variable frequency driver, and communicates with the PLC through a Modbus RTU protocol; the PLC controller is provided with a dual-core processor and is provided with 16 digital quantity input / output channels and 8 analog quantity input channels; the RTU terminal is internally provided with a LoRa wireless communication module; the edge layer comprises an edge computing node and a protocol conversion gateway; the edge computing node is provided with an FPGA coprocessor and supports an edge reasoning framework; and multi-protocol conversion is realized through the protocol conversion gateway.

Embodiments of the present application relate to the technical field of generation of fault locating information, and provide a method and apparatus for generating fault locating information, an electronic device, and a storage medium. The method comprises: configuring a first operating system for a coprocessor, and configuring a second operating system for a main processor, the first operating system and the second operating system being different operating systems; when a fault signal for a server is acquired by means of the main processor, sending the fault signal to the first operating system by means of the second operating system; and generating fault locating information for the server by means of the first operating system on the basis of the fault signal. Excessively occupying the main processor when the server is subjected to fault locating is effectively avoided, improving the data processing efficiency of the processor.

The embodiment of the invention discloses a taint analysis method and device, computer equipment and a storage medium, and belongs to the technical field of information security. In the application, the coprocessor of the computer equipment comprises a plurality of registers, and the plurality of registers not only can be used for storing stain information corresponding to a plurality of general registers in a main processor of the computer equipment, but also can be used for storing stain information corresponding to a program memory space of a target program currently executed by the main processor. Therefore, when the coprocessor performs taint propagation on the first instruction, the taint information of the operand of the first instruction can be accessed by accessing the plurality of registers, and compared with the mode of accessing the taint information by accessing a memory, the operation is simpler, the speed is faster, and the performance overhead is smaller.

The invention provides an SIMT-based neural network processor and a task execution method thereof, and the method comprises the steps that a general processor queries a state register of a coprocessor, and the state register stores the resource condition of the coprocessor; the universal processor completes splitting from a thread block to a thread bundle according to the resource condition, and the universal processor forwards a thread bundle instruction to a thread bundle distributor of the coprocessor; and the thread beam distributor decodes instructions in the thread beams in sequence and schedules the instructions to instruction queues of different calculation cores, and the thread beams sequentially perform thread beam scheduling, instruction emission and instruction execution according to the sequence, so that all calculations of a neural network task are completed in parallel, and a running result of the neural network task is obtained. According to the method, a general processor for task splitting is introduced in front of the thread beam scheduler or a specific compiler is directly used, so that dynamic scheduling of the threads can be realized, and a scheme for dynamically expanding the number of the threads according to data precision becomes a feasible architecture option.

The invention discloses a vector coprocessor and a vector calculation method, and relates to the technical field of processors. The vector coprocessor comprises an arbitration module, a distributor module, a function module and a data path; the arbitration module is used for receiving the calculation tasks from the main processor, screening vector tasks from the calculation tasks and filtering non-vector tasks in the calculation tasks; the dispatcher module is used for determining the parallelism degree and the task queue of the vector tasks and dispatching the vector tasks according to the parallelism degree and the task queue; the function module is used for decomposing the vector task into a plurality of subtasks and determining a data path corresponding to each subtask; distributing the subtasks to the data paths, and reducing the calculation results corresponding to the data paths to generate target results corresponding to the vector tasks; and the data path is used for calculating the subtasks and sending a calculation result to the functional module. Data redundancy storage is avoided, and the working efficiency of the processor in vector calculation is improved.

Certain examples described herein relate to at least a cryptographic system and a method of operating a cryptographic system. The cryptographic system may be implemented as a co-processor for performing post-quantum cryptographic functions. The cryptographic system has a set of bus interfaces for coupling to an external computing system, a cryptographic math unit and a control unit. The cryptographic math unit in certain examples is adapted to provide one or more masked modes of operation that secure the cryptographic operations against side-channel and non-invasive attacks. The method of operating a cryptographic system involves annotating secret data and tracking those annotations through one or more arithmetic operations.

The invention discloses an embedded image decoding display system based on an ARM, and relates to the technical field of computers, and the system comprises a dynamic sensing module which is used for monitoring the CPU occupancy rate, the cache hit rate and the memory bandwidth utilization rate of an ARM processor in real time, establishing a three-dimensional resource vector containing a dynamic weight coefficient, and calculating a threshold boundary; the adaptive decoding engine comprises an optimization unit which is used for reconstructing a bit stream processing channel and a register data exchange mechanism based on an SIMD expansion instruction of an ARMv8.2 instruction set; the prediction unit is used for predicting instruction-level hotspot distribution of the decoding task by adopting a TinyLSTM model and generating an instruction transmitting strategy; the hardware optimization module is used for executing a heterogeneous collaboration strategy of the NEON coprocessor and the MaliGPU, and the heterogeneous collaboration strategy comprises the following steps: dividing DCT / IDCT (discrete cosine transform / inverse discrete cosine transform) calculation granularity; determining a mixing precision conversion assembly line of the GPU shader according to the color gamut of the display equipment; and the display driving module is used for implementing a decoding parameter dynamic confusion algorithm in the security domain and forming a tamper-proof closed loop with the optimization unit.

The invention discloses a pulse neural network hardware accelerator and a data processing method, and the accelerator is characterized in that a low-power-consumption three-stage pipeline CPU module is used for receiving input data, scheduling an SNN network acceleration instruction, and sending the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; the asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels and an on-chip network, the pulse data encoding and decoding module encodes input data into a pulse form and sends the pulse form into the neuromorphic kernels, and the neuromorphic kernels are used for performing calculation based on the data in the pulse form; the network-on-chip is used for communication between the neuromorphic kernels, and the connection between neurons before and after synapses in the neuromorphic kernels is realized by adopting a synaptic cross array. According to the invention, the data processing acceleration performance can be greatly improved.

The present invention relates to an acceleration processing method for a video compression card based on a RISC-V processor, and belongs to the technical field of video compression card software compression research. The method performs the following steps: 1) collected image information; 2) completing AVS format encoding of the image information; 3) using the RISC-V processor and the coprocessor to interact to complete the zig-zag scanning and run-length encoding of the image information in step 2); 4) completing AVS format entropy encoding of the image information that has completed the zig-zag scanning and run-length encoding in step 3); 5) completing AVS video compression; the coprocessor participates in completing the execution, memory access and write-back functions of the RISC-V processor through coprocessor instructions. The present invention utilizes the characteristic of RISC-V itself that it has easy-to-expand instructions, generates specific coprocessor instructions for zig-zag scanning and run-length encoding at the compiler level, and adds them to traditional CPU instructions.

The invention relates to a coprocessor based on an RISC-V architecture and a processing system thereof. The coprocessor comprises a decoding unit, a control unit, an arithmetic unit, a cross-clock transmission unit and a cache unit. The decoding unit receives the value of the source register sent by the main processor and decodes the value to output an operation parameter, the control unit controls the working process of the operation unit based on the operation parameter, and the cross-clock transmission unit communicates with the main processor and comprises transmission of configuration parameters and feedback signals. Therefore, the main coprocessor can run in different clock domains; the cache unit is used for caching part of weight data and all bias data required in single operation, can be used for realizing operation of an expansion instruction, does not occupy the storage space of the main processor, and greatly improves the operation efficiency of the neural network.

According to the safety coprocessor hybrid encryption method based on the SM2 / 3 / 4 domestic cryptographic algorithm, a novel hybrid encryption system based on the SM2 / 3 / 4 and considering encryption safety, efficiency and key management convenience is constructed on the basis of the characteristics of the SM2 algorithm, the SM3 algorithm and the SM4 algorithm, and the encryption / decryption and signature / verification process is achieved. And aiming at the efficiency problem of a domestic SM algorithm, an encryption / decryption and signature / verification scheme is designed and realized through pure software analysis and software and hardware (SW / HW) collaboration, so that optimal division of software and hardware is realized, and the algorithm efficiency is greatly improved.

The invention discloses a financial auditing system based on artificial intelligence, which belongs to the technical field of artificial intelligence and comprises a heterogeneous data dynamic adaptation device, a trusted data pipeline system and a central auditing processing unit. The heterogeneous data dynamic adaptation device comprises a multi-protocol PHY chip set, an FPGA programmable logic array, a protocol sensing antenna array and an AI coprocessor. The protocol sensing antenna array is annularly arranged on the inner wall of the device shell and comprises at least 12 miniature receiving and transmitting modules with adjustable directions; a protocol reverse learning model is arranged in the AI coprocessor, and a protocol analysis scheme is dynamically generated by analyzing electromagnetic radiation characteristics of an interface. According to the financial auditing system based on artificial intelligence, real-time dynamic data adaptation and credible traceability of a cross-heterogeneous financial system can be achieved, the problems of format conflict, semantic ambiguity and transmission delay of multi-source heterogeneous data in the auditing process are solved, and meanwhile verifiability and non-tampering performance of the data extraction process are ensured.

An embodiment of the present application provides a data processing method, a data processing device, a processor and related devices thereof. The method is applied to a main processor core bound to a network card and configured with a cryptographic coprocessor. By receiving packets to be processed sequentially sent by a network end, network layer processing is then performed to obtain a data vector; the data vector is sequentially recorded in a circular buffer so that the main processor core and the slave processor core can obtain the data vector; after obtaining the data vector, the cryptographic coprocessor is used to perform encryption / decryption processing on the data indicated by the data vector to obtain first result data, and the result information is fed back to the circular buffer; based on the indication of the data vector in the circular buffer, the result data is sent to the network end; the result data includes the first result data and second result data obtained by the slave processor core performing encryption / decryption processing on the data indicated by the data vector using an encryption / decryption program, thereby realizing the full utilization of computing resources.

The invention relates to the technical field of computer encryption, and discloses a fully homomorphic encryption system based on a coprocessor architecture, which comprises a main processor, a coprocessor realized by an FPGA (Field Programmable Gate Array) and an upper computer, in the coprocessor, a data transmission and storage module is connected with a block random access memory through an on-chip bus to store data; the encryption module is used for encoding and encrypting the data; the KNN algorithm implementation module is used for performing distance calculation and sorting on ciphertext or plaintext data; the decryption module is used for decrypting and decoding the encrypted classification result based on a key issued by the upper computer; and the FPGA main processing module is used for controlling data input selection and comparing classification results. Through the control of the FPGA main processing module, the standardized data processing flow and the hardware collaborative architecture, the problem of difficulty in chip branch prediction is solved, and the stability and the safety of data processing are improved.

The invention discloses a quantum cognitive simulation system and method based on classical computation, and belongs to the technical field of quantum computation.A data processing module receives original data of external data input equipment, converts the original data into quantum state data after processing, and transmits the quantum state data to a quantum cognitive simulation computation module; the quantum cognitive simulation calculation module performs quantum cognitive simulation calculation by using a CPU cluster, a GPU array and a coprocessor, and stores a result in the storage module or directly transmits the result to the output module; and the output module performs format conversion on the calculation result and outputs the result to external display / control equipment. The quantum cognitive simulation system and method based on classical calculation aim at overcoming the defects of a traditional cognitive model in the aspects of processing decision fuzziness, context dependency and high-dimensional calculation efficiency, the effects of quantum superposition, interference, entanglement and the like can be efficiently simulated, quantitative calculation of related functions of human consciousness is achieved, and the quantum cognitive simulation system and method based on classical calculation can be applied to the field of quantum computing. And the performance in an actual application scene is optimized.

An electronic device includes a local memory, multiple global memories, a coprocessor, an application processor, a memory protect unit and a memory access monitor. The coprocessor is electrically coupled to the local memory, the global memories, and the application processor, and runs an ultra-low power framework. The ultra-low power framework includes an interrupt align and activity group, a memory predict monitor, and a task dynamic migration monitor. The interrupt align and activity group aligns multiple interrupts, so that the coprocessor is waken up based on the aligned interrupts to perform all expired low power functions, and the application processor is aligned to wake up based on a wakeup of the coprocessor. The memory protect unit and the memory access monitor are electrically coupled to the global memories and the coprocessor, run the memory predict monitor, and determine whether to power off the global memories through the memory access monitor.

This application is applicable to the field of machine learning technologies and provides a system and a method for target detection. The system includes: a controller and a coprocessor which is in communication connection with the controller. The controller is configured to perform at least some arithmetic operations of a target detection model based on a target image to be detected and / or data sent by the coprocessor. The coprocessor is configured to perform at least some arithmetic operations of the target detection model based on the target image to be detected and / or data sent by the controller. According to the system for target detection, the controller and the coprocessor are utilized to perform some of the arithmetic operations in the target detection model respectively to solve a problem of slow execution speed of target detection task in deployment of the target detection model.

The invention relates to the technical field of converters, in particular to a three-phase converter control method and system, a medium and equipment. The method comprises the steps that a main processor transmits sampling original data of a three-phase converter to a first storage area; the coprocessor reads the sampled original data, performs operation to obtain operation result data, and transmits the operation result data to the second storage area; the coprocessor runs at a period higher than the preset control frequency of the main processor, and immediately triggers the operation of the sampled original data after completing the collection of the sampled original data; the main processor performs control loop calculation, reads the operation result data when the newest operation result data is needed, and loads the newest operation result data for updating operation; the main processor runs the control program at the preset control frequency, and the control program triggering time is set in a minimum allowable time window before the control output quantity loading moment. Through the above arrangement, real-time sampling is effectively realized, CPU load is optimized, and the control performance of the converter is improved.

The invention belongs to the technical field of clock chips, and discloses an intelligent calibration multi-channel clock chip system and a control method, the system comprises a coprocessor, an initial phase-locked loop, a selector and a plurality of clock output branches; the clock output branch comprises a numerical control circuit and a frequency divider which are connected with each other; the initial phase-locked loop is used for receiving an input clock signal, performing frequency multiplication on the input clock signal to obtain a reference clock signal, and sending the reference clock signal to the numerical control circuit of the at least one clock output branch through the selector; and the numerical control circuit is used for eliminating the distributed transmission delay difference in the reference clock signal by adopting a digital compensation algorithm, generating a target clock signal according to the reference clock signal after the delay difference is eliminated, and sending the target clock signal to the corresponding frequency divider. According to the invention, the absolute synchronization error of each clock output branch can be reduced, and the application scene diversity and flexibility of the clock chip are improved.

The invention provides a task processing method and device, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the steps of obtaining at least one task request operation instruction from an upper-layer application; distributing each task request operation instruction to a password acceleration resource component according to the target scheduling mode, and processing the task request operation instructions by the password acceleration resource component; the password acceleration resource component comprises a coprocessor and encryption hardware, and the target scheduling mode comprises proportional scheduling or polling scheduling; and respectively reading a processing result of the task request operation instruction corresponding to the coprocessor and a processing result of the task request operation instruction corresponding to the encryption hardware, and returning the read processing results corresponding to the task request operation instructions to the upper-layer application. According to the scheme, idle resources can be effectively and reasonably utilized, the processing burden of a processing engine in an application layer is effectively relieved, the task processing speed is increased, and the effects of all high-performance acceleration resources in a platform are dynamically exerted.

The invention relates to a satellite navigation baseband processing device optimized by a coprocessor. A core processing part of the device adopts a realization framework of a main processor and a coprocessor; the coprocessor is used for scheduling hardware acceleration computing resources in real time under exchange control of the main processor, and completing high-real-time processing tasks such as signal capture and tracking loop processing of satellite navigation; an instruction set and an external interface of the coprocessor are subjected to targeted optimization, the bus bit width and the internal storage width of the coprocessor are expanded, and the in-situ width of an ALU and a register of the coprocessor is reserved; performing bus data access and storage by adopting an external port access instruction and an internal memory access instruction which are matched with the expanded bus according to the expansion state; and performing access and storage of single register data by adopting a bus write enable, an access instruction and a storage instruction which are matched with the expanded internal storage width. According to the invention, the function load of the main processor is effectively reduced, and the implementation cost of the baseband processing device is reduced.

The invention belongs to the technical field of data processing. The invention discloses a matrix multiplication calculation task processing system, method and device, a storage medium, a program product and a chip, and the system comprises a storage module which is used for storing a preset weight matrix in advance; the linear transformation control module comprises a finite-state machine used for matrix multiplication operation scheduling and is used for generating an input request signal so that the matrix multiplication calculation task processing system can receive an input matrix; the operation module is used for executing matrix multiplication operation on the input matrix and a preset weight matrix to obtain a matrix multiplication operation result and generate an output matrix; and the data flow control module is used for controlling a plurality of groups of data flows formed by the input data in the input matrix according to rows to sequentially enter the operation module according to the input request signal until all the data in the input matrix execute and complete the matrix multiplication operation. The problems that in the prior art, a matrix multiplication accelerator lacks flexibility in a linear layer implementation task of artificial intelligence hardware, the data migration cost is high, and the energy efficiency ratio is low are solved, and the method is suitable for self-defined extension based on an RISC-V instruction set architecture, can be used as a coprocessor of an RISC-V processor, and can be used as a coprocessor of the RISC-V processor. And linear layer calculation in the neural network is accelerated, especially in an artificial intelligence task, the calculation efficiency can be remarkably improved, the power consumption can be reduced, and the real-time processing requirement can be met.

The invention discloses a general parallel computing architecture co-processing system based on RISC-V, belongs to the technical field of digital integrated circuits, and is used for solving the problems of low computing speed and complex data propagation path in the prior art. A universal parallel operation module, a scheduling module and a shared memory; the scheduling module receives an operation request sent by the RISC-V main processor, and schedules the shared memory and controls the universal parallel operation module according to decoding information; and the universal parallel operation module performs operation on the data in the shared memory to obtain an operation result, and writes the operation result back to the shared memory. According to the method, multiple complex algorithms such as multiplication, floating point, vector and matrix are supported at the same time based on the general parallel computing architecture, support of other computing coprocessors is not needed, hardware computing resources are reused to the maximum extent in the general parallel computing architecture, hardware redundancy is reduced, non-parallel computing is optimized by utilizing the advantages of the parallel architecture, the computing speed is increased, and the computing cost is reduced. A data propagation path is optimized, and redundant data reading and writing in the transmission process are reduced.

The invention provides a mode switching method and electronic equipment, the mode switching method is applied to the electronic equipment, the electronic equipment comprises a main processor, a coprocessor and an internal memory, operation modes of the electronic equipment comprise a power-saving mode and a working mode, the coprocessor works in the power-saving mode, the main processor does not work, and the internal memory does not work in the working mode. In the working mode, the main processor and the coprocessor work, and the method comprises the steps that first operation is received, and the first operation is used for switching the operation mode of the electronic equipment from the power-saving mode to the working mode; controlling the main processor to be powered on; and obtaining first data from the internal memory, wherein the first data is business data of the main processor stored when the operation mode of the electronic equipment is switched from the working mode to the power saving mode. By adopting the method and the device, the running mode of the electronic equipment can provide due function effects, and the function availability is improved, so that the user experience is improved.