203 results about "Coprocessor" patented technology

The invention discloses a pulse neural network hardware accelerator and a data processing method, and the accelerator is characterized in that a low-power-consumption three-stage pipeline CPU module is used for receiving input data, scheduling an SNN network acceleration instruction, and sending the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; the asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels and an on-chip network, the pulse data encoding and decoding module encodes input data into a pulse form and sends the pulse form into the neuromorphic kernels, and the neuromorphic kernels are used for performing calculation based on the data in the pulse form; the network-on-chip is used for communication between the neuromorphic kernels, and the connection between neurons before and after synapses in the neuromorphic kernels is realized by adopting a synaptic cross array. According to the invention, the data processing acceleration performance can be greatly improved.

Implementations of systems and methods for coordinating the sleep mode of a vehicle processor and coprocessor. The systems and methods may include determining whether each of a plurality of subsystems is in an operational state that permits entering the sleep state, transmitting, from the processor to the coprocessor, a trigger message, and switching the plurality of subsystems into the sleep state. The systems and methods may identify by the coprocessor whether each of the plurality of subsystems has switched to the sleep state, start a first timer with a predetermined time period, and switch the processor and coprocessor to the sleep state within the predetermined time period in response to identifying whether each of the plurality of subsystems has switched to the sleep state.

A communication method and a related apparatus, which relate to the technical field of communications. The method can be applied to a computing node, and comprises: receiving priority indication information of a computing task to be processed, wherein the priority indication information indicates the processing priority of a computing node for the computing task, and the priority indication information is obtained on the basis of at least one of a task requirement of the computing task and subscription data of a terminal device; and on the basis of the priority indication information, scheduling the computing task to a first position of a first queue or a second queue of the computing node, or directly scheduling the computing task to a third queue, wherein the first queue is one of a plurality of different priority queues of the computing node, the second queue is a queue in the computing node that waits to access a coprocessor resource, and the third queue is a queue in a coprocessor in the computing node. The present application can ensure the quality of service for important users or computing tasks requiring a low latency.

Various embodiments include systems and methods for allocating memory resources in a computing system that includes memory system resource partitioning and monitoring (MPAM) features. The computing system may transition from an MPAM configuration controlled using a CPU to using an MPAM configuration managed by an external entity, such as a CPU co-processor (CPCP). The computing system may centralize MPAM operations, introduce various control modes, and / or notify the autonomous decision process in conjunction with the use of system sensors and parameters.

The invention relates to the technical field of industrial automation control and robots, in particular to a heterogeneous high-real-time multi-axis robot cooperative motion control system and method.The system comprises an SoC main control layer, an FPGA driving layer and a hardware interconnection layer, the SoC main control layer adopts a heterogeneous SoC chip, an ARM processor is responsible for track planning and task scheduling, an FPGA logic deployment reconfigurable PID calculation engine is responsible for FPGA logic deployment, and the FPGA driving layer is responsible for FPGA logic deployment. A multi-axis position ring and speed ring algorithm is realized through the time division multiplexing processing unit; the FPGA driving layer comprises a plurality of FPGA coprocessors, and an FOC current loop IP core is instantiated to execute bottom layer vector control related operation; the hardware interconnection layer adopts an EPPI protocol supporting topology awareness, dynamic bandwidth allocation and a ping-pong buffering mechanism, and efficient transmission of a control instruction and feedback data is achieved. Through hierarchical control and hardware collaborative design, the problems that an existing multi-axis control system is large in calculation delay, insufficient in synchronization precision and low in hardware resource utilization rate are effectively solved.

The invention relates to a three-dimensional visual synthesis system based on heterogeneous collaboration and screen alignment fusion, which is characterized in that a master control system generates complete viewpoint configuration information of a current scene acquired by an image acquisition device, and the complete viewpoint configuration information is used as a single data source and is simultaneously distributed to a graphic processing unit and a neural rendering coprocessor of the master control system; synchronous starting and parallel execution of the two heterogeneous rendering pipelines are achieved. And in combination with a subsequent screen alignment fusion mechanism, an end-to-end collaboration framework with low delay, low coupling and high coordination is constructed, and the key problem of real-time integration of high-fidelity contents is effectively solved. On the premise of not depending on a traditional deep buffer area or geometric alignment, high-fidelity visual content generated by special hardware acceleration and a dynamic environment of a main control system are efficiently fused, and complex effects such as lightweight asynchronous communication and real-time shadow are supported. Therefore, multiple bottlenecks in the aspects of real-time performance, compatibility and engineering deployment in the prior art are broken through.

Techniques for using soft-barrier hints are described. An example includes a synchronous microthreading (SyMT) co-processor coupled to a logical processor to execute a plurality of microthreads, with each microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode, wherein the SyMT co-processor is further to support a soft-barrier hint instruction in code which when processed by a microthread is to pause execution of the microthread to be resumed based at least in part on a data structure having at least one entry, the entry to include an instruction pointer of the soft-barrier hint instruction and a count of microthreads that have encountered the soft-barrier hint instruction at the instruction pointer.

Cluster storage systems (100) and methods provide secure generation, distribution, and update of encryption keys (132, 142) during initial cluster formation and cluster membership changes without using readable persistent media. A cryptographic co­processor (130) stores a key encryption key (132) in write-only memory and uses the unreadable key (132) for encryption and decryp­tion of a data encryption key (142). Methods to securely distribute the initial or updated the key (132) to be stored in the coprocessor (130) and securely update the key (132) when cluster membership changes are provided.

This invention belongs to the field of flight control computer hardware architecture technology, specifically relating to a heterogeneous flight control core circuit and system. This invention integrates a microcontroller unit and an artificial intelligence coprocessor unit on the same printed circuit board, achieving data and command interaction through isolated high-speed interconnect channels. The microcontroller unit constitutes the safety control and real-time decision-making domain, used to execute safety-critical and hard real-time tasks, and to implement operational management and fault isolation for the artificial intelligence coprocessor unit; the artificial intelligence coprocessor unit constitutes the intelligent sensing and computing domain, used to execute computationally intensive and non-real-time critical tasks. This architecture achieves decoupling and collaboration between the safety domain and the computing domain at the hardware level, ensuring both high functional safety and determinism in flight control, while fully releasing the high-performance computing power required for intelligent sensing, thus meeting the dual requirements of advanced aircraft for highly reliable flight control and intelligent function expansion.

A method (400) may include a processor core fetching (402) a packet of machine code instructions and then determining (404) whether a first machine code instruction of the packet corresponds to a coprocessor operation. In response to determining that the first machine code instruction corresponds to a coprocessor operation, the processor core may treat the other machine code instructions of the packet as no operations (NOOPs) and transmit (406) the machine code instructions of the packet to a coprocessor. The coprocessor may then decode and execute the machine code instructions. The method may further include the processor core keeping responsibility for load and store operations and, in the case of coprocessor operations, using (408, 410) registers of the coprocessor as source and destination for load and store operations.

A method for memory system initialization to bootstrap error correction code (ECC) regions during system boot is described. The method includes partitioning a memory sub-system into sub-system memory segments. The method also includes using a last level cache coprocessor (LCP) to initialize a first of the sub-system memory segments to provide a first ECC region. The method also includes booting a system through the first ECC region of the memory sub-system. The method also includes using the LCP to initialize remaining ones of the sub-system memory segments during the boot to enable a second ECC region of the memory sub-system.

The invention provides a program compiling method and device, electronic equipment, a storage medium and a program product. The method comprises the steps of obtaining a to-be-processed program; from the to-be-processed program, determining a task interface used for indicating to distribute the coprocessor task to the coprocessor for execution; generating a first execution code of the coprocessor task on the coprocessor based on the logic relationship of the task interface in the to-be-processed program; original logic used for calling a task interface in the to-be-processed program is updated into control logic executed by the central processing unit, an updated program is obtained, and the control logic is used for the central processing unit to drive the coprocessor to execute the first execution code; and based on the update program, generating a second execution code of the central processing unit task on the central processing unit, and packaging the first execution code and the second execution code to obtain a compiling result of the to-be-processed program. Through the method, the compiling efficiency can be effectively improved.

The invention discloses an access address configuration method, a processor, a multiprocessor system, a medium and a product. The method comprises the following steps: configuring an independent register block for each thread bundle in the processor; wherein the register group is used for storing coordinate information of tensor data used in the execution process of a corresponding thread bundle program; reading the coordinate information of the tensor data to be processed from the register group, and sending the read coordinate information to a coprocessor to carry out access address calculation of the corresponding tensor data; according to the method, each thread bundle is provided with a group of entity registers for storing the coordinate information of the tensor data, multiple multiplexing of the coordinate information can be supported, and a large number of instructions for specifying coordinates are saved, so that the number of assembly instructions is reduced, the instruction overhead is effectively reduced, the execution time of a processor is saved, and the processing efficiency of the processor is improved.

The application discloses a kind of based on coprocessor's taint propagation method and system.The steps of the method include:1) pre-analysis instruction semantics, construct the taint propagation mask table of instruction;2) by coprocessor, intervene CPU instruction pipeline decoding, write-back process;3) in decoding stage, the opcode and operand of current instruction are acquired in real time quickly, and the taint propagation mask corresponding to instruction is found in taint propagation mask table by coprocessor;4) in write-back stage, the mask table corresponding to current instruction is searched in real time quickly, and taint propagation calculation is implemented.The application can analyze the semantics of instruction, calculate taint propagation process by using the characteristics of hardware fast and accurate when CPU instruction is executed by configuring the input function return value of monitoring.

The invention provides an image rendering method and device, a storage medium and electronic equipment, and relates to the technical field of image processing, and the image rendering method comprises the steps: obtaining graphic elements of a to-be-rendered target image and attribute information of the graphic elements through a central processing unit; and sending a rendering instruction to the coprocessor through the central processing unit, so that the coprocessor renders the target image according to the graphic element and the attribute information in response to the rendering instruction. The computing process of the central processing unit is shared through the coprocessor, the load of the central processing unit can be reduced, and computing resources used by the central processing unit during image rendering are saved.

The invention belongs to the technical field of avionics, and particularly relates to an architecture design method of a TSN network end system with dual-processor collaboration. The system architecture comprises a main processor and a network card; a buffer A, a register A, a buffer B, a register B, a coprocessor and a protocol conversion module are arranged in the network card; the main processor performs data interaction with a buffer A and a register A in the network card; the coprocessor performs data interaction with a buffer B and a register B in the network card; the protocol conversion module performs data interaction with the buffer A, the register A, the buffer B, the register B and an external network; the main processor is used for receiving an airborne light thunder signal, a sensor signal, an avionics / electromechanical control signal and a graphic video signal, and outputting light thunder sensor data, an avionics / electromechanical control instruction and a graphic video signal; the coprocessor is used for receiving avionics network management data, network time synchronization data and built-in self-inspection data and outputting corresponding data packets.

The application discloses a centralized ALU time-sharing multiplexing ECC coprocessor based on a dynamic priority arbitration bus, and relates to the technical field of integrated circuit design and information security. The coprocessor comprises a centralized ALU, an intelligent arbitration module, and an ECC core master module, a point operation module and a coordinate conversion module which are all function request units. The ECC core master module generates a scheduling instruction according to a task, or sends a verification request to the intelligent arbitration module to call the centralized ALU; the point operation and coordinate conversion module generates an arithmetic operation request according to the scheduling instruction and sends the arithmetic operation request to the intelligent arbitration module; the intelligent arbitration module judges the priority of each request unit, controls the request units to send the requests to the centralized ALU in sequence; and the centralized ALU executes the arithmetic operation and feeds back the result to the corresponding request unit. The coprocessor significantly reduces the response delay.

The application discloses a kind of data processing method, device and readable medium based on blockchain, the blockchain includes terminal equipment, and the terminal equipment includes main processor and coprocessor;The method comprises: generating cryptography operation instruction according to business transaction instruction by main processor, and issuing cryptography operation instruction to coprocessor;Cryptography operation instruction is received by coprocessor, and the instruction type of cryptography operation instruction is identified;The instruction type is used to indicate the cryptography operation type corresponding to cryptography operation instruction;Business transaction instruction is executed by main processor, and cryptography operation instruction is executed according to instruction type by coprocessor.This scheme realizes the parallel execution of business transaction and cryptography operation by the collaborative architecture of main processor and integrated coprocessor, greatly improves the overall data processing speed and concurrent capability of blockchain terminal, avoids that main processor is blocked by a large number of cryptography operation tasks.

The present application relates to a kind of reconfigurable baseband processing SoC architecture based on RISC-V extension instruction set and its instruction control method, belong to communication chip and processor design technical field.For the instruction set flexibility insufficient, data handling inefficiency and dynamic reconfiguration and high energy efficiency difficult to consider of existing 5G / 6G baseband processor, the present application proposes a kind of heterogeneous computing architecture, including the RISC-V processor core cluster of supporting RV64IMAFDCV instruction set, extension instruction execution unit, vector coprocessor and reconfigurable hardware acceleration module group.By adding special instructions such as complex matrix multiplication, optimizing data path design, using double buffering mechanism and hierarchical reconfigurable technology, efficient execution of baseband processing is realized.At the same time, dynamic voltage frequency regulation system can adjust power supply parameters in real time according to work load.The scheme significantly improves the performance and energy efficiency of baseband processing, and is suitable for physical layer signal processing of 5G / 6G communication system.

The application discloses a Bluetooth channel sounding high-precision ranging SOC method, a chip and equipment. The method comprises the following steps: controlling a radio frequency transceiver front end to output a data frame and a received signal strength quantization value, a direct memory access controller carries the data frame to a memory of a channel sounding coprocessor, the coprocessor compares the quantization value with a multipath deep fading threshold value, and when the quantization value is lower than the threshold value, corresponding data is overwritten as a digital zero, a polar coordinate system conversion forms a frequency domain channel response array, an inverse fast Fourier transform is performed to extract a line-of-sight path main peak and calculate a first distance value, a high-frequency counter records a physical round trip time and converts a second distance value, a hardware interlocking comparator calculates a difference value, and when the difference value exceeds a safety tolerance window, a blocking instruction is sent to the direct memory access controller. The application can solve the data distortion problem in a multipath environment and eliminate the delay vulnerability of the anti-relay attack of the physical layer.

Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.

Cluster storage systems (100) and methods provide secure generation, distribution, and update of encryption keys (132, 142) during initial cluster formation and cluster membership changes without using readable persistent media. A cryptographic coprocessor (130) stores a key encryption key (132) in write-only memory and uses the unreadable key (132) for encryption and decryption of a data encryption key (142). Methods to securely distribute the initial or updated the key (132) to be stored in the coprocessor (130) and securely update the key (132) when cluster membership changes are provided.

The present disclosure relates to a video stream processing method and device, electronic equipment and storage medium. The method can include: transmitting a video stream at a current time to a preprocessor to cause the preprocessor to perform road element recognition on the video stream at the current time to obtain an element recognition result corresponding to the current time; sending the element recognition result corresponding to the current time to a main processor to cause the main processor to predict a video stream at a next time based on the element recognition result corresponding to the current time, determining first target allocation information in a case where a video stream prediction result represents that the predicted video stream at the next time is a first type of video stream, and awakening a coprocessor in a case where the coprocessor is not awakened. According to the technical scheme provided by the present disclosure, the video stream at the next time can be predicted, and in a case where it is determined that the video stream at the next time is the first type of video stream, the coprocessor is awakened in advance to improve the response timeliness of the coprocessor, i.e., the timeliness of processing data.

The present application relates to a kind of adaptive arctangent function computing system and method based on coprocessor, using coprocessor to complete data transmission and state control.The present application includes data write module, iteration register, iteration angle selection module, data iteration module and data write back module;Data write module reads input data from coprocessor interface and stores in iteration register;Iteration angle selection module selects optimal iteration angle according to the data characteristics in iteration register and sends to data iteration module;Data iteration module calculates iteration data according to the optimal iteration angle and iterates the state in iteration register;Data write back module sends the calculation completion signal to coprocessor and executes the calculation result write back through coprocessor interface.The present application can utilize coprocessor without changing the internal structure of processor, and also can utilize the internal logic calculation unit of processor to realize high-speed high-precision arctangent function calculation.

The utility model belongs to the field of block chains and the technical field of computer hardware circuit design, particularly relates to a computer mainboard hardware system supporting block chain acceleration, and aims to improve the intelligent contract execution efficiency of a block chain system through hardware architecture innovation, enhance the reliability of time and position verification of data, and improve the efficiency of the computer mainboard hardware system. And low-delay data synchronization among the nodes is realized to optimize the performance of the consensus mechanism. According to the main scheme, the system comprises a system basic function module, a peripheral interface circuit, a Beidou positioning hardware module and a reflection memory hardware module. The system basic function module comprises a CPU (Central Processing Unit) integrated with a special coprocessor, a memory unit, a storage unit, a clock unit and a power supply unit; the Beidou positioning hardware module is connected with the antenna unit through the MCU and the Beidou chip to generate time and position verification data of block chain transaction; and the reflective memory hardware module comprises an FPGA chip, a storage medium and an optical communication unit, and is connected with a plurality of block chain nodes through optical fibers to realize data synchronization.

This invention belongs to the field of computer communication technology and discloses an embedded computer backplane conforming to the OpenVPX standard. It includes a base plate, a power management module, and multiple load slots disposed on the base plate. The power management module, disposed on the base plate, includes a power management coprocessor and a programmable power distribution unit. The power management coprocessor receives voltage setpoints and current limits determined by an external system management controller based on the power consumption of each load slot, and sends control commands for the voltage setpoints and current limits to the programmable power distribution unit. The programmable power distribution unit outputs the voltage setpoints and current limits to the corresponding load slots according to the control commands. In this invention, the power management module can achieve independent power supply control and dynamic power adjustment for the loads in each load slot, solving the problems of resource waste and insufficient power supply caused by fixed power distribution.

The utility model relates to a bit processing system for digital ink-jet printing. The bit processing system comprises an upper computer, a core processor (comprising an instruction tight coupling memory), a coprocessor (comprising a bit operation unit), an external memory and a printer, the upper computer generates image data and a bit operation instruction; the external memory is used for receiving image data from the upper computer; the core processor stores a bit operation instruction from an upper computer through the instruction tight coupling memory and sends the bit operation instruction to the coprocessor; the core processor obtains image data from the external memory and sends the image data to the coprocessor; the coprocessor analyzes the bit operation instruction and determines a bit operation type corresponding to the bit operation instruction; the bit operation unit performs bit operation on the image data according to the bit operation type; and the bit operation unit sends the image data after bit operation to the printer, and an ink-jet printing task is executed through the printer. The utility model constructs a high-efficiency bit processing system for digital ink-jet printing.

The invention belongs to the field of embedded device security design, and particularly relates to a security starting system and method based on dynamic environment binding and heterogeneous inspection. A safe starting framework is constructed through a triaxial accelerometer, a main control chip and a verification module, wherein the main control chip integrates an annular oscillator array, a temperature sensor and a hardware hash engine, and the verification module comprises an AI coprocessor and a block chain communication module. The system firstly collects three-dimensional acceleration and environment temperature data, combines dynamic physical signals generated by an annular oscillator array, and generates a dynamic decryption key through fusion of a hardware hash engine; and then heterogeneous dual-channel verification is formed through the AI coprocessor and the block chain communication module, so that the key validity is ensured. According to the method, a static key is replaced by a dynamic trust root, the bottleneck of a single chain is broken through heterogeneous verification, protection is enhanced through environmental data binding, security and light weight are considered, a real-time industrial control scene with limited adaptive resources is adapted, and attacks such as physical detection and environmental simulation are effectively resisted.