334 results about "Coprocessor" patented technology

The invention provides a multi-screen cabin entertainment system, and relates to the technical field of embedded systems and intelligent cabins, and the multi-screen cabin entertainment system is characterized in that an application layer is deployed with a plurality of cabin entertainment applications, and when the application layer is started, content rendering requests are sent out respectively; the hardware layer is provided with a development board, is provided with a CPU core cluster and a coprocessor, and is connected with different cabin display screens through different video output interfaces. The system layer respectively distributes an independent thread and an independent frame buffer area for each content rendering request on the CPU core cluster, and establishes a mapping relation between each frame buffer area and each video output interface; and sending operation result data of each independent thread to a coprocessor for rendering, correspondingly storing a rendering result in a frame buffer area, and then sending the rendering result to a cabin display screen for display through a video output interface. The method has the advantages that on the premise that the number of hardware coprocessors is not increased, complete separation of multi-screen rendering threads and frame buffer is achieved, and multiple cockpit entertainment applications can run at the same time and do not interfere with one another.

The invention belongs to the technical field of intelligent hardware control methods, and discloses a low-power-consumption intelligent hardware control method which comprises the following steps: acquiring working state parameters and user interaction information of intelligent hardware, and generating an equipment state feature vector; judging whether a dormancy condition is met or not according to the equipment state feature vector; when the sleep condition is satisfied, sending a network communication agent instruction; the coprocessor configures an internal timer and awakens signal output after receiving the instruction; the master control stores a system operation state, configures a wake-up source and then enters a deep sleep state; the coprocessor cuts off the power supply of the inactive module; when a timer of the coprocessor reaches a preset network heartbeat cycle, a wake-up signal is sent to the master controller; and the master control recovers the system state, updates the feature vector and re-decides whether to sleep or not. And through multi-dimensional state perception and a master-slave cooperation architecture, and through refined power management and a dynamic reevaluation mechanism, the equipment power consumption is obviously reduced on the premise of ensuring the user experience.

An end-to-end rendering system enforces policy-constrained, symbolic presentation of artificial-intelligence (AI) outputs prior to any pixel emission. An AI accelerator emits inference tokens as (token identifier, confidence, domain tag) tuples into an output FIFO. A graphics processor with a command processor and SIMD co-processor executes a policy engine that runs a deterministic finite automaton (DFA) stored in non-transitory memory. The DFA consumes the tuples and produces, before any frame-buffer writes, a permit / deny decision and a visibility mask that constrain presentation attributes. A glyph selector maps permitted tuples to entries in a constrained glyph dictionary specifying a glyph identifier, semantic class, and allowed substitutions. A provenance tagger computes a cryptographic hash over at least the glyph identifier, a DFA-state policy identifier, a session nonce, and a checksum of the tuples to create an evidence capsule bound to the glyph. A device-aware renderer, consulting a device profile registry and a rendering grammar, emits a renderable asset for the glyph only when permitted by the visibility mask and grammar. A justification ledger records, for each displayed glyph, the evidence capsule and a monotonic timestamp. Executed entirely within the graphics processor, the pipeline prevents unauthorized tokens from entering the display path, enables cryptographically verifiable traceability of visible content, and reduces bandwidth by representing outputs as glyph identifiers rather than text or raster imagery, while allowing runtime policy updates without modifying the underlying inference model.

The invention provides an SIMT-based neural network processor and a task execution method thereof, and the method comprises the steps that a general processor queries a state register of a coprocessor, and the state register stores the resource condition of the coprocessor; the universal processor completes splitting from a thread block to a thread bundle according to the resource condition, and the universal processor forwards a thread bundle instruction to a thread bundle distributor of the coprocessor; and the thread beam distributor decodes instructions in the thread beams in sequence and schedules the instructions to instruction queues of different calculation cores, and the thread beams sequentially perform thread beam scheduling, instruction emission and instruction execution according to the sequence, so that all calculations of a neural network task are completed in parallel, and a running result of the neural network task is obtained. According to the method, a general processor for task splitting is introduced in front of the thread beam scheduler or a specific compiler is directly used, so that dynamic scheduling of the threads can be realized, and a scheme for dynamically expanding the number of the threads according to data precision becomes a feasible architecture option.

Certain examples described herein relate to at least a cryptographic system and a method of operating a cryptographic system. The cryptographic system may be implemented as a co-processor for performing post-quantum cryptographic functions. The cryptographic system has a set of bus interfaces for coupling to an external computing system, a cryptographic math unit and a control unit. The cryptographic math unit in certain examples is adapted to provide one or more masked modes of operation that secure the cryptographic operations against side-channel and non-invasive attacks. The method of operating a cryptographic system involves annotating secret data and tracking those annotations through one or more arithmetic operations.

The invention discloses a pulse neural network hardware accelerator and a data processing method, and the accelerator is characterized in that a low-power-consumption three-stage pipeline CPU module is used for receiving input data, scheduling an SNN network acceleration instruction, and sending the input data to an asynchronous edge SNN hardware accelerator module through a coprocessor interface; the asynchronous edge SNN hardware accelerator module comprises a pulse data encoding and decoding module, L neuromorphic kernels and an on-chip network, the pulse data encoding and decoding module encodes input data into a pulse form and sends the pulse form into the neuromorphic kernels, and the neuromorphic kernels are used for performing calculation based on the data in the pulse form; the network-on-chip is used for communication between the neuromorphic kernels, and the connection between neurons before and after synapses in the neuromorphic kernels is realized by adopting a synaptic cross array. According to the invention, the data processing acceleration performance can be greatly improved.

According to the safety coprocessor hybrid encryption method based on the SM2 / 3 / 4 domestic cryptographic algorithm, a novel hybrid encryption system based on the SM2 / 3 / 4 and considering encryption safety, efficiency and key management convenience is constructed on the basis of the characteristics of the SM2 algorithm, the SM3 algorithm and the SM4 algorithm, and the encryption / decryption and signature / verification process is achieved. And aiming at the efficiency problem of a domestic SM algorithm, an encryption / decryption and signature / verification scheme is designed and realized through pure software analysis and software and hardware (SW / HW) collaboration, so that optimal division of software and hardware is realized, and the algorithm efficiency is greatly improved.

The invention discloses a financial auditing system based on artificial intelligence, which belongs to the technical field of artificial intelligence and comprises a heterogeneous data dynamic adaptation device, a trusted data pipeline system and a central auditing processing unit. The heterogeneous data dynamic adaptation device comprises a multi-protocol PHY chip set, an FPGA programmable logic array, a protocol sensing antenna array and an AI coprocessor. The protocol sensing antenna array is annularly arranged on the inner wall of the device shell and comprises at least 12 miniature receiving and transmitting modules with adjustable directions; a protocol reverse learning model is arranged in the AI coprocessor, and a protocol analysis scheme is dynamically generated by analyzing electromagnetic radiation characteristics of an interface. According to the financial auditing system based on artificial intelligence, real-time dynamic data adaptation and credible traceability of a cross-heterogeneous financial system can be achieved, the problems of format conflict, semantic ambiguity and transmission delay of multi-source heterogeneous data in the auditing process are solved, and meanwhile verifiability and non-tampering performance of the data extraction process are ensured.

The invention relates to the technical field of computer encryption, and discloses a fully homomorphic encryption system based on a coprocessor architecture, which comprises a main processor, a coprocessor realized by an FPGA (Field Programmable Gate Array) and an upper computer, in the coprocessor, a data transmission and storage module is connected with a block random access memory through an on-chip bus to store data; the encryption module is used for encoding and encrypting the data; the KNN algorithm implementation module is used for performing distance calculation and sorting on ciphertext or plaintext data; the decryption module is used for decrypting and decoding the encrypted classification result based on a key issued by the upper computer; and the FPGA main processing module is used for controlling data input selection and comparing classification results. Through the control of the FPGA main processing module, the standardized data processing flow and the hardware collaborative architecture, the problem of difficulty in chip branch prediction is solved, and the stability and the safety of data processing are improved.

The invention discloses a quantum cognitive simulation system and method based on classical computation, and belongs to the technical field of quantum computation.A data processing module receives original data of external data input equipment, converts the original data into quantum state data after processing, and transmits the quantum state data to a quantum cognitive simulation computation module; the quantum cognitive simulation calculation module performs quantum cognitive simulation calculation by using a CPU cluster, a GPU array and a coprocessor, and stores a result in the storage module or directly transmits the result to the output module; and the output module performs format conversion on the calculation result and outputs the result to external display / control equipment. The quantum cognitive simulation system and method based on classical calculation aim at overcoming the defects of a traditional cognitive model in the aspects of processing decision fuzziness, context dependency and high-dimensional calculation efficiency, the effects of quantum superposition, interference, entanglement and the like can be efficiently simulated, quantitative calculation of related functions of human consciousness is achieved, and the quantum cognitive simulation system and method based on classical calculation can be applied to the field of quantum computing. And the performance in an actual application scene is optimized.

The invention relates to the technical field of converters, in particular to a three-phase converter control method and system, a medium and equipment. The method comprises the steps that a main processor transmits sampling original data of a three-phase converter to a first storage area; the coprocessor reads the sampled original data, performs operation to obtain operation result data, and transmits the operation result data to the second storage area; the coprocessor runs at a period higher than the preset control frequency of the main processor, and immediately triggers the operation of the sampled original data after completing the collection of the sampled original data; the main processor performs control loop calculation, reads the operation result data when the newest operation result data is needed, and loads the newest operation result data for updating operation; the main processor runs the control program at the preset control frequency, and the control program triggering time is set in a minimum allowable time window before the control output quantity loading moment. Through the above arrangement, real-time sampling is effectively realized, CPU load is optimized, and the control performance of the converter is improved.

The invention belongs to the technical field of clock chips, and discloses an intelligent calibration multi-channel clock chip system and a control method, the system comprises a coprocessor, an initial phase-locked loop, a selector and a plurality of clock output branches; the clock output branch comprises a numerical control circuit and a frequency divider which are connected with each other; the initial phase-locked loop is used for receiving an input clock signal, performing frequency multiplication on the input clock signal to obtain a reference clock signal, and sending the reference clock signal to the numerical control circuit of the at least one clock output branch through the selector; and the numerical control circuit is used for eliminating the distributed transmission delay difference in the reference clock signal by adopting a digital compensation algorithm, generating a target clock signal according to the reference clock signal after the delay difference is eliminated, and sending the target clock signal to the corresponding frequency divider. According to the invention, the absolute synchronization error of each clock output branch can be reduced, and the application scene diversity and flexibility of the clock chip are improved.

The invention belongs to the technical field of data processing. The invention discloses a matrix multiplication calculation task processing system, method and device, a storage medium, a program product and a chip, and the system comprises a storage module which is used for storing a preset weight matrix in advance; the linear transformation control module comprises a finite-state machine used for matrix multiplication operation scheduling and is used for generating an input request signal so that the matrix multiplication calculation task processing system can receive an input matrix; the operation module is used for executing matrix multiplication operation on the input matrix and a preset weight matrix to obtain a matrix multiplication operation result and generate an output matrix; and the data flow control module is used for controlling a plurality of groups of data flows formed by the input data in the input matrix according to rows to sequentially enter the operation module according to the input request signal until all the data in the input matrix execute and complete the matrix multiplication operation. The problems that in the prior art, a matrix multiplication accelerator lacks flexibility in a linear layer implementation task of artificial intelligence hardware, the data migration cost is high, and the energy efficiency ratio is low are solved, and the method is suitable for self-defined extension based on an RISC-V instruction set architecture, can be used as a coprocessor of an RISC-V processor, and can be used as a coprocessor of the RISC-V processor. And linear layer calculation in the neural network is accelerated, especially in an artificial intelligence task, the calculation efficiency can be remarkably improved, the power consumption can be reduced, and the real-time processing requirement can be met.

Implementations of systems and methods for coordinating the sleep mode of a vehicle processor and coprocessor. The systems and methods may include determining whether each of a plurality of subsystems is in an operational state that permits entering the sleep state, transmitting, from the processor to the coprocessor, a trigger message, and switching the plurality of subsystems into the sleep state. The systems and methods may identify by the coprocessor whether each of the plurality of subsystems has switched to the sleep state, start a first timer with a predetermined time period, and switch the processor and coprocessor to the sleep state within the predetermined time period in response to identifying whether each of the plurality of subsystems has switched to the sleep state.

The invention provides an edge-computing-oriented low-power-consumption neural network coprocessor chip architecture, which comprises a core computing layer, a data processing layer and a power consumption and security management layer, and is characterized in that the core computing layer comprises an event-driven computing engine, a storage and computing integrated array and a dynamic reconfigurable internet. Compared with the prior art, the system has the following beneficial effects that by adding the core calculation layer, the data processing layer and the power consumption and safety management layer, the core calculation layer realizes non-zero feature selective activation through the data change threshold comparison circuit, the invalid calculation power consumption is reduced, the data carrying energy consumption is eliminated, and the task scheduler is matched to realize the dynamic path configuration of the calculation unit; the data processing layer matches a data stream with a calculation rhythm, realizes 30%-70% compression ratio of weight data and dynamically switches a calculation mode through a configuration register, and the power consumption and safety management layer dynamically adjusts threshold voltage according to a load, realizes optimal balance of power consumption and performance and outputs 32 / 16 / 8-bit flexible precision data, and can realize low-power-consumption operation.

The invention discloses a security encryption method, device, equipment and medium for a vehicle-gauge-level HSM, and relates to the technical field of vehicle network security, and the method comprises the steps: obtaining a target algorithm parameter corresponding to a target encryption task in an algorithm parameter register after receiving the target encryption task, and determining a corresponding encryption algorithm type; if the target algorithm type is a post quantum cryptography algorithm type, a true random number generation component of a vehicle gauge level HSM is called through a post quantum cryptography coprocessor to generate a true random seed, and a target encryption task is executed based on the target algorithm parameter and the true random seed; in the process of executing the target encryption task, second-order mask operation is carried out on the fast number theory transformation operation, whether error injection attacks exist or not is continuously detected in the sampling process, and operation results of the key steps are stored through a preset composite register set.

A communication method and a related apparatus, which relate to the technical field of communications. The method can be applied to a computing node, and comprises: receiving priority indication information of a computing task to be processed, wherein the priority indication information indicates the processing priority of a computing node for the computing task, and the priority indication information is obtained on the basis of at least one of a task requirement of the computing task and subscription data of a terminal device; and on the basis of the priority indication information, scheduling the computing task to a first position of a first queue or a second queue of the computing node, or directly scheduling the computing task to a third queue, wherein the first queue is one of a plurality of different priority queues of the computing node, the second queue is a queue in the computing node that waits to access a coprocessor resource, and the third queue is a queue in a coprocessor in the computing node. The present application can ensure the quality of service for important users or computing tasks requiring a low latency.

The invention discloses a data transmission method and device, electronic equipment and a storage medium, and belongs to the technical field of communication. The method comprises the steps that a first data frame is sent to a coprocessor through a main processor, the first data frame is used for controlling the main processor to write or read data to the coprocessor, the first data frame carries an address increasing identifier, and the address increasing identifier is used for indicating the coprocessor to start writing or reading data from a starting register in N registers, n is an integer greater than 1; and writing or reading data in the N registers from the starting register based on the address increase identification through the coprocessor.

Various embodiments include systems and methods for allocating memory resources in a computing system that includes memory system resource partitioning and monitoring (MPAM) features. The computing system may transition from an MPAM configuration controlled using a CPU to using an MPAM configuration managed by an external entity, such as a CPU co-processor (CPCP). The computing system may centralize MPAM operations, introduce various control modes, and / or notify the autonomous decision process in conjunction with the use of system sensors and parameters.

Methods, systems, and devices are disclosed for calculating parameters, such as electrodynamic parameters of a battery or other electrochemical system. A system includes a sequencing, programmable core (e.g., a central processing unit (CPU)) or other digital logic which is used to control a state machine of the system. One or more digital logic accelerators (e.g., co-processor or math co-processor) blocks may be used in operable communication with at least one accelerator module, wherein the at least one accelerator module is configured to provide an input to the CPU that is used in calculating the electrodynamic parameter of the battery.

The invention relates to the technical field of industrial automation control and robots, in particular to a heterogeneous high-real-time multi-axis robot cooperative motion control system and method.The system comprises an SoC main control layer, an FPGA driving layer and a hardware interconnection layer, the SoC main control layer adopts a heterogeneous SoC chip, an ARM processor is responsible for track planning and task scheduling, an FPGA logic deployment reconfigurable PID calculation engine is responsible for FPGA logic deployment, and the FPGA driving layer is responsible for FPGA logic deployment. A multi-axis position ring and speed ring algorithm is realized through the time division multiplexing processing unit; the FPGA driving layer comprises a plurality of FPGA coprocessors, and an FOC current loop IP core is instantiated to execute bottom layer vector control related operation; the hardware interconnection layer adopts an EPPI protocol supporting topology awareness, dynamic bandwidth allocation and a ping-pong buffering mechanism, and efficient transmission of a control instruction and feedback data is achieved. Through hierarchical control and hardware collaborative design, the problems that an existing multi-axis control system is large in calculation delay, insufficient in synchronization precision and low in hardware resource utilization rate are effectively solved.

Disclosed are various embodiments for authentication with network connected computing resources using a cryptographic coprocessor installed on a client device. A request can be sent to the client device to provision an asymmetric encryption key-pair using a cryptographic coprocessor installed on the client device, wherein the request comprises a key-authorization credential for the asymmetric encryption key-pair and the asymmetric encryption key-pair comprises a public key and a private key. The public key of the asymmetric encryption key-pair and an identity public key for the cryptographic coprocessor can be received. The public key, key-authorization credential, and the identity public key can then be stored in association with each other.

This invention provides an e-book lending management system based on OPAC bidirectional linkage, belonging to the field of library information technology. It includes: a hardware acceleration layer that constructs a dynamic resource distribution matrix and calculates the matrix norm in real time using an FPGA coprocessor, combined with an ASIC anti-collision controller to implement request queue scanning every 100ms and a redundant copy generation algorithm; a system service layer that deploys a dynamic priority scheduling engine, achieving intelligent resource allocation based on cross-campus collaboration coefficients and edge-cloud collaboration strategies, while recording borrowing operations and performing automated copyright revenue sharing audits through blockchain notarization services; and a user interaction layer that provides a bidirectional association search interface and a priority borrowing channel based on credit scoring. The system improves resource scheduling efficiency in high-concurrency scenarios through hardware-accelerated matrix norm calculation, an elastic copy allocation mechanism, and an anti-collision algorithm embedded in ASICs. Combined with geolocation scoring and blockchain technology, it achieves cross-campus resource collaboration and accurate allocation of copyright revenue.

The invention discloses an FPGA (Field Programmable Gate Array) coprocessor for accelerated execution of an intelligent contract, which belongs to the field of hardware acceleration and comprises a controller module, an operation module, a memory module and a stack module, the controller module is used for receiving a byte code instruction of an external smart contract and generating a control signal to control the operation module to carry out corresponding operation and / or the stack module to carry out corresponding operation; the memory module is used for receiving and storing to-be-operated data output by the smart contract and outputting corresponding operation data to the stack module, and then the stack module inputs the data to the operation module; the operation module comprises a calculator module, a multiplier module, a divider module and a hash operation module; and the stack module is used for storing the data obtained by the calculation of the operation module, and can also execute the operations of in-stack, out-stack, copying and exchange according to the control of the control signal, and outputting the data stored in the stack module to the memory module. The method is suitable for block chains and other high-performance computing applications.

The invention relates to a three-dimensional visual synthesis system based on heterogeneous collaboration and screen alignment fusion, which is characterized in that a master control system generates complete viewpoint configuration information of a current scene acquired by an image acquisition device, and the complete viewpoint configuration information is used as a single data source and is simultaneously distributed to a graphic processing unit and a neural rendering coprocessor of the master control system; synchronous starting and parallel execution of the two heterogeneous rendering pipelines are achieved. And in combination with a subsequent screen alignment fusion mechanism, an end-to-end collaboration framework with low delay, low coupling and high coordination is constructed, and the key problem of real-time integration of high-fidelity contents is effectively solved. On the premise of not depending on a traditional deep buffer area or geometric alignment, high-fidelity visual content generated by special hardware acceleration and a dynamic environment of a main control system are efficiently fused, and complex effects such as lightweight asynchronous communication and real-time shadow are supported. Therefore, multiple bottlenecks in the aspects of real-time performance, compatibility and engineering deployment in the prior art are broken through.

To provide an information processing device that enables overlapping of communication and calculation without buffering the communication between calculation processes on a host.SOLUTION: In an information processing device, a coprocessor-host memory translation function maps a calculation process virtual memory for a calculation process in a coprocessor provided in the information processing device to an offloading function virtual address for collective communication offloading. The collective communication offloading function uses the mapped offloading function virtual address to perform remote direct memory access (RDMA) for another information processing device connected via a network, and implements communication between the calculation process and a calculation process of the other information processing device.SELECTED DRAWING: Figure 1

Techniques for using soft-barrier hints are described. An example includes a synchronous microthreading (SyMT) co-processor coupled to a logical processor to execute a plurality of microthreads, with each microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode, wherein the SyMT co-processor is further to support a soft-barrier hint instruction in code which when processed by a microthread is to pause execution of the microthread to be resumed based at least in part on a data structure having at least one entry, the entry to include an instruction pointer of the soft-barrier hint instruction and a count of microthreads that have encountered the soft-barrier hint instruction at the instruction pointer.

A processor includes a time counter and a vector coprocessor for executing vector instructions for statically dispatching vector instructions with preset execution times based on a write time of a register in a coprocessor register scoreboard and a time counter provided to a vector execution pipeline. The processor also provides a method for hiding the latency of the vector load instructions.

The invention relates to the field of state evaluation, and particularly discloses a method and a system for evaluating the starting state of a wind turbine generator based on a PLC (Programmable Logic Controller), which do not limit the starting state evaluation of the wind turbine generator to a single and static end point value, but improve the evaluation dimension from a point to a line and a plane. Specifically, firstly, when a starting command is responded, a PLC coprocessor is used for matching or dynamically generating a target dynamic health curve adaptive to the current working condition from a preset DHP database according to context information such as the current environment temperature. The curve not only defines an ideal temperature-time track, but also is embedded with key dynamic characteristics such as ideal heating rate, fluctuation range and the like. Afterwards, after time sequence data of a to-be-monitored component is collected in real time, real-time dynamic features of the to-be-monitored component are extracted and subjected to vectorized contour similarity comparison with features of a target curve, and therefore a quantized health score is obtained.

Cluster storage systems (100) and methods provide secure generation, distribution, and update of encryption keys (132, 142) during initial cluster formation and cluster membership changes without using readable persistent media. A cryptographic co­processor (130) stores a key encryption key (132) in write-only memory and uses the unreadable key (132) for encryption and decryp­tion of a data encryption key (142). Methods to securely distribute the initial or updated the key (132) to be stored in the coprocessor (130) and securely update the key (132) when cluster membership changes are provided.