234 results about "Instruction stream" patented technology

The invention relates to the technical field of robot scheduling, and discloses a robot task management framework system based on asynchronous communication. The system comprises a task asynchronous analysis module for performing time sequence decoupling on an original task instruction stream of a heterogeneous robot terminal by means of a multi-channel buffer queue to separate out independent executable task units; the resource dynamic mapping module is used for establishing a variable granularity resource allocation mapping table according to cluster real-time load and task resource requirements, and recording various resource dynamic binding relationships; the task priority reconstruction module is used for constructing a directed acyclic graph scheduling topology based on task logic dependence and deadline constraint, and generating a weighted execution sequence through topological sorting; the exception isolation processing module captures exceptions during operation and triggers an isolation strategy; and the cross-node cooperation module guarantees the multi-robot cooperation task state consensus through a distributed consistency protocol. The system is suitable for heterogeneous robot cluster complex task scenes.

The invention relates to the technical field of chip design, and discloses a chip dynamic power consumption scheduling method and system based on an intelligent algorithm. The method comprises the following steps of: firstly, acquiring instruction stream data operated by a chip in real time, extracting a feature vector comprising an instruction dynamic change vector and context associated data, and determining a power consumption prediction mapping parameter according to the feature vector; and when the parameter exceeds a preset threshold value, an accurate power consumption prediction result is generated by adjusting the weight of the convolutional neural network. Subsequently, a synchronous timing demand is calculated based on the instruction switching frequency and the data dependency, and an initial power supply configuration is determined. By monitoring task load classification signals, the power consumption distribution proportion is adjusted when the signals are lower than a threshold value, the optimized power supply configuration is obtained, and the improvement index of the resource distribution efficiency is calculated according to the optimized power supply configuration. And finally, according to the index, dynamically adjusting a limiting condition of a scheduling period, and forming a self-adaptive optimization framework, thereby realizing accurate prediction and dynamic optimization scheduling of the chip power consumption.

The invention discloses an industrial robot multi-machine cooperative interaction method and system based on artificial intelligence. The method comprises the following steps: S1, collecting and preprocessing interaction data of an industrial robot; s2, constructing a cooperative relation graph formed by industrial robot nodes and interaction edges; s3, disassembling the target task by adopting a priority mechanism and generating an execution weight matrix; s4, in combination with the interaction data and the weight matrix, generating a cooperative action vector through a multi-target reinforcement learning algorithm; s5, action conflict detection is executed, path overlapping and resource conflicts are eliminated, and a candidate action sequence is obtained; s6, generating a path and a control instruction, and forming a distributed execution instruction stream; and S7, driving the robot to execute the task, collecting feedback, updating the atlas, and circularly executing until the task is completed. According to the invention, task cooperation, path obstacle avoidance and dynamic optimization control among multiple industrial robots are realized, and the scheduling efficiency, the execution stability and the system intelligence level are effectively improved.

The invention relates to the technical field of simultaneous interpretation, and discloses a simultaneous interpretation data processing method and system based on a POE microphone array. The method comprises the following steps: synchronously acquiring multi-language original audio streams and meeting place environment noise spectrum features through a distributed microphone array powered by the Ethernet; after time domain framing is carried out on the audio stream, adaptive filtering is carried out by using a dynamic noise reduction weight coefficient to obtain a primary pure voice segment; dividing the multi-language speech endpoint detection model into independent speech units with language labels through a pre-trained multi-language speech endpoint detection model, and matching a corresponding acoustic model to generate a phoneme-level time alignment sequence; comparing and outputting a term replacement instruction stream in real time in combination with a simultaneous transfer term library, and generating an intermediate semantic representation vector after fusion; and the low-delay encoder converts the voice parameter sequence into a target language voice parameter sequence, and drives the waveform synthesizer to generate final simultaneous transmission audio. The method optimizes the whole process processing, gives consideration to the simultaneous transmission accuracy and real-time performance, and is suitable for a multilingual meeting place scene.

The invention discloses a double-seat cooperative safety control method and system for engineering machinery, relates to the technical field of engineering machinery control, and provides the following scheme that the method comprises the steps that a first operation instruction stream of a main driving seat and a second operation instruction stream of a co-driving seat are collected in real time, and a working condition parameter set of the engineering machinery is synchronously obtained; the operation instruction stream comprises all degree-of-freedom motion parameters of the engineering machinery, inputting the first operation instruction stream into a pre-constructed long-short-term memory model, outputting a prediction operation instruction stream in a future time window, and based on a difference vector of the first operation instruction stream and a second operation instruction stream on each degree-of-freedom motion parameter. According to the method, through the index curve fitting model and Simpson integral calculation, the defect that the co-pilot intervention weight is difficult to quantify is overcome, the dynamic intervention weight based on the physical equidistant interval absolute integral value is realized, and the accuracy of the control signal of the engineering machinery is improved.

The invention discloses a dynamic resource demand characterization method and system for a task life cycle, and belongs to the technical field of artificial intelligence computing power resource management.The method comprises the steps that when a task is started, a monitoring agent is deployed, the task life cycle is dynamically divided through a GPU instruction sudden increase inflection point, and a CPU instruction stream is synchronously monitored; task semantic features, CPU / GPU hardware indexes and interaction time delay data are collected, key features are extracted after space-time alignment, and collaborative efficiency indexes are calculated; constructing a cross-stage resource demand coupling matrix based on a historical task library, and quantifying CPU / GPU resource conduction coefficients in adjacent stages; constructing a double-flow prediction model, predicting a resource demand in combination with the coupling matrix, and generating a three-dimensional demand matrix; and encoding the demand matrix into a dynamic vector, introducing a stage transition resource change intensity enhancement vector, and finally outputting an enhancement vector sequence to trigger CPU / GPU cooperative scheduling.

The invention discloses a real-time software deformation interaction method based on a physical engine in an environment. The real-time software deformation interaction method comprises the following steps: S1, establishing a virtual environment and a software model; s2, constructing an interactive perception and collision detection network; s3, receiving and analyzing a multi-modal interaction instruction; s4, real-time deformation calculation based on a physical engine; s5, performing multi-user collaborative state synchronization and rendering feedback; and S6, carrying out fault state simulation on the software object. According to the method, real-time and high-precision simulation of software deformation is realized through deep fusion of software dynamics calculation of a physical engine and an interaction instruction stream, and through hierarchical physical attribute binding and client prediction, the network synchronization data volume is greatly reduced while the millimeter-level deformation precision is ensured, so that the network synchronization efficiency is improved. And low-delay and high-consistency experience under multi-person cooperative operation is ensured.

The invention relates to the technical field of confidential computing, and discloses a data credibility-oriented vehicle-mounted integrated security computing system and credibility construction method, which comprises the following steps of: establishing a static trust chain by using a hardware trust root, shielding external interruption in a credible execution environment, and controlling a performance monitoring unit; synchronously collecting real-time hardware micro-architecture events of the key business algorithm to generate a runtime feature vector; according to the method, the instruction stream during operation is anchored by utilizing the physical characteristics of the micro-architecture, the hijacking attack of the control stream is accurately identified in a ciphertext environment, the hijacking attack of the control stream is accurately identified, the hijacking attack of the control stream is accurately identified, the hijacking attack is accurately identified, and the hijacking attack of the control stream is accurately identified. Strong coupling verification of a calculation result and an execution behavior is realized, and logic safety of a vehicle-mounted platform is ensured.

The invention discloses a test spline identity tracing method and system based on a block chain. The method comprises the following steps: collecting full-life-cycle multi-modal data of a test spline embedded with a PUF chip for quality evaluation and semantic mapping; generating an attack judgment mark and an abnormal conduction path so as to embed an encrypted watermark in the control instruction; carrying out block chain evidence storage on the standardized traceability data set; constructing a test spline dynamic knowledge graph to generate a knowledge enhancement traceability data set; analyzing a control instruction stream carrying a watermark, monitoring a deviation value between an execution result and an expected physical behavior, generating an execution deviation value and watermark feedback data, enhancing a traceability data set in combination with base knowledge, generating attack source coordinate information and a traceability path map, and pushing a traceability report which cannot be tampered. The space-time calibration of the multi-source heterogeneous data is realized, and the integrity and consistency of the traceability data are ensured; a PUF chip is adopted, and watermark information which cannot be tampered is embedded in a control instruction, so that double protection from a physical layer to a data layer is realized.

The invention discloses a statistical data downloading method for supply chain finance, which relates to the technical field of finance and comprises an acceptance permission judgment module, a query resource control module and a desensitization packaging evidence storage module. The acceptance permission judgment module is used for uniformly accessing the statistical application, completing identity verification, main body range binding, index range binding, time range binding and area range binding, and generating an acceptance bill and a judgment bill; the query resource control module is used for generating a query plan under the index aperture mapping dictionary, the partition information and the resource quota, binding a concurrent quota, a throttling quota and a priority queue, and outputting an executable instruction stream; and the desensitization packaging evidence storage module is used for executing differential desensitization according to the main body type and the sensitivity level, performing aggregation calculation and deduplication execution, completing result set packaging, digital watermarking and downloading delivery, generating a downloading certificate and writing a certificate abstract and an evidence index into an evidence storage chain. The method has the characteristic of high consistency.

The invention discloses a method for constructing vTEE and certification in an AMD SEV environment, provides a refined communication and fusing sequence diagram for the vTEE for the first time, and defines a module interaction sequence under two scenes of normal task execution and anomaly detection. According to the method, a trusted cloud security management platform initiates a request, a protection component coordinates a calculation component to collect an SEV-SNP report and vTEE key data, signature combination and uploading verification are carried out, and finally, the platform compares with a reference value to determine whether the vTEE is trusted or not. According to the method, a double-layer certification mechanism of SEV hardware certification and vTEE equipment measurement is adopted, an SEV-SNP certification report proves that a hardware environment, a VM mirror image and a vTEE operation environment are not tampered, vTEE key data measurement supports complete trust chain verification of equipment firmware, instruction streams and strategy states, and end-to-end certification is achieved. Equipment-level measurement, strategy issuing, abnormal fusing and remote certification are realized through an external protection part, and the system has important commercial landing value and strong system expandability.

A power consumption prediction and management method and system based on a solid state disk, a medium and a product relate to the field of solid state disks. The method comprises the following steps: predicting the workload intensity of a host in a first preset time window based on an I / O (Input / Output) instruction stream to obtain an expected host workload curve, and determining an expected host idle time period; calculating an expected host power consumption value in the expected host idle time period; extracting internal state parameters of the solid state disk according to the historical operation log data; establishing a background task triggering probability model, and calculating the triggering probability of starting the high-power-consumption background task by the solid state disk in a first preset time window; performing power consumption conflict judgment according to the expected host power consumption value and the triggering probability, and generating a comprehensive predicted power consumption value; and based on the comprehensive predicted power consumption value, determining an optimal target power consumption state, and instructing the solid state disk to be switched to the optimal target power consumption state. By implementing the technical scheme provided by the invention, the stability of state switching of the solid state disk is improved.

The invention relates to the technical field of instruction set conversion, and discloses an instruction set conversion method of a GPU heterogeneous environment based on simulation software. According to the method, the key instruction stream in the simulation task is accurately captured through the dynamic instrumentation method, and a solid foundation is provided for subsequent processing; the method comprises the following steps: dividing an original instruction stream into a plurality of instruction blocks to be converted through a classification mechanism according to instruction semantic features and hardware suitability, and creating conditions for parallel conversion; a lightweight front-end translator is adopted to efficiently convert classified instruction blocks into architecture-independent intermediate representations, the degree of parallelism and the data dependency relationship between instructions are reserved, the intermediate representation instructions are deeply optimized, and the method comprises the key steps of instruction selection, register allocation, instruction recombination, SIMT mapping, instruction coding and the like. And generating a native instruction of the target GPU architecture through accelerated translation of the target GPU thread block. According to the method, the instruction conversion period is shortened, and the correctness and the execution efficiency of the conversion result are improved.

The invention discloses a cross-platform order data format conversion and unified instruction set generation system, and relates to the technical field of data format conversion. The method comprises the following steps: establishing a cross-source semantic recognition template and a semantic mapping index table, performing semantic decomposition on multi-source order data, generating a semantic node sequence, constructing a dynamic semantic association link in a unified logic domain to form a standard semantic format, generating a unified parameter instruction template, and embedding a cross-platform instruction process; and semantic automatic identification and mapping updating of the newly added order field are realized. By constructing the cross-source semantic recognition template and the unified parameter instruction template, semantic recognition, decomposition and dynamic updating of multi-platform order data are achieved, it is ensured that meanings of same-name fields are accurately distinguished, the structures of the same-name fields are unified, semantic logic consistency and execution process continuity are kept, and the data fusion accuracy and the intelligent level of equipment control are improved.

The invention discloses an information fusion and reasoning method and system based on multi-agent collaborative networking search, and relates to the technical field of network information, and the method comprises the steps: a deep research strategy scheduling agent deconstructs an unstructured request through a task formalization mechanism, generates a high-dimensional instruction code, and dynamically optimizes an execution path. And the network intelligence index generation agent extracts and screens the trusted URL by using a rule engine and a semantic evaluator based on the code, and generates a structured link instruction stream. The structured analysis intelligent agent implements multi-level semantic distillation and conversion on an original document to obtain key value pair representations, and the key value pair representations are packaged into machine readable data. And generating a comprehensive intelligence abstract with consistent logic through the information fusion analysis agent. And the natural language generation engine converts the information into a professional report, and returns the professional report to the scheduling module through a feedback interface to realize cognitive closed-loop iterative optimization. The technical problem that in the prior art, it is difficult for geologists to obtain accurate, comprehensive and credible professional conclusions is solved.

The invention relates to the technical field of digital content production, and discloses an interactive digital content production system based on a Transform architecture. According to the system, text, image and audio data of original digital content are acquired through a content feature extraction module, cross-modal feature alignment is performed by using a multi-head attention mechanism, and content feature tensors with space-time relevance are generated; the dynamic weight distribution module calculates relative importance scores of different modal features based on the tensor, and adopts a gating mechanism to perform dynamic weight fusion to form content semantic enhancement representation; the interaction intention analysis module performs space-time coding matching on the enhanced representation and the user operation instruction stream, and analyzes an intention distribution matrix of user operation on the content dimension; a hierarchical decoding generation module constructs a multi-scale content generation path in a Transform decoder according to the intention distribution matrix; and the real-time rendering engine module loads implicit representation output by the path, so that efficient and intelligent digital content creation is realized.

The invention provides an operation method of an attention mechanism in a chip, the chip, electronic equipment, a storage medium and a program product. In a forward stage of attention model training, forward calculation is performed on a query matrix, a key matrix and a value matrix in each thread of a calculation engine based on a first instruction pipeline to obtain a forward output matrix, in algorithm implementation, matrix multiplication is executed by calling a matrix multiplication unit through a first thread and a third thread, and a forward output matrix is obtained. The vector calculation is processed by a second thread calling vector calculation unit; in a reverse phase, performing reverse calculation on the query matrix, the key matrix, the value matrix and the output gradient matrix in each thread based on a second instruction pipeline to obtain a target gradient matrix; the matrix multiplication unit is called in the first thread and the third thread to execute matrix multiplication, the vector calculation unit is called in the second thread to execute vector calculation, and the data carrying unit is called in the idle first thread or the third thread to obtain all matrixes. According to the invention, the operation performance of the chip can be improved.

The invention discloses a power transaction auxiliary decision processing method and system based on extreme weather, and relates to the technical field of power transaction decision, and the method comprises the steps: obtaining an extreme weather early warning message to form an original weather early warning data set; performing space-time reference alignment on the data set to generate a grid chart containing a meteorological intensity matrix and a power generation facility distribution index; mapping the meteorological intensity matrix to obtain a meteorological sensitivity coefficient matrix, and carrying out topological association on power generation facility distribution indexes to obtain a power generation side asset vulnerability association table; inputting the two into a risk conduction calculation engine for coupling deduction to generate a power supply-demand imbalance risk thermodynamic diagram; constructing a transaction price elasticity prediction model based on the thermodynamic diagram, and forming a transaction strategy reference matrix; quotation interval suggestions are generated through matching of the decision rule base and are converted into standardized declaration instruction streams to be pushed to the transaction interface end. According to the method, the extreme weather information and the power transaction decision can be accurately joined, and the accuracy and the normalization of the transaction decision are improved.

A method for compiling a computational graph, and a related product. The method comprises: acquiring a computational graph to be compiled that is expressed by a second intermediate representation, performing forward inference of a shape, and on the basis of the forward inference and tensor data splitting information, obtaining complete shape information; using the complete shape information to determine whether the tensor data splitting information needs to be adjusted; on the basis of a determination result, determining the tensor data splitting information that meets requirements; on the basis of the tensor data splitting information that meets the requirements, performing memory access pattern derivation on operators in the computational graph; on the basis of a derived memory access pattern, determining address-domain-related parameters of instructions involved in loops in code logic of the computational graph; performing pipeline scheduling on the instructions in the loops; and on the basis of the address-domain-related parameters of the instructions involved in the loops and a pipeline scheduling result of the instructions, compiling the computational graph, so as to obtain a binary file recognizable by an intelligent processor.

The invention discloses a periodic synchronous position interpolation control method and system for a servo driver, and relates to the technical field of servo control, and the method comprises the steps: receiving a synchronous position instruction at a fixed bus period, and recording a theoretical / actual arrival timestamp of the synchronous position instruction; converting the instruction into a position increment and storing the position increment into a buffer; calculating a cache saturation index reflecting instruction stream supply and demand balance in real time; based on the index and the change trend, dynamically calculating and smoothly adjusting a next position loop sampling period through a feedback control model; position loop processing is triggered in the post-adjustment period. According to the invention, by monitoring the instruction stream state and adaptively adjusting local processing, the influence caused by master and slave clock skew and network jitter is compensated, and continuous and uniform instruction input is ensured to be always obtained by a position ring, so that high-stability and high-precision motion control under bus communication is realized, and the anti-interference capability and the synchronization performance of the system are improved.

The invention provides a multi-shape batch rendering method suitable for a GPU without hardware batch processing capability, and relates to the technical field of computer graphic rendering, the method comprises the following steps: pre-defining path drawing instruction templates of various graphic primitives and text characters; traversing and analyzing all to-be-rendered graphics and text elements of the current frame, and uniformly converting the to-be-rendered graphics and text elements into a path instruction sequence and coordinate parameters; separately storing the instruction and the parameter in a global array; sorting and combining all elements according to the rendering hierarchy to generate a global instruction stream and a parameter stream; and finally, packaging the complete instruction stream and the parameter stream into a single drawing command, and submitting the single drawing command to a GPU (Graphics Processing Unit) through one-time calling to complete the whole-frame rendering. According to the method, unified batch processing of graphs and texts on the path level can be realized, the GPU calling times are remarkably reduced, and the interface rendering efficiency and smoothness on resource-limited equipment such as smart watches and health bracelets are greatly improved.

The application provides an operation method of an attention mechanism in a chip, a chip, an electronic device, a storage medium and a program product; in a forward stage of attention model training, based on a first instruction flow, a query matrix, a key matrix and a value matrix are calculated forward in each thread of a calculation engine to obtain a forward output matrix; in the algorithm implementation, matrix multiplication is executed by a matrix multiplication unit called by a first thread and a third thread, and vector calculation is processed by a vector calculation unit called by a second thread; in a reverse stage, based on a second instruction flow, the query matrix, the key matrix, the value matrix and an output gradient matrix are calculated reversely in each thread to obtain a target gradient matrix; the matrix multiplication unit is called in the first thread and the third thread to execute matrix multiplication, the vector calculation unit is called in the second thread to execute vector calculation, and the data carrying unit is called in the idle first thread or third thread to obtain each matrix. Through the application, the operation performance of the chip can be improved.

The present application relates to the technical field of data security, in particular to a serialization traceability data verification method based on block chain, comprising: collecting physical features of labeling and packaging equipment to generate a dynamic capture pulse entropy source, and constructing a label sequence identity coupling fingerprint containing instruction stream bias and physical state texture; combining traceability code and action time offset to perform XOR packaging to generate label sequence instantaneous credentials, and introducing historical feedback values to generate label sequence topology entropy chain through hash iteration; using distributed ledger consensus nodes to analyze the entropy chain, verifying the extracted logical feature vector and hardware base state characteristics, comparing the global state root closed loop to generate a logical anchor credential, and triggering asynchronous evidence storage accordingly. Through the deep coupling of physical entropy source and recursive topology chain, the present application realizes cross-dimensional verification of equipment identity, action timing, and physical terminal and block chain nodes, ensuring the authenticity and non-tamperability of traceability data in the generation and circulation process.

Extraction across a predicted employed branch instruction in an extraction beam of a processor-based device is disclosed. In an exemplary aspect, a processor-based apparatus includes instruction processing circuitry configured to process a stream of instructions in an instruction pipeline. The instruction processing circuitry includes instruction fetch circuitry configured to generate a fetch bundle including a plurality of fetched instructions from the instruction stream, where a last fetched instruction of the plurality of fetched instructions is a branch instruction predicted to be taken. The instruction processing circuitry is further configured to identify the plurality of extracted instructions as loop iterations. The instruction processing circuitry is further configured to determine that at least one loop iteration copy is adapted to be placed within the fetch beam. The instruction processing circuitry is additionally configured to store the at least one loop iteration copy within the fetch beam in response to determining that the at least one loop iteration copy is adapted to be placed within the fetch beam.

An accelerator circuit includes a control interface to receive a stream of instructions, a first memory to store an input data, and an engine circuit. The engine circuit includes a dispatch circuit to decode an instruction of the stream of instructions into a plurality of commands and a plurality of queue circuits. Each of the plurality of queue circuits supports a queue data structure to store a respective one of the plurality of commands decoded from the instruction, and a plurality of command execution circuits. Each of the plurality of command execution circuits is to receive and execute a command extracted from a corresponding one of the plurality of queues.

The application discloses a three-dimensional stacked chip testing method based on multi-interface cooperation and parallel broadcasting, and relates to the technical field of integrated circuit testing.The method sets a USB controller on a master control chip layer to preload 116 bit testing instruction streams to a PRO_RAM on the chip;the states of each layer are configured by issuing instructions through JTAG;then, a coordinator FSM runs in a three-stage pipeline mode of instruction fetching, broadcasting and executing, instruction parameters are synchronously distributed to BIST controllers of target layers by using a source fan-out broadcasting bus;by introducing physically isolated shadow registers and active registers in the BIST controllers, the next group of instructions are prefetched and loaded in the background while the current task scanning and shifting are performed, and zero-bubble task switching is achieved;the application effectively reduces the transmission amount of repeated instructions, eliminates the time domain coupling of configuration and execution in the traditional architecture, and significantly improves the testing efficiency of the heterogeneous stacked chip.

The invention relates to the technical field of laser-assisted milling machining, and discloses a modularized self-adaptive laser-assisted machining device and method.The modularized self-adaptive laser-assisted machining device comprises a data acquisition module used for acquiring the three-dimensional shape of a workpiece before machining and acquiring physical parameters of the workpiece in the machining process; the electromechanical execution module is used for controlling the laser to pass through the to-be-machined area in the machining process; the laser light path module is used for emitting laser in the machining process and adjusting physical parameters of the laser; the data processing module is electrically connected with the data acquisition module, the electromechanical execution module and the laser light path module, and the data processing module is used for processing data acquired by the data acquisition module and generating double-path control instruction streams in parallel in a single processing period; and the laser light path module is driven to adjust laser parameters and adjust an advancing strategy of the electromechanical execution module.

The invention discloses a method, a product and a medium used in an AI accelerator chip, and the method comprises the steps: statically dividing a plurality of physical buffer areas in a shared memory of the AI accelerator chip according to a preset pipeline stage, and locking a base address of each physical buffer area in the plurality of physical buffer areas; analyzing calculation and memory allocation logic of operator blocks of the AI model, and inserting a synchronization token on one or more intermediate representation nodes of the AI model based on an analysis result, the synchronization token inserted into any intermediate representation node contains information about a synchronization dependency relationship of hardware operation represented by the intermediate representation node in a physical pipeline executed by a hardware engine in the AI accelerator chip; and generating a hardware instruction stream based on the intermediate representation of the AI model, and interleaving and rearranging instruction blocks in the hardware instruction stream based on a synchronization token inserted on one or more intermediate representation nodes.

The invention relates to a hardware accelerator VTA model deployment scheme support extension method and device, electronic equipment and a storage medium. The method comprises the steps that a pre-training model is imported into a deep learning compiler, a hardware accelerator is used as a target operation model to compile and generate a low-level intermediate representation, the hardware accelerator compiles and generates an operation environment, and the hardware accelerator receives the introduced low-level intermediate representation and generates an instruction stream; processing the instruction flow queue, and driving a model reasoning process on hardware; and the hardware accelerator calculates the input and weight data loaded to the on-chip cache to obtain a reasoning result of the model, and post-processes the reasoning result of the model and generates a visual result for output. According to the method, the model reasoning efficiency on the target hardware platform is improved, the logic completeness of the design during the running of the hardware accelerator VTA is improved, and the generalization degree of the hardware accelerator VTA is improved.

The invention relates to a multi-thread dynamic task scheduling circuit, a computing chip and a computing system, which are integrated in a parallel computing chip, and comprise a plurality of thread management units which are respectively used for storing context information of each task thread, reading an instruction stream from a memory through an internal instruction reading and transmitting unit, and decoding and transmitting the instruction stream; the arithmetic logic unit is used for executing arithmetic and logic operation instructions of the thread management unit so as to realize dynamic parameter derivation during operation; the task distribution unit is used for arbitrating the task configuration information transmitted by the plurality of thread management units and distributing the task configuration information to each processing unit in the chip; and the synchronization unit is used for synchronizing primitives through hardware so as to realize synchronization among the plurality of thread management units and synchronization between the thread management units and the processing unit. Each thread is programmable and adapts to complex scenes such as dynamic image sizes and dynamic calculation processes.