98 results about "Power domains" patented technology

The invention provides a kernel control method and device and electronic equipment. Relates to the technical field of inner cores. The method comprises the following steps: acquiring inner core state information of an inner core under the condition of processing a current thread; determining a target running state of the kernel in response to the condition that the kernel state information meets a set control condition or a running control instruction for the kernel is received; the target operation state comprises a target operation state of a power domain and / or a target operation state of a clock domain of the kernel; the power consumption corresponding to the target operation state is smaller than the power consumption of the kernel in a normal operation state; and determining an adjustment signal corresponding to the kernel based on the target operation state, and sending the adjustment signal to a power domain and / or a clock domain of the kernel so as to control the operation state of the kernel. According to the invention, the fineness of power consumption management can be improved, and the flexibility of kernel control in a low power consumption mode can be improved.

The invention provides a power domain control software architecture and a controller thereof, the software architecture comprises an application layer developed based on an AUTOSAR standard, a runtime environment and a basic software layer, the application layer comprises a plurality of modularized software components, the software components package service logic functions of the controller to be integrated, the software components are provided with an AUTOSAR-based ARXML file definition interface, and the AUTOSAR-based ARXML file definition interface is used for defining the service logic functions of the controller to be integrated. According to the method, the interface compatibility can be improved, seamless integration of application layers across controllers can be realized, and the development parallelism is enhanced by kernel deployment of independently packaged software components according to the real-time performance of functions. The runtime environment generates an inter-core communication agent code, constructs a virtual bus and routes a service request of an application layer component to the basic software layer, and the basic software layer provides system-level service for the application layer through a virtual bus interface of the runtime environment, so that the application layer does not need to directly operate hardware, software and hardware decoupling is realized, and the service performance of the application layer is improved. And smooth realization of software fusion and integration is promoted.

The present invention belongs to the technical field of power natural language data question answering, and specifically relates to a method for enhancing NL2SQL questions driven by multi-source knowledge links. The method includes: constructing a power data schema using database table information and sorting out power domain knowledge; constructing a question parsing Prompt template and using a large language model to analyze the structure of the original question to extract key entities from the original question; retrieving power domain knowledge in a hybrid similarity retrieval manner based on the sorted out power domain knowledge and the key entities extracted from the original question; obtaining database tables and data schemas related to the original question through a multi-level schema linking method; standardizing knowledge and designing a question enhancement Prompt template based on the retrieved power domain knowledge and the obtained data schema, and using a large language model to reconstruct and enhance the original question to eliminate confusion and interference factors and improve the accuracy of question answering.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

The invention discloses a design information generation method and device of an intellectual property core, electronic equipment and a medium. The method comprises the steps that input design associated information of the intellectual property core is acquired; determining a current design direction type according to the design association information; according to the design direction type and a port signal naming rule of a preset template library, a standardized top-layer code is generated, and the standardized top-layer code comprises standardized signal code information, a standardized time sequence constraint file and a standardized power domain constraint file. According to the embodiment of the invention, based on a design direction type and a port signal naming rule of a preset template library, port naming standardization is automatically carried out on top-layer codes: signal code information, a time sequence constraint file and a power domain constraint file, so that the problem that design information such as top-layer HDL codes, instantiation codes and SDC, UPF and the like of a current digital IP needs to be written manually is solved; time and labor are consumed, efficiency is low, and errors are prone to occurring.

Systems and methods for power management of Out-of-Band (OOB) processors in heterogeneous computing platforms. In some embodiments, a heterogeneous computing platform may include: a first, low-power domain including a first set of one or more devices, where the first, low-power power domain is configured to receive a first voltage supply during an Out-of-Band (OOB) packet sniffing operation while a second set of one or more devices is in a low-power state; and a second, high-power domain including the second set of one or more devices, where the second, high-power domain is configured to receive a second voltage supply under control of at least one of the first set of one or more devices.

The invention provides a low-power-consumption SOC optimization method and system. The method comprises the following steps: periodically sampling interface states of a plurality of interfaces; periodically determining a joint weight, wherein the joint weight is used for indicating the relevance among the interfaces; determining the relevance between the interfaces and the behaviors based on the corresponding relation between the interface states of the plurality of historical interfaces and the actual behaviors; determining a prediction behavior of the current period based on the relevance between the interface and the behavior, the interface state of the current period and the joint weight of the current period; and determining a target clock domain and a target power supply domain based on the prediction behavior of the current period, the first corresponding relation and the second corresponding relation, and triggering a control strategy of a power supply and a clock based on the target clock domain and the target power supply domain. Under different working modes, power supply, clock and data storage strategies of multiple modules are dynamically coordinated, system-level power consumption optimization is achieved, and meanwhile rapid wakeup and data integrity are ensured.

The invention provides a power supply abnormity processing method and device, electronic equipment and a readable storage medium. The method comprises the following steps: in response to a detection request for a power supply state of a target module, matching a target state of a power-on and power-off state machine of the target module with a first feedback signal of a power domain of the target module to obtain a first matching result; when the first matching result represents that the first feedback signal is not matched with the target state, executing an operation corresponding to the target state on the power domain to obtain a second feedback signal of the power domain; matching the target state with the second feedback signal to obtain a second matching result; when the second matching result represents that the second feedback signal is not matched with the target state, the first matching result and the second matching result are sent to the central controller; and performing power supply exception processing on the target module based on the exception solution issued by the central controller. According to the invention, real-time detection and rapid processing of power supply abnormity can be realized.

The invention discloses a dynamic multi-domain power consumption regulation-based ultra-low power consumption design method for an AI voice chip. The method comprises the following steps of 1, designing a chip power supply scheme and a clock scheme according to an application scene of a system; 2, designing a multi-level layered clock gating architecture control system; step 3, dividing the power supply network into a dynamic power supply domain and a normally open power supply domain; step 4, cache compression design of voice data is carried out; step 5, minimum addressable unit grouping optimization is carried out on a memory, and minimum addressable units with different granularities are supported to implement selective turn-off; and step 6, completing the design after the simulation is passed and an expected target is reached. Through a hierarchical gating layer design method, bidirectional optimization of dynamic energy efficiency management and time sequence precision is realized, and the overall clock power consumption is reduced.

The application provides a content management and control method, device and equipment based on end-side cooperation, which comprises the following steps: determining the number of devices corresponding to each to-be-deployed model; determining the number of computing power domains corresponding to each to-be-deployed model based on the total number of end-side devices and the number of devices corresponding to each to-be-deployed model; sequentially traversing each to-be-deployed model as a current to-be-deployed model, and obtaining K computing power domains corresponding to the current to-be-deployed model; splitting the current to-be-deployed model into M sub-models; deploying the M sub-models to M end-side devices of each computing power domain; obtaining a computing power graph of the current to-be-deployed model; and when any to-be-deployed model is used for abnormality detection, the computing power graph of the to-be-deployed model is used for abnormality detection of to-be-detected content to obtain an abnormality detection result. Through the technical scheme of the application, computing resources can be fully cooperatively utilized, and abnormality detection can be efficiently completed. The computing resources of the end-side devices can be reasonably allocated.

The invention discloses an expansion board and a server, and relates to the technical field of servers, and the expansion board can comprise a logic controller, at least one power domain and at least one memory. Wherein the power domains and the memories are in one-to-one correspondence, the power domains can comprise a plurality of retimers and a plurality of level translators, the level translators can be connected with the retimers in one-to-one correspondence, and correspondingly, the retimers belonging to one power domain can share one memory. Thus, a plurality of retimers can share one memory, the number of memories is greatly reduced, hardware resources can be saved, and hardware cost is reduced. In addition, in the firmware upgrading or modifying process, the number of memories needing to be burnt and verified is greatly reduced, the operation and maintenance complexity is reduced, and then the time cost is also reduced. In conclusion, a plurality of re-timers share one memory, so that the cost can be reduced.

A dual-power domain SRAM is disclosed in which the dual power domains can be powered up or down in any desired order. For example, the (CX) power domain can be powered up first, followed by the memory (MX) power domain. Conversely, the MX power domain can be powered up before the CX domain.

A device includes a plurality of hardware blocks and an interconnect network to interconnect the plurality of hardware blocks, where the interconnect network includes a memory-based cross-domain solutions (M-CDS) device. The M-CDS device includes a shared memory region and a cross-domain solutions (CDS) manager to create a buffer in the shared memory region to restrict transmission of data through the buffer to a given hardware block in the plurality of hardware blocks based on a configuration of the buffer, where the buffer is to temporarily hide presence of the given hardware block on the interconnect from an operating environment.

A high availability controller for combining and unifying aspects of a process controller and an electrical controller. A unified namespace combines a process domain namespace and a power domain namespace in a common database of the controller without altering either. The unified namespace maps source device names of the power domain and unique process control names of the process domain. A common record set of sequence of events (SOEs) for the process domain and the power domain is generated and SOEs arising from the power domain are incorporated into the common record set. The controller performs process control and monitoring along with electrical control signaling and monitoring within a single control strategy directly from the controller.

The invention relates to the field of cell antenna factor calibration, in particular to a power domain estimation method and device based on GTEM cell antenna factor calibration. The scheme comprises the following steps: determining a working frequency band according to application requirements, and selecting a plurality of calibration frequency points in the working frequency band; performing reference field intensity calibration on each selected calibration frequency point; measuring an initial azimuth angle based on the GTEM cell; measuring noise power, and establishing a noise power matrix; measuring the receiving power under the full angle; subtracting the corresponding noise power from the measured receiving power to obtain net signal power; calculating an antenna factor of the antenna under the current set angle and the calibration frequency point according to the antenna factor definition; and finally, calibrating and verifying the antenna factors. The method is suitable for power domain estimation based on GTEM cell antenna factor calibration.

Systems, methods, and devices provide efficient wake operations and boot times for electronic devices. Methods include initiating, using one or more processing elements, a boot operation associated with a plurality of power domains, and determining, using the one or more processing elements, a type of the boot operation based, at least in part, on current status information identifying a current status of each of the plurality of power domains. Methods further include determining, using the one or more processing elements, one or more authentication operations based, at least in part, on the type of boot operation and a configuration of the plurality of power domains being booted, performing, using the one or more processing elements, the one or more authentication operations prior to booting the power domain.

The application provides a three-phase imbalance treatment method based on a fuzzy biased particle swarm optimization algorithm. The three-phase imbalance treatment method based on the fuzzy biased particle swarm optimization algorithm comprises the following steps: constructing a four-phase node admittance matrix equation corresponding to three-phase nodes and a neutral node, solving the admittance matrix equation based on the admittance matrix parameters of a circuit system to obtain electrical basic data of nodes of the circuit system; based on the electrical basic data, deducing, converting three-phase imbalance of the circuit system from a current domain to a power domain, and obtaining an evaluation value of three-phase current imbalance; determining a constraint threshold value of the evaluation value based on a preset power quality standard; constructing a target optimization function based on a constraint condition corresponding to the evaluation value; constructing a multi-dimensional constraint comprising a power grid safety constraint, a device operation constraint and a power balance constraint; initializing a plurality of candidate power scheduling schemes based on power supply output data and load data; and based on the constraint threshold value of the evaluation value and the multi-dimensional constraint, iteratively optimizing the plurality of candidate power scheduling schemes to obtain a target scheduling scheme of the circuit system. The application can improve the accuracy of the three-phase imbalance treatment based on the fuzzy biased particle swarm optimization algorithm.

A circuit portion comprises a mapping module, a source component, a destination component and a memory. The mapping module comprises a plurality of channels that each provides a connection for connecting two components of the circuit portion in a one-to-one relationship. The source component is arranged in a first clock or power domain, and the destination component is arranged in a second clock or power domain. In response to an assertion of an event signal or an interrupt by the source component, the mapping module is configured to forward the event signal or interrupt to the destination component via only one channel of the plurality of channels so as to cause the destination component to perform a corresponding task according to a mapping stored in the memory.

This invention discloses a method and system for automatic extraction and knowledge construction of data quality rules for power equipment, belonging to the fields of artificial intelligence and power data governance technology. To address the problems of low parsing accuracy of complex tables in power technology standard documents, lack of physical constraint verification of extraction results, and catastrophic forgetting of models due to standard updates, this invention utilizes a multimodal large language model to parse documents. A structured document object model is obtained through hierarchical table structure encoding, cross-page context preservation, and semantic binding of table annotations. The large language model, fine-tuned with domain knowledge, extracts entity relationships and performs consistency verification in conjunction with a physical constraint knowledge base in the power domain. The verified entity relationships are assembled into structured quality rule records and stored in a graph database. A differential-adaptive elastic weight consolidation strategy is employed for continuous learning, combined with a human-machine collaborative quality inspection optimization model, achieving high-precision complex table parsing, physical consistency verification, and anti-forgetting continuous learning.

According to an embodiment, a method for debugging a low-power domain in a multi-power domain device is disclosed. The method includes mapping a critical signal of the low-power domain to a latch circuit of a register bank; capturing, by the latch circuit, transitions of the critical signal in registers of the register bank; observing, by a core circuit in a switchable power domain of the multi-power domain device, registers of the register bank; and determining a fault corresponding to the critical signal based on a value of the registers of the register bank.

The invention provides a multi-power domain chip timing sequence adaptive test system and test method, the system comprises a plurality of timing sequence test devices, each timing sequence test device is connected with a GPU chip, the models of all GPU chips are the same, and each timing sequence test device comprises a timing sequence control module, a timing sequence detection module and a result analysis module. A test scheme of the time sequence test device is formulated according to the test states of the time sequence test device and other simultaneous test time sequence test devices, and a plurality of time sequence test devices are adopted to test the GPU chip at the same time, so that the time sequence test efficiency of the multi-power-domain GPU chip is improved; during testing, the power-on sequence and the rising time delay of the time sequence of the multi-power-domain GPU chip are evaluated, and time sequence parameters of the GPU chip are analyzed more comprehensively; and testing is carried out in a normal working state of the GPU chip, so that the time sequence parameters of the chip in an actual application scene are reflected more accurately.

A system and method for designing a programmable sequencer capable of modifying power up and power down sequences for power control in a power domain using a no-code approach. According to one embodiment, the system includes a memory to store at least one instruction, a component storage configured to store power component information and instruction component information, a code logic storage configured to store software code logic for generating executable code based on an instruction instance, and at least one processor configured to execute the stored instruction(s). The instruction(s) include operations for generating at least one power instance based on a power component, generating a first instruction instance based on an instruction component, determining a target power instance among the generated power instances and setting a value, and generating code including an instruction, a register address, and data based on the instruction instance, the target power instance, and the value.

This invention relates to the field of intelligent power system technology, and discloses a method, system equipment, and medium for injecting knowledge into the power field. The method includes employing a hierarchical hybrid sparse expert model and a cyclic knowledge distillation framework. This is achieved by reconstructing the large model architecture into a hybrid expert layer containing a general expert network and a power field expert network. A progressive gating activation mechanism is used to dynamically select and combine relevant expert networks. A cyclic knowledge distillation process is constructed using forward knowledge transfer and backward knowledge correction. Combined with a knowledge compensation network, supplementary training samples are automatically generated after identifying weak areas in the model's knowledge, enabling continuous optimization and evolution of the model. This invention achieves efficient injection of knowledge into the power field, significantly reducing training and inference resource consumption and improving inference speed while ensuring diagnostic accuracy and solution generation quality. It is suitable for power application scenarios such as intelligent diagnosis and management of distribution network problems.

Systems, methods, and devices provide management of power domains. Methods include activating a first power domain of a memory controller in response to receiving a memory command associated with a storage location coupled to the memory controller, and performing a first portion of a sequence of operations determined based on the memory command, the first portion being performed using a first plurality of processing elements included in the first power domain. Methods further include activating a second power domain of the memory controller based on a timing determined by the sequence of operations, and performing a second portion of the sequence of operations using a second plurality of processing elements included in the second power domain.

The invention discloses a power domain modulation method, a demodulation method, a modulation system and a demodulation system in the technical field of optical fiber communication. The modulation method comprises the following steps: generating three groups of chaos sequences A, B and C by using a Lorenz chaos model; performing triple encryption and orthogonal decomposition on the original data by using the three groups of chaos sequences A, B and C to obtain a third layer of encrypted constellation and a 3D-8symbol constellation; converting a key of the Lorenz chaos model into a binary system, mapping the binary system to a 1D constellation, and superposing the 1D constellation with a third layer of encrypted constellation to obtain a 2D-QPSK constellation; the method comprises the following steps: carrying out dimension transformation on a 2D-QPSK constellation on a symbol coordinate dimension, supplementing a dimension with a coordinate of 0 for the 2D-QPSK constellation to obtain a 3D-4symbol constellation, and then carrying out PDM modulation on the 3D-4symbol constellation and a 3D-8symbol constellation to obtain a transmission signal. The method has high security and accuracy for encryption of high-dimensional constellations, and has low complexity at the same time.

The invention provides a netlist detection method and device, equipment and a storage medium, and relates to the technical field of computers. According to the implementation scheme, in response to a power gating PG netlist detection request for a target power domain, a PG netlist of the target power domain and a unified power format UPF file are obtained, and the UPF file is provided with an isolation strategy for a port signal of the target power domain; on the basis of an isolation strategy in the UPF file, first isolation units in the PG netlist are detected, second isolation units with integration errors are obtained, and the first isolation units are isolation units integrated for port signals of the target power domain; and determining a PG netlist detection result of the target power domain based on the position information of the second isolation unit in the PG netlist. By adopting the method and the device, the verification efficiency of the PG netlist can be improved.

1. Name of the Design Product: Power Domain Controller (FZPDCU33N25S5). 2. Use of the Design Product: Used for controlling power systems powered by electricity. 3. Design Key Points of the Design Product: Lies in the shape. 4. Picture or Photograph that Best Illustrates the Design Key Points: Perspective View 1.

The invention discloses a redundant power domain cooperative scheduling method and related equipment, and relates to the technical field of power grids, and the method comprises the steps: dynamically collecting state data, peripheral power consumption demand data, environment and heat dissipation data and system-level data of multiple power domains; based on the peripheral power consumption demand data and the state data, executing a dynamic power consumption distribution algorithm to generate a preliminary power consumption distribution scheme; performing heat dissipation compensation adjustment on the initial power consumption distribution scheme in combination with environment and heat dissipation data, and generating a temperature-optimized target power consumption distribution scheme; inputting the target power consumption distribution scheme into the thermoelectric coupling model, solving a coupling equation of electrical parameters and thermal parameters, and outputting a globally optimized power distribution strategy; a power domain fault flag is monitored based on system-level data, and when a fault is detected, a redundant power seamless switching mechanism is triggered based on a power distribution strategy. Through priority weighted distribution and thermal compensation linkage, the power domain utilization rate is improved, and peripheral performance fluctuation is effectively reduced.

The invention discloses a communication method of a power domain non-orthogonal multiple access system based on a symmetric Hamming distance constellation and a related device, and the method comprises the steps: carrying out the coding and bit interleaving processing of information bit sequences of two users, and obtaining corresponding bit interleaving sequences; modulating the bit interleaving sequence to obtain a corresponding modulation symbol sequence, and determining transmission power; based on the symmetric Hamming distance, determining a mutual constellation arrangement function according to the modulation orders of the modulation symbol sequences of the two users; based on a mutual constellation arrangement function, performing mapping superposition according to the modulation symbol sequence and the transmission power through a joint constellation mapper to obtain a superposed symbol sequence; transmitting the superposed symbol sequence through a transmission channel to obtain a received signal; and decoding the received signal by adopting an iterative soft demodulation and decoding mode, and recovering the decoding bit sequences of the first user and the second user. According to the method, the correlation between the users is established based on the mutual constellation arrangement function to reduce the interference between different user constellations.