138 results about "Power domains" patented technology

The invention relates to the technical field of pre-silicon verification, and discloses an isolation function verification method, device and system, and the method comprises the steps: obtaining the hierarchical structure information of a power domain module in a to-be-tested chip; determining isolation definition information of the power domain module, and identifying an isolation signal type from the isolation definition information; determining a target internal port signal corresponding to the isolation signal type in the hierarchical structure information, and judging whether to perform mapping processing on the target internal port signal based on the signal mapping information according to the isolation signal type; and generating at least one assertion of a target isolation function verification signal according to the target isolation function verification signal represented by the judgment result, and performing isolation function verification on the power domain module based on the generated assertion. According to the technical scheme provided by one or more embodiments, the check assertion can be automatically and efficiently generated to verify the chip.

The invention relates to a communication equipment optimization method and device based on power management. The method comprises the following steps: performing delay power consumption domain transformation and minimum mean square error power equalization processing on power consumption data of communication equipment to obtain power consumption characteristic data; inputting a heterogeneous equipment management neural network to carry out power management prediction to obtain an equipment power consumption prediction parameter; deploying a virtual power supply manager and executing power supply response control on the communication base station and the standby power supply to obtain power supply adjustment parameters; constructing an equipment power consumption scheduling matrix, and performing equalization optimization on the equipment power consumption scheduling matrix by adopting a block iteration mode to obtain a multi-equipment power consumption scheduling scheme; and executing power distribution control according to the multi-device power consumption scheduling scheme, generating an initial power distribution strategy, and dynamically adjusting the initial power distribution strategy through a three-layer Bayesian network model to obtain a target power distribution strategy. According to the invention, the accuracy and adaptive capability of power distribution are improved.

The invention provides a kernel control method and device and electronic equipment. Relates to the technical field of inner cores. The method comprises the following steps: acquiring inner core state information of an inner core under the condition of processing a current thread; determining a target running state of the kernel in response to the condition that the kernel state information meets a set control condition or a running control instruction for the kernel is received; the target operation state comprises a target operation state of a power domain and / or a target operation state of a clock domain of the kernel; the power consumption corresponding to the target operation state is smaller than the power consumption of the kernel in a normal operation state; and determining an adjustment signal corresponding to the kernel based on the target operation state, and sending the adjustment signal to a power domain and / or a clock domain of the kernel so as to control the operation state of the kernel. According to the invention, the fineness of power consumption management can be improved, and the flexibility of kernel control in a low power consumption mode can be improved.

The invention provides a power domain control software architecture and a controller thereof, the software architecture comprises an application layer developed based on an AUTOSAR standard, a runtime environment and a basic software layer, the application layer comprises a plurality of modularized software components, the software components package service logic functions of the controller to be integrated, the software components are provided with an AUTOSAR-based ARXML file definition interface, and the AUTOSAR-based ARXML file definition interface is used for defining the service logic functions of the controller to be integrated. According to the method, the interface compatibility can be improved, seamless integration of application layers across controllers can be realized, and the development parallelism is enhanced by kernel deployment of independently packaged software components according to the real-time performance of functions. The runtime environment generates an inter-core communication agent code, constructs a virtual bus and routes a service request of an application layer component to the basic software layer, and the basic software layer provides system-level service for the application layer through a virtual bus interface of the runtime environment, so that the application layer does not need to directly operate hardware, software and hardware decoupling is realized, and the service performance of the application layer is improved. And smooth realization of software fusion and integration is promoted.

The invention discloses a coding method and device based on power domain chaotic distribution matching. The method comprises the following steps: acquiring a key initial value and to-be-sent original data; performing chaotic encryption on the key initial value through a Chua's chaotic system to generate a chaotic sequence; carrying out system conversion on the key initial value, and carrying out mapping processing according to a rule to obtain a key stream formed by a QPSK constellation diagram; performing encryption and serial-to-parallel conversion on original data in a binary form by using the chaos sequence, and then performing quadrature phase shift keying (QPSK) mapping to obtain an information stream formed by uniformly distributed QPSK constellation diagrams; respectively carrying out power distribution on the key stream and the information stream, and carrying out constellation diagram superposition on the key stream and the information stream after power distribution to form an encrypted stream of a non-uniformly distributed 16 QAM constellation diagram; and performing translation rotation on each region of the partitioned constellation diagram of the encrypted stream according to a rule, and finally realizing probabilistic shaping to obtain the PS-16QAM constellation diagram encrypted stream. The method can improve the quality of signal transmission.

A method for wireless communication at a user equipment (UE) and related apparatus are provided. In the method, the UE receives, from a network entity, a channel state information (CSI) report configuration including a set of sub-configurations. Each sub-configuration in the set of sub-configurations corresponds to a transmission setting associated with a channel state information reference signal (CSI-RS). The UE further determines one or more CSIs respectively corresponding to a subset of the set of sub-configurations, and transmits, based on the transmission setting corresponding a first sub-configuration of the subset of sub-configurations, a reduced content of a CSI report or refrains from transmitting the CSI report. The CSI report is associated with a first CSI for the first sub-configuration.

Systems and methods for kill pill management in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform having a plurality of devices and an Embedded Controller (EC) integrated into or coupled to the heterogeneous computing platform, where the EC is configured to receive a kill pill command, and, in response to the kill pill command, at least one of: (i) turn off one or more power domains and set a flag that prevents the one or more power domains from being turned on, or (ii) erase one or more portions of a storage device.

The invention provides a software integration method and a software management system of a power domain controller, and belongs to the field of automobiles, the method comprises the following steps: generating an ARXML file based on a variable data type and a system transfer function interface defined in a software architecture; based on the ARXML file, generating a code file of the basic software; based on the ARXML file, a code file of the application software is generated, and the code file of the application software is matched with the software interface described by the ARXML file; based on the ARXML file, a code file of a middle layer is generated, the middle layer is used for connecting the basic software and the application software, and the code file of the middle layer is matched with the software interface described by the ARXML file; and performing integrated compiling on the code file of the basic software, the code file of the middle layer and the code file of the application software to obtain an executable file. The software integration method and device can be compatible with various modes for software development, rapid integration of the software is facilitated, and the software integration efficiency is improved.

The present invention belongs to the technical field of power natural language data question answering, and specifically relates to a method for enhancing NL2SQL questions driven by multi-source knowledge links. The method includes: constructing a power data schema using database table information and sorting out power domain knowledge; constructing a question parsing Prompt template and using a large language model to analyze the structure of the original question to extract key entities from the original question; retrieving power domain knowledge in a hybrid similarity retrieval manner based on the sorted out power domain knowledge and the key entities extracted from the original question; obtaining database tables and data schemas related to the original question through a multi-level schema linking method; standardizing knowledge and designing a question enhancement Prompt template based on the retrieved power domain knowledge and the obtained data schema, and using a large language model to reconstruct and enhance the original question to eliminate confusion and interference factors and improve the accuracy of question answering.

The invention belongs to the technical field of power grid regulation and control, and particularly relates to a power grid demand side resource adjustable power domain aggregation method and device. The method comprises the following steps: S1, constructing adjustable power domains of various demand side resources containing time sequence coupling characteristic constraints, and representing the adjustable power domains of the demand side resources in adjacent time periods by using time-segmented linear boundary constraints; s2, establishing a demand side resource comprehensive probability model containing various correlations according to historical data of various demand side resources; and S3, constructing an adjustable power domain aggregation model of the demand side resources in combination with the linear boundary constraint and the comprehensive probability model, and obtaining a flexibility decision space of the demand side resources through model optimization. According to the scheme, the linear constraint of each demand side resource and the correlation constraint between the demand side resources are considered at the same time, the obtained feasible region is finer, the supply and demand regulation and control effect of the new energy transformer area is improved, and the stability and safety of a power grid are improved.

Provided are systems, methods, and apparatuses for obtaining first data of a power domain of a system on chip and second data of the power domain, predicting an expected power for the power domain based on the first data and the second data, and applying to the power domain a power level that is selected based on the expected power. The first data is utilization data. The second data is thermal data that includes at least one of a spatial thermal limit or a positional thermal limit of the power domain. The spatial thermal limit is based on at least one of a proximity of the power domain to a component outside the power domain or a power level of the component at a time when the expected power is calculated. The positional thermal limit is based on a location of the power domain on the system on chip.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

Methods and systems involving automotive computing architectures with phased wake sequences and power control are disclosed herein. A disclosed automotive computing system includes at least three subsystems: a first subsystem that is in an always-on power domain, a second subsystem that is powered on from a sleep state in response to an event detected by the first subsystem, and a third subsystem that is powered on, from an off state, after the first subsystem and the second subsystem are powered on. The subsystems of the architecture can be activated in different phases based on a given scenario in which the automotive computing architecture is operating. The same subsystem can occupy a different phase in different scenarios. The phased wake sequences may conserve power without sacrificing utility and may be optimized for different scenarios and triggering events.

Methods, systems, and apparatus, for implementing a save-restore engine in a computing device. One of the apparatus includes a power manager configured to control power provided to a plurality of power domains on the device, wherein each power domain has a respective client device, wherein each respective client device has a respective access control (AC) component that is configured to control which other components on the device can communicate with the respective client device; and a save-restore engine (SRE) configured to save, in an isolated local memory, configuration data for an AC component located in a power domain affected by the power manager initiating a power collapse operation, and wherein the SRE is configured to restore, from the isolated local memory, the configuration data of the AC component when the power manager restores the power to the power domain of the AC component.

The invention discloses a design information generation method and device of an intellectual property core, electronic equipment and a medium. The method comprises the steps that input design associated information of the intellectual property core is acquired; determining a current design direction type according to the design association information; according to the design direction type and a port signal naming rule of a preset template library, a standardized top-layer code is generated, and the standardized top-layer code comprises standardized signal code information, a standardized time sequence constraint file and a standardized power domain constraint file. According to the embodiment of the invention, based on a design direction type and a port signal naming rule of a preset template library, port naming standardization is automatically carried out on top-layer codes: signal code information, a time sequence constraint file and a power domain constraint file, so that the problem that design information such as top-layer HDL codes, instantiation codes and SDC, UPF and the like of a current digital IP needs to be written manually is solved; time and labor are consumed, efficiency is low, and errors are prone to occurring.

An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.

A high availability controller for combining and unifying aspects of a process controller and an electrical controller. A unified namespace combines a process domain namespace and a power domain namespace in a common database of the controller without altering either. The unified namespace maps source device names of the power domain and unique process control names of the process domain. A common record set of sequence of events (SOEs) for the process domain and the power domain is generated and SOEs arising from the power domain are incorporated into the common record set. The controller performs process control and monitoring along with electrical control signaling and monitoring within a single control strategy directly from the controller.

Systems and methods for power management of Out-of-Band (OOB) processors in heterogeneous computing platforms. In some embodiments, a heterogeneous computing platform may include: a first, low-power domain including a first set of one or more devices, where the first, low-power power domain is configured to receive a first voltage supply during an Out-of-Band (OOB) packet sniffing operation while a second set of one or more devices is in a low-power state; and a second, high-power domain including the second set of one or more devices, where the second, high-power domain is configured to receive a second voltage supply under control of at least one of the first set of one or more devices.

Systems and methods for power management of Out-of-Band (OOB) processors in heterogeneous computing platforms. In some embodiments, a heterogeneous computing platform may include: a first, low-power domain including a first set of one or more devices, where the first, low-power power domain is configured to receive a first voltage supply during an Out-of-Band (OOB) packet sniffing operation while a second set of one or more devices is in a low-power state; and a second, high-power domain including the second set of one or more devices, where the second, high-power domain is configured to receive a second voltage supply under control of at least one of the first set of one or more devices.

The utility model provides a test system based on a power domain controller CAN communication matrix. The test system comprises an upper computer and a test vehicle. The test vehicle is provided with a power domain controller and a CAN board card. The upper computer is configured with a simulink interface; the upper computer is in communication connection with the power domain controller through the simulink interface and the CAN board card; and the upper computer tests the test vehicle based on the CAN communication matrix, the dbc file and the power domain controller. According to the utility model, CAN signal transceiving of a real vehicle can be simulated, and the test accuracy is improved. According to the utility model, the vehicle controller can be comprehensively tested, the test requirements are met, the purpose of measurement test is achieved, the vehicle controller can be manually tested or automatically tested to meet various test scenes, and the test efficiency is improved.

The invention provides a low-power-consumption SOC optimization method and system. The method comprises the following steps: periodically sampling interface states of a plurality of interfaces; periodically determining a joint weight, wherein the joint weight is used for indicating the relevance among the interfaces; determining the relevance between the interfaces and the behaviors based on the corresponding relation between the interface states of the plurality of historical interfaces and the actual behaviors; determining a prediction behavior of the current period based on the relevance between the interface and the behavior, the interface state of the current period and the joint weight of the current period; and determining a target clock domain and a target power supply domain based on the prediction behavior of the current period, the first corresponding relation and the second corresponding relation, and triggering a control strategy of a power supply and a clock based on the target clock domain and the target power supply domain. Under different working modes, power supply, clock and data storage strategies of multiple modules are dynamically coordinated, system-level power consumption optimization is achieved, and meanwhile rapid wakeup and data integrity are ensured.

The invention provides a power supply abnormity processing method and device, electronic equipment and a readable storage medium. The method comprises the following steps: in response to a detection request for a power supply state of a target module, matching a target state of a power-on and power-off state machine of the target module with a first feedback signal of a power domain of the target module to obtain a first matching result; when the first matching result represents that the first feedback signal is not matched with the target state, executing an operation corresponding to the target state on the power domain to obtain a second feedback signal of the power domain; matching the target state with the second feedback signal to obtain a second matching result; when the second matching result represents that the second feedback signal is not matched with the target state, the first matching result and the second matching result are sent to the central controller; and performing power supply exception processing on the target module based on the exception solution issued by the central controller. According to the invention, real-time detection and rapid processing of power supply abnormity can be realized.

The invention discloses a dynamic multi-domain power consumption regulation-based ultra-low power consumption design method for an AI voice chip. The method comprises the following steps of 1, designing a chip power supply scheme and a clock scheme according to an application scene of a system; 2, designing a multi-level layered clock gating architecture control system; step 3, dividing the power supply network into a dynamic power supply domain and a normally open power supply domain; step 4, cache compression design of voice data is carried out; step 5, minimum addressable unit grouping optimization is carried out on a memory, and minimum addressable units with different granularities are supported to implement selective turn-off; and step 6, completing the design after the simulation is passed and an expected target is reached. Through a hierarchical gating layer design method, bidirectional optimization of dynamic energy efficiency management and time sequence precision is realized, and the overall clock power consumption is reduced.

The invention discloses a construction method and system of a power domain model, and the method is characterized in that the method comprises the steps: collecting a power text from a power knowledge base, constructing a triple cue word template of a power domain, extracting the power text according to the template content, and constructing an initial power knowledge graph; calculating the degree of the entity so as to generate a first entity fusion strategy according to the position of the entity in the initial electric power knowledge graph; obtaining vectorized representations of the non-edge entities so as to generate a second entity fusion strategy according to the degree of repetition between the non-edge entities; and presetting a convergence condition of the electric power knowledge graph, calculating an entity quantitative index of the electric power knowledge graph in each iteration process of the electric power knowledge graph by using the first entity fusion strategy and the second entity fusion strategy, and if the entity quantitative index meets the convergence condition, generating the electric power domain model.

The invention discloses a power domain energy consumption estimation method and device, equipment and a storage medium, and the method comprises the steps: obtaining the performance information of a power domain in a plurality of scenes in an offline state; determining a power consumption model of the power domain based on the performance information; the power consumption model is used for determining the power consumption of the power domain in the online state. According to the method, the power consumption model of the power domain is determined in the offline state, the power consumption model can be used online for energy consumption estimation, and the efficiency of online estimation of the energy consumption of the power domain is effectively improved.

The application provides a content management and control method, device and equipment based on end-side cooperation, which comprises the following steps: determining the number of devices corresponding to each to-be-deployed model; determining the number of computing power domains corresponding to each to-be-deployed model based on the total number of end-side devices and the number of devices corresponding to each to-be-deployed model; sequentially traversing each to-be-deployed model as a current to-be-deployed model, and obtaining K computing power domains corresponding to the current to-be-deployed model; splitting the current to-be-deployed model into M sub-models; deploying the M sub-models to M end-side devices of each computing power domain; obtaining a computing power graph of the current to-be-deployed model; and when any to-be-deployed model is used for abnormality detection, the computing power graph of the to-be-deployed model is used for abnormality detection of to-be-detected content to obtain an abnormality detection result. Through the technical scheme of the application, computing resources can be fully cooperatively utilized, and abnormality detection can be efficiently completed. The computing resources of the end-side devices can be reasonably allocated.

The invention discloses an expansion board and a server, and relates to the technical field of servers, and the expansion board can comprise a logic controller, at least one power domain and at least one memory. Wherein the power domains and the memories are in one-to-one correspondence, the power domains can comprise a plurality of retimers and a plurality of level translators, the level translators can be connected with the retimers in one-to-one correspondence, and correspondingly, the retimers belonging to one power domain can share one memory. Thus, a plurality of retimers can share one memory, the number of memories is greatly reduced, hardware resources can be saved, and hardware cost is reduced. In addition, in the firmware upgrading or modifying process, the number of memories needing to be burnt and verified is greatly reduced, the operation and maintenance complexity is reduced, and then the time cost is also reduced. In conclusion, a plurality of re-timers share one memory, so that the cost can be reduced.

A dual-power domain SRAM is disclosed in which the dual power domains can be powered up or down in any desired order. For example, the (CX) power domain can be powered up first, followed by the memory (MX) power domain. Conversely, the MX power domain can be powered up before the CX domain.