56 results about "Power domains" patented technology

The invention discloses an expansion board and a server, and relates to the technical field of servers, and the expansion board can comprise a logic controller, at least one power domain and at least one memory. Wherein the power domains and the memories are in one-to-one correspondence, the power domains can comprise a plurality of retimers and a plurality of level translators, the level translators can be connected with the retimers in one-to-one correspondence, and correspondingly, the retimers belonging to one power domain can share one memory. Thus, a plurality of retimers can share one memory, the number of memories is greatly reduced, hardware resources can be saved, and hardware cost is reduced. In addition, in the firmware upgrading or modifying process, the number of memories needing to be burnt and verified is greatly reduced, the operation and maintenance complexity is reduced, and then the time cost is also reduced. In conclusion, a plurality of re-timers share one memory, so that the cost can be reduced.

A high availability controller for combining and unifying aspects of a process controller and an electrical controller. A unified namespace combines a process domain namespace and a power domain namespace in a common database of the controller without altering either. The unified namespace maps source device names of the power domain and unique process control names of the process domain. A common record set of sequence of events (SOEs) for the process domain and the power domain is generated and SOEs arising from the power domain are incorporated into the common record set. The controller performs process control and monitoring along with electrical control signaling and monitoring within a single control strategy directly from the controller.

The invention relates to the field of cell antenna factor calibration, in particular to a power domain estimation method and device based on GTEM cell antenna factor calibration. The scheme comprises the following steps: determining a working frequency band according to application requirements, and selecting a plurality of calibration frequency points in the working frequency band; performing reference field intensity calibration on each selected calibration frequency point; measuring an initial azimuth angle based on the GTEM cell; measuring noise power, and establishing a noise power matrix; measuring the receiving power under the full angle; subtracting the corresponding noise power from the measured receiving power to obtain net signal power; calculating an antenna factor of the antenna under the current set angle and the calibration frequency point according to the antenna factor definition; and finally, calibrating and verifying the antenna factors. The method is suitable for power domain estimation based on GTEM cell antenna factor calibration.

Systems, methods, and devices provide efficient wake operations and boot times for electronic devices. Methods include initiating, using one or more processing elements, a boot operation associated with a plurality of power domains, and determining, using the one or more processing elements, a type of the boot operation based, at least in part, on current status information identifying a current status of each of the plurality of power domains. Methods further include determining, using the one or more processing elements, one or more authentication operations based, at least in part, on the type of boot operation and a configuration of the plurality of power domains being booted, performing, using the one or more processing elements, the one or more authentication operations prior to booting the power domain.

The application provides a three-phase imbalance treatment method based on a fuzzy biased particle swarm optimization algorithm. The three-phase imbalance treatment method based on the fuzzy biased particle swarm optimization algorithm comprises the following steps: constructing a four-phase node admittance matrix equation corresponding to three-phase nodes and a neutral node, solving the admittance matrix equation based on the admittance matrix parameters of a circuit system to obtain electrical basic data of nodes of the circuit system; based on the electrical basic data, deducing, converting three-phase imbalance of the circuit system from a current domain to a power domain, and obtaining an evaluation value of three-phase current imbalance; determining a constraint threshold value of the evaluation value based on a preset power quality standard; constructing a target optimization function based on a constraint condition corresponding to the evaluation value; constructing a multi-dimensional constraint comprising a power grid safety constraint, a device operation constraint and a power balance constraint; initializing a plurality of candidate power scheduling schemes based on power supply output data and load data; and based on the constraint threshold value of the evaluation value and the multi-dimensional constraint, iteratively optimizing the plurality of candidate power scheduling schemes to obtain a target scheduling scheme of the circuit system. The application can improve the accuracy of the three-phase imbalance treatment based on the fuzzy biased particle swarm optimization algorithm.

A circuit portion comprises a mapping module, a source component, a destination component and a memory. The mapping module comprises a plurality of channels that each provides a connection for connecting two components of the circuit portion in a one-to-one relationship. The source component is arranged in a first clock or power domain, and the destination component is arranged in a second clock or power domain. In response to an assertion of an event signal or an interrupt by the source component, the mapping module is configured to forward the event signal or interrupt to the destination component via only one channel of the plurality of channels so as to cause the destination component to perform a corresponding task according to a mapping stored in the memory.

This invention discloses a method and system for automatic extraction and knowledge construction of data quality rules for power equipment, belonging to the fields of artificial intelligence and power data governance technology. To address the problems of low parsing accuracy of complex tables in power technology standard documents, lack of physical constraint verification of extraction results, and catastrophic forgetting of models due to standard updates, this invention utilizes a multimodal large language model to parse documents. A structured document object model is obtained through hierarchical table structure encoding, cross-page context preservation, and semantic binding of table annotations. The large language model, fine-tuned with domain knowledge, extracts entity relationships and performs consistency verification in conjunction with a physical constraint knowledge base in the power domain. The verified entity relationships are assembled into structured quality rule records and stored in a graph database. A differential-adaptive elastic weight consolidation strategy is employed for continuous learning, combined with a human-machine collaborative quality inspection optimization model, achieving high-precision complex table parsing, physical consistency verification, and anti-forgetting continuous learning.

According to an embodiment, a method for debugging a low-power domain in a multi-power domain device is disclosed. The method includes mapping a critical signal of the low-power domain to a latch circuit of a register bank; capturing, by the latch circuit, transitions of the critical signal in registers of the register bank; observing, by a core circuit in a switchable power domain of the multi-power domain device, registers of the register bank; and determining a fault corresponding to the critical signal based on a value of the registers of the register bank.

The invention provides a multi-power domain chip timing sequence adaptive test system and test method, the system comprises a plurality of timing sequence test devices, each timing sequence test device is connected with a GPU chip, the models of all GPU chips are the same, and each timing sequence test device comprises a timing sequence control module, a timing sequence detection module and a result analysis module. A test scheme of the time sequence test device is formulated according to the test states of the time sequence test device and other simultaneous test time sequence test devices, and a plurality of time sequence test devices are adopted to test the GPU chip at the same time, so that the time sequence test efficiency of the multi-power-domain GPU chip is improved; during testing, the power-on sequence and the rising time delay of the time sequence of the multi-power-domain GPU chip are evaluated, and time sequence parameters of the GPU chip are analyzed more comprehensively; and testing is carried out in a normal working state of the GPU chip, so that the time sequence parameters of the chip in an actual application scene are reflected more accurately.

This invention relates to the field of intelligent power system technology, and discloses a method, system equipment, and medium for injecting knowledge into the power field. The method includes employing a hierarchical hybrid sparse expert model and a cyclic knowledge distillation framework. This is achieved by reconstructing the large model architecture into a hybrid expert layer containing a general expert network and a power field expert network. A progressive gating activation mechanism is used to dynamically select and combine relevant expert networks. A cyclic knowledge distillation process is constructed using forward knowledge transfer and backward knowledge correction. Combined with a knowledge compensation network, supplementary training samples are automatically generated after identifying weak areas in the model's knowledge, enabling continuous optimization and evolution of the model. This invention achieves efficient injection of knowledge into the power field, significantly reducing training and inference resource consumption and improving inference speed while ensuring diagnostic accuracy and solution generation quality. It is suitable for power application scenarios such as intelligent diagnosis and management of distribution network problems.

Systems, methods, and devices provide management of power domains. Methods include activating a first power domain of a memory controller in response to receiving a memory command associated with a storage location coupled to the memory controller, and performing a first portion of a sequence of operations determined based on the memory command, the first portion being performed using a first plurality of processing elements included in the first power domain. Methods further include activating a second power domain of the memory controller based on a timing determined by the sequence of operations, and performing a second portion of the sequence of operations using a second plurality of processing elements included in the second power domain.

The invention discloses a power domain modulation method, a demodulation method, a modulation system and a demodulation system in the technical field of optical fiber communication. The modulation method comprises the following steps: generating three groups of chaos sequences A, B and C by using a Lorenz chaos model; performing triple encryption and orthogonal decomposition on the original data by using the three groups of chaos sequences A, B and C to obtain a third layer of encrypted constellation and a 3D-8symbol constellation; converting a key of the Lorenz chaos model into a binary system, mapping the binary system to a 1D constellation, and superposing the 1D constellation with a third layer of encrypted constellation to obtain a 2D-QPSK constellation; the method comprises the following steps: carrying out dimension transformation on a 2D-QPSK constellation on a symbol coordinate dimension, supplementing a dimension with a coordinate of 0 for the 2D-QPSK constellation to obtain a 3D-4symbol constellation, and then carrying out PDM modulation on the 3D-4symbol constellation and a 3D-8symbol constellation to obtain a transmission signal. The method has high security and accuracy for encryption of high-dimensional constellations, and has low complexity at the same time.

The invention provides a netlist detection method and device, equipment and a storage medium, and relates to the technical field of computers. According to the implementation scheme, in response to a power gating PG netlist detection request for a target power domain, a PG netlist of the target power domain and a unified power format UPF file are obtained, and the UPF file is provided with an isolation strategy for a port signal of the target power domain; on the basis of an isolation strategy in the UPF file, first isolation units in the PG netlist are detected, second isolation units with integration errors are obtained, and the first isolation units are isolation units integrated for port signals of the target power domain; and determining a PG netlist detection result of the target power domain based on the position information of the second isolation unit in the PG netlist. By adopting the method and the device, the verification efficiency of the PG netlist can be improved.

The invention discloses a redundant power domain cooperative scheduling method and related equipment, and relates to the technical field of power grids, and the method comprises the steps: dynamically collecting state data, peripheral power consumption demand data, environment and heat dissipation data and system-level data of multiple power domains; based on the peripheral power consumption demand data and the state data, executing a dynamic power consumption distribution algorithm to generate a preliminary power consumption distribution scheme; performing heat dissipation compensation adjustment on the initial power consumption distribution scheme in combination with environment and heat dissipation data, and generating a temperature-optimized target power consumption distribution scheme; inputting the target power consumption distribution scheme into the thermoelectric coupling model, solving a coupling equation of electrical parameters and thermal parameters, and outputting a globally optimized power distribution strategy; a power domain fault flag is monitored based on system-level data, and when a fault is detected, a redundant power seamless switching mechanism is triggered based on a power distribution strategy. Through priority weighted distribution and thermal compensation linkage, the power domain utilization rate is improved, and peripheral performance fluctuation is effectively reduced.

The invention discloses a communication method of a power domain non-orthogonal multiple access system based on a symmetric Hamming distance constellation and a related device, and the method comprises the steps: carrying out the coding and bit interleaving processing of information bit sequences of two users, and obtaining corresponding bit interleaving sequences; modulating the bit interleaving sequence to obtain a corresponding modulation symbol sequence, and determining transmission power; based on the symmetric Hamming distance, determining a mutual constellation arrangement function according to the modulation orders of the modulation symbol sequences of the two users; based on a mutual constellation arrangement function, performing mapping superposition according to the modulation symbol sequence and the transmission power through a joint constellation mapper to obtain a superposed symbol sequence; transmitting the superposed symbol sequence through a transmission channel to obtain a received signal; and decoding the received signal by adopting an iterative soft demodulation and decoding mode, and recovering the decoding bit sequences of the first user and the second user. According to the method, the correlation between the users is established based on the mutual constellation arrangement function to reduce the interference between different user constellations.

An apparatus and method for efficiently managing power consumption of multiple partitions of an integrated circuit. A processing unit includes multiple partitions, each assigned to operation parameters of a respective power domain. Each of the partitions is assigned to operating parameters of a respective power domain. A power manager accesses a total power consumption budget for the multiple partitions and sends corresponding assigned power limits to the multiple partitions. A particular partition calculates a corresponding measurement of power consumption as a weighted sum of sampled signals, and performs steps to reduce power consumption when the particular partition determines the corresponding measurement of power consumption exceeds a corresponding assigned power limit. The power manager updates the assigned power limits within a first time interval. The multiple partitions calculate the power consumption measurements and perform power reduction steps within a second time interval less than the first time interval.

The application provides an adaptive power regulation method and system for a power integrated circuit, and relates to the technical field of power regulation. The method comprises the following steps: dividing the power integrated circuit and outputting multiple power domains; constructing multiple power feature vector sets according to power requirement data of each power domain, performing Gaussian mixture model clustering, and constructing a complementarity matrix based on multiple clustering results; establishing a pairing priority list according to the complementarity matrix, obtaining a complementary power regulator pair based on the pairing priority list; configuring an adaptive power regulator for the complementary power regulator pair, and performing adaptive power regulation on each complementary power regulator pair based on an adaptive power switching regulation logic model. The application can solve the technical problem of poor power regulation stability of the power integrated circuit in the prior art, and achieve the technical effect of improving the power regulation stability.

This invention relates to the field of intelligent analysis technology for power systems, and particularly to a multi-task prediction method, system, electronic device, and medium based on a hybrid expert network. The method includes: acquiring multi-source heterogeneous operating data of the power system to generate an input tensor; generating a shared feature map through a power domain feature aggregator; generating an optimized feature sequence through a variable mixer; capturing cross-task common knowledge and outputting global expert features through a global hybrid expert network; outputting task expert features through a task-specific hybrid expert network; and fusing the global expert features and task expert features to generate prediction results for each specific task. This approach solves the technical problem of insufficient prediction accuracy in existing hybrid expert networks when facing multi-task intensive prediction scenarios in power systems, and improves the feature representation capability, task collaboration efficiency, and final prediction accuracy of multi-task learning.

The present invention relates to a power control system and a system-on-chip device including the same, which controls power of a plurality of power domains constituting the system-on-chip device by performing power control decisions at a software level and power control execution at a hardware level in parallel. The power control system according to the present invention includes a central processor configured to make decisions on power-up or power-down of at least one target power domain among a plurality of power domains included in the system-on-chip device, and transmit at least one domain power control command among a domain power-up command and a domain power-down command based on the domain power-up / power-down decisions, and a domain power manager configured to receive the domain power control command and execute at least one of a power-up sequence and a power-down sequence for the target power domain.

The invention relates to a multi-source heterogeneous data automatic mapping method and device based on semantic alignment, and the method comprises the steps: determining a power entity and an entity feature vector according to a power domain ontology model, and determining a power entity mapped by a to-be-aligned field based on the similarity between the entity feature vector and a feature vector of the to-be-aligned field; updating a message transmission mechanism by taking the constructed entity constraint condition as a constraint condition of a message function; inputting a full connection graph taking the to-be-aligned fields as nodes into the graph neural network, and obtaining an embedded vector of each node based on the updated message passing mechanism; when a candidate mapping relation is determined according to the semantic similarity of the two embedded vectors, entity category conflict detection and field conflict detection are carried out, and the candidate mapping relation is corrected according to a detection result; and generating data in a target format based on the corrected candidate mapping relationship. According to the method and the device, sharing, management and compatibility of multi-source heterogeneous data in different systems are realized.

Disclosed are a system and method for designing a power management controller that performs power control of a plurality of power domains in a system-on-chip (SoC) device using a no-code approach. The system comprises a memory configured to store instructions and a processor configured to execute the instructions. The instructions include operations for generating a root power manager instance based on a root power manager component, generating at least one domain power manager instance based on one or more domain power manager components, establishing connections between output ports of the root power manager instance and input ports of the domain power manager instances, allocating memory storage space for each power manager instance, and generating hardware code of power elements, register code corresponding to the power elements, hardware code corresponding to ports and connections, and binary code corresponding to an operation sequence of the power management controller.

Logic retention support in a data processing system is provided. In a system and a methodology thereof, secondary requests are distributed based on a logic retention power mode request to functional units of a power domain by mapping the logic retention power mode request to a clock quiescence request; distributing the clock quiescence request to one or more first functional units of the functional units that are without a logic retention power mode; and maintaining the one or more first functional units in a functional power mode.

An asynchronous FIFO system (300) for transferring data from a transmit power region (302) to a receive power region (304) on a chip comprises a plurality of memory elements (308) and a plurality of cyclic multiplexers (310, 312) in the transmit power region, a data toggling multiplexer (318) and a plurality of pointer generators (314, 316) in the receive power region, and a plurality of level shifters (322a~d) positioned between the cyclic multiplexer in the transmit power region (302) and other elements in the receive power region, each The pointer generator is configured to provide each circular multiplexer with a pointer value so that each circular multiplexer can transfer discontinuous data (1, 3, 5, 7 or 0, 2, 4, 6) from multiple memory elements (308), and the data toggling multiplexer (318) is configured to periodically read the data (0, 1, 2, 3, 4, 5, 6, 7, 8) from multiple circular multiplexers (310, 312) in order to reconstruct the data from the multiple memory elements in the received power domain.

The present disclosure relates to a power domain management circuit and a system-on-chip. The power domain management circuit comprises: an enabling unit, configured to generate an enabling signal having a first preset level upon reception of an isolated set signal, or generate an enabling signal having a second preset level upon reception of a reset indication signal; and a clamping unit, electrically connected to the enabling unit, the clamping unit being configured to, upon reception of the enabling signal having the first preset level, clamp an initial signal transmitted from a first power domain to a second power domain, so as to generate a target signal having a third preset level, or upon reception of the enabling signal having the second preset level, not clamp the initial signal, so as to generate a target signal having a level that changes with the level of the initial signal.

The invention provides a self-adaptive power regulation and control method and system for a power integrated circuit, and relates to the technical field of power regulation and control, and the method comprises the steps: dividing the power integrated circuit, and outputting a plurality of power domains; constructing a plurality of power feature vector sets according to the power demand data of each power domain, performing Gaussian mixture model clustering, and constructing a complementarity matrix based on a plurality of clustering results; establishing a pairing priority list according to the complementarity matrix, and obtaining a complementary power regulator pair based on the pairing priority list; and configuring adaptive power regulators for the complementary power regulator pairs, and performing adaptive power regulation on each complementary power regulator pair based on the adaptive power switching regulation logic model. According to the invention, the technical problem of poor power regulation and control stability of a power integrated circuit in the prior art can be solved, and the technical effect of improving the power regulation and control stability is achieved.

The application discloses a design method of a logic circuit, an analysis platform and the logic circuit, and relates to the chip manufacturing field, wherein the method comprises the following steps: determining whether a timing path meets the following preset conditions: a combinational logic unit of the timing path is located in a always-on power domain, a target buffer connected with the combinational logic unit is located in a switchable power domain, and a plurality of end nodes connected with the target buffer comprise a first end node located in the always-on power domain and a second end node located in the switchable power domain; in the case that the timing path meets the preset conditions, generating an intermediate buffer, the intermediate buffer comprising a first type of buffer located in the switchable power domain; connecting the target buffer, the intermediate buffer and the first end node.

The invention provides a control method and device, equipment, a chip and a medium, and the method comprises the steps: carrying out the power-on control of a first power domain in at least two power domains, the at least two power domains also comprise a second power domain, and the first power domain is different from the second power domain; determining that the signal of the first power domain is stable; and performing power-on control on the second power domain. The technical problems of low power-on efficiency and waste of power consumption in the prior art are solved.

The invention discloses a low-power-consumption event closed-loop embedded entity node machine core module and a method thereof. The machine core module comprises a main control processing unit, a power management and turn-off domain unit, an input trigger unit, a short-distance communication unit and a prompt output unit. The movement module is in deep dormancy in a default state through power domain division and state machine control, and works for a short time only when an event is triggered or an external instruction is awakened; and after event packaging, reporting, prompt output and confirmation receipt are completed, a dormant state is automatically returned, so that a low-power-consumption event closed loop is formed. The movement module only executes event perception, fixed prompt and user confirmation functions, and does not perform semantic judgment, relation modeling or decision processing; related judgment and rule processing are completed by an external terminal or system, and the external system is not a necessary condition for independent operation of the machine core module. The method is suitable for an embedded entity node scene which needs long-term standby and intermittent communication and is sensitive to misjudgment risks.

An adaptive signaling architecture compensates for electrical and thermal variation among multiple power domains of a wafer- or panel-scale computing substrate. Each domain receives power from an independent power-supply board, and inter-domain signal channels include adaptive control circuitry that dynamically adjusts voltage swing, bias, pre-emphasis, and termination in response to local voltage and temperature sensors. The adaptive network maintains uniform impedance and timing across domain boundaries without retimers, reducing interconnect power and improving reliability. The system sustains per-channel data rates above 32 Gb / s and rack-scale throughput around 1 zettaFLOPS (FP4 sparse AI inference) within practical power limits.