75 results about "Power Management Bus" patented technology

An electronic system is disposed on a single integrated circuit including a plurality of power domains and a power control manager. Each power domain may be independently powered. The power control manager includes a set of control registers storing individual control bits, a power switch for each power domain and a programmable microprocessor. The programmable microprocessor controls the digital state of individual bits within the control registers thereby controlling the ON and OFF state of the corresponding power domain.

Methods for performing power management of InfiniBand (IB) switches and apparatus and software configured to implement the methods. Power management datagrams (MADs) are used to inform IB switches that host servers connected to the IB switch's ports are to transition to a reduced-power or offline state or have returned to a normal operating state. A subnet management agent (SMA) on the IB switch receives the power MADs from the host servers and tracks each server's operating state. In response to power down MADs, the SMA coordinates power reduction of the switch's ports and other switch circuitry. For switches with multi-port IB interfaces, a multi-port interface is caused to enter a reduced-power state when all of its ports are connected to host servers that are idle or offline. Additionally, when all of a switch's ports are connected to idle or offline servers the SMA may put the switch's core switch logic into a reduced-power state. Power MADs are also used to inform upstream IB switches when a switch is to transition to a reduced power state or has returned to a normal operating state.

A single integrated circuit includes logic that supports 10BASE-T, 100BASE-T and 1000BASE-T transceiver functionality. The invention implements power management techniques by placing unused functionality in sleep mode. When the functionality is required later, then that functionality may be awakened again and used as required for the particular situation. A processor is able to interact with the media access controller (MAC), and the MAC then communicates with the physical layer (PHY). The invention is adaptable to various devices that are capable to operating using 10BASE-T, 100BASE-T and 1000BASE-T, even those the PHY of these devices may be somewhat different.

A power supply circuit comprises a power supply unit, a microcontroller, a plurality of power management chips and a plurality of switching circuits. Each of the switching circuits comprises an input end and an output end, wherein the input end of each of the switching circuits is connected with the power supply unit after being connected with a resistor in series, and the output end of each of the switching circuits is connected with a mainboard to supply power to the mainboard. Each of the power management chips is connected with the microcontroller through a power management bus to monitor real power consumption of each of the mainboards during operation in real time and feed the monitored results back to the microcontroller. The microcontroller is connected with each of the mainboards through a data line to regulate and manage power use of each of the mainboards according to the rated power of the power supply unit and the sum of the real power consumption of the mainboards. The power supply circuit has the function of limiting current and power among a plurality of mainboards and provides comprehensive safeguard procedures for the mainbaords.

A card with power management circuitry is provided. A card may have circuitry contained therein (e.g., a processor) that may have a maximum operating voltage. The card may include a power source (e.g., a battery) that provides power ranging in voltage from a maximum power source voltage to a minimum power source voltage. The maximum power source voltage is greater than the maximum operating voltage. Power management circuitry is provided to manage the power received from the power source such that the voltage provided to the circuitry (e.g., processor) does not exceed the maximum operating voltage.

A method and system for managing power in a computer system is disclosed. In one embodiment the method includes providing output signals from a sensor panel to a controller, wherein the controller includes a data bus and a plurality of devices communicatively coupled to the data bus; monitoring an activity level on the data bus by monitoring bus access requests by one or more of the plurality of devices; and reducing or shutting off a bus clock frequency if there is reduced or no activity on the bus for a predetermined period of time.

Systems and methods for dynamic multi-link compilation partitioning. In particular, some implementations of the present invention relate to systems and methods for connecting a computer processing unit to a video display through the use of a wide variety of video display connectors. The present invention further relates to a dynamic interface incorporating USB, PCI-express, SATA, I²C, and power management bus (PMBus) technologies. Further still, some implementations of the present invention relate to an openly connected dynamic storage system whereby the storage capacity of a processing unit is increased by coupling additional storage components to the processing unit via a dynamic interface connector that is interposedly connected. Some implementations of the invention further relate to a customizable grouping of PCIe lanes to provide for a flexible allocation of the lanes to customize the characteristic of the board set, while reducing the power consumption, improving the bandwidth and speed of the device, reducing the cost of the device and providing serial data transfer architecture to provide multiple busses.

A computer system comprising a motherboard and a power supply having an associated power management bus controller with memory storing the power capacity of the associated power supply. A power circuit provides power from the power supply to the motherboard, wherein the motherboard has a processor and a baseboard management controller. The system further comprises a power management bus providing communication between the baseboard management controller and the power management bus controller associated with the selected power supply, wherein the power management bus controller provides the stored power capacity to the baseboard management controller. This allows the baseboard management controller to limit operation of the processor to control the amount of power consumed from exceeding the power capacity of the selected power supply. The power capacity of the power supply may be sent to the baseboard management controller in response to booting the motherboard.

The invention belongs to the technical field of power sources, and particularly relates to a power source automatic calibration device and a calibration method thereof. The power source automatic calibration method comprises the following steps of utilizing a computer module to read voltage values and current values of two different points of a to-be-calibrated power source through a PMbus (power management bus), quickly calculating the calibration parameters through programs, transmitting the calibration parameters to an MCU (micro controller unit) in the to-be-calibrated power source, and enabling the MCU to store and call the calibration parameters to calibrate the voltages and the currents, so as to output the qualified power source meeting the precision requirement. The power source automatic calibration device and the calibration method have the advantages that the defects of complicated operation, low efficiency, low precision and the like of the traditional manual calibration are overcome, the production efficiency is obviously improved, and the precision is also ensured.

The invention provides a power management system based on multi-node micro servers. The power management system comprises a plurality of micro servers. Each micro server comprises a general purpose input/output (GPIO) interface. A power management bus is connected with the micro servers. An out-of-band (OOB) management chip is connected with the GPIO interfaces of the micro servers and is connected with the power management bus. The OOB management chip is used for sending power control commands to one or the plurality of micro servers, and controlling power supplies of the micro servers through the power management bus. The power management system carries out management on the power supplies of the multi-node micro servers through utilization of an in-band and out-of-band combination mode, ensures power running safety of the multi-node micro servers, improves power management efficiency of the multi-node micro servers, and is simple, convenient, and easy to use. The invention further provides the micro servers.

The invention provides a power management system and a power management method. The power management system includes a power chip, which is used for storing power source information; a base block management controller (BMC), which is used for obtaining the power source information stored by the power chip through a power management bus (PMBUS), wherein the power chip is provided with a PMBUS communication interface, and the power chip is connected with the BMC through the PMBUS. The power management system and method are able to output the power source information to the BMC.

The invention provides a server rack system and a power management method of the server rack system. The server rack system comprises more than one power supply device, a power controller, a network switch and an integrated management module. The power controller is coupled to the power supply devices through power management buses and general input/output interfaces. The network switch is coupled to the power controller. The integrated management module is coupled to the network switch, wherein the integrated management module is communicated with the power supply devices through the power controller, and controls the power supply devices through the power controller.

Techniques for autonomous thermal management of a power-management integrated circuit (PMIC). In an exemplary embodiment, an embedded microcontroller is provided on the PMIC to store instructions for implementing a thermal controller. The thermal controller may manage in real-time the current scaling factors of a plurality of modules coupled to corresponding off-chip power entities. The thermal controller may include registers that are programmable by an off-chip entity such as a microprocessor to specify parameters such as module priorities and a minimum current scaling factor for each module. Power entities that may be controlled by the autonomous thermal controller include, e.g., a battery charger, and/or one or more user-interface entities such as a back light display driver, a flash LED driver, or an audio amplifier.

The invention provides a device for monitoring total power consumption of servers in real time. A precision resistor is connected between a hot plug redundant power supply and a power supply end of a PCB board in series; a hot plug controller is connected with two ends of the precision resistor and is used for measuring voltages at the two ends of the precision resistor; the hot plug controller is connected with a power management bus. All the output currents of the hot plug redundant power supply are collected onto the precision resistor; the voltages at the two ends of precision resistor are detected through the hot plug controller; the resistance value of the precision resistor is known, so that an input current value can be obtained according to an Ohm law and then input power consumption can be obtained; the power consumption is stored in a power register in a digital form through an A/D analog to digital manner, so that control chips such as BMC, PCH and the like in a system can read the value through PMBUS; and the value is a real-time summary of all the paths, so that the detection precision can be improved.

Disclosed is a power management system that performs power management of a graphic processing unit (GPU). The power management system includes a dynamic voltage and frequency scaling (DVFS) driver configured to include an interface that calls a device driver of the GPU or is called by the device driver, and control an operating voltage and/or an operating frequency of the GPU, and a DVFS governor interface module configured to provide an interface for the DVFS driver to a power management policy module of an operating system (OS). Therefore, in the power management system according to the present invention, a power management policy of the OS based on a change in a workload of the GPU may be applied to the GPU, independently of a hardware configuration of the GPU.

An electronic device, typically a microcontroller, which is divided into a multiplicity of power domains comprising one or more intelligent peripherals, is provided with an on-board power management module for switching power to one or more domains for pre-determined time periods and in a predetermined sequence. The values of the predetermined time periods and sequence may be pre-programmed by the design engineer or user of the device. In one example, power is switched to domains in a round robin fashion. An optional interrupt capability permits selective application of power to a dormant intelligent peripheral requesting it at the expense of others and based on a priority scheme. Consumption of current supplied to power domains may be monitored by a power watchdog or alternatively via a dedicated power monitor associated with each intelligent peripheral. The invention helps to reduce device power consumption without any associated reduction in processing performance.

A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents the propagation of data, in particular ingress grains, to a given group of egress ports if the data is not selected by any of the egress ports in a given group. While the ingress data disable method partitions ports into groups and saves power by disabling the fanout tree from the root on a port group basis, the egress data disable method saves power on a port group basis by disabling the fanout tree from the tail end in addition to applying the ingress data disable method. The ESS block also includes an grain select block for selecting and storing a given ingress grain for eventual output to an egress port.

The invention discloses a power allocation system for data centre. The system is used for determining one BMC in the data centre as the main BMC, controlling the main BMC for reading the total power consumption of the whole data centre at fixed period from a power supply module through a power management bus; selecting the mainboard capable of being turned off in the data centre according to the preset principle after that the read total power consumption gets to the power supply upper limit of the power supply module; sending a control command to the selected mainboard for controlling the selected mainboard for turning off provisionally. A power allocation method for data centre is also provided. The power supply status of the whole data centre can be intelligently managed.

The invention provides a method for dynamically adjusting power supply efficiency in the cloud computing industry by means of centralization. System hardware includes a power module, a primary power back panel, a node middle board, a secondary power panel, a management back panel and a fan plugboard, the primary power back panel is connected with the node middle board through a power line, the management back panel is plugged together with management mainboards and connected between the primary power back panel and the node middle board, and the management mainboards are simultaneously connected with computing nodes through a management network switch for transmitting electricity load conditions and are used for detecting a system consisting of the computing nodes and the node middle board through the management network switch for an IPMB (intelligent platform management bus). When the system is in a light-load environment, one of four power modules is closed by the aid of GPIO (general purpose input/output) signals or one power module is led to sleep by means of PMBUS (power management bus) commands, the other three power modules remain being used for outputting 12V power, the load factor of each power module is increased by one third than that of a prior power module at the time, and power sources are operated between a more efficient load interval, so that power is saved.