626 results about "Dynamic storage" patented technology

A method for dynamically allocating control of a storage device, the method comprising receiving an access request from a first computer requesting access to a storage device; directing, based upon the access request, a first storage controller computer to assume an inactive state with respect to control of the storage device; and directing, based upon the access request, a second storage controller computer to assume an active state with respect to control of the storage device.

A method and apparatus of dynamically storing critical data of a gaming machine by allocating and deallocating memory space in a gaming machine is disclosed. One or more embodiments describe downloading or removing a new game to a gaming machine such that all existing critical data in NV-RAM memory is left intact. In one embodiment, the invention discloses a method and apparatus for dynamically allocating and deallocating memory space to accommodate either permanent or temporary storage in an NV-RAM. A method and apparatus is provided to monitor available memory space and dynamically resize the memory in NV-RAM. In one embodiment, a method is disclosed for performing an integrity check of the NV-RAM and determining whether a critical data error has occurred. In one or more embodiments, methods of compacting and shifting contents of an NV-RAM are described to consolidate available memory space or to prevent unauthorized access of NV-RAM memory.

A method and an apparatus for dynamic memory resource management are provided. Memory activity information is collected for a virtual machine. Additional memory shares are dynamically allocated to the virtual machine, as needed, based on the memory activity information for the virtual machine and based on a specified priority of the virtual machine in order to properly adjust the total physical memory used by the virtual machine.

A processor core for transitioning a debugging unit between a plurality of operating states in response to an instruction stream is disclosed. The processor core generates trace data as it processes operating signals of the instruction stream. The processor core provides a first trigger event signal to the debugging unit in response to a first trigger instruction signal within the instruction stream that is representative of a triggering instruction to transitions the debugging unit to a base operating state. The processor core provides a second trigger event signal to the debugging unit in response to a second trigger instruction signal within the instruction stream that is representative of a triggering instruction to dynamically store trace data within the memory component of the debugging unit. The processor core provides a third trigger event signal to the debugging unit in response to a third trigger instruction signal within the instruction stream that is representative of a triggering instruction to statically store trace data within the memory component of the debugging unit. Concurrently or alternatively, the processor core can provide one or more of the trigger event signals to the debugging unit as a function of a generated trigger data in response to additional operational instructions within the instruction stream.

A gateway device configured to receive IP video content may select and use transmission methods that maintain a certain quality of service for delivering the content. A transmission method may be selected based on a network to which the client device is connected. The gateway device may select a network through which the content is to be delivered depending on a variety of factors including bandwidth availability, client compatibility, quality of service provided and the like. A gateway device may further be configured to convert multicast transmissions to unicast, to provide dynamic storage of content for pre-positioning and other purposes and/or to provide other functions.

System and method for tracking statistics at the subfile level and transparently placing or migrating inactive or less active blocks of data to other storage devices. Embodiments may provide mechanisms to track statistics at the subfile level of files including, but not limited to, database files, and to transparently place or migrate inactive or less active blocks of data of the files from higher-performing, typically more expensive, storage to lower-performing, typically less expensive, storage, while placing or migrating active blocks of data of the files to higher-performing storage, based on the subfile-level statistics rather than on file-level timestamps. In some embodiments, knowledge of file structure (e.g., database file structure), for example knowledge of database partitions with header blocks and data blocks in databases using data partitioning, may be used to separate more active and less active blocks of data of files onto storage with different performance and/or other characteristics.

A head suspension for supporting a head slider over a disk in a dynamic storage device and providing precise movement of the head slider relative to tracks on the disk. The head suspension includes a load beam, a flexure having a slider mounting region, and a dimple interface transmitting a load beam force to the slider mounting region. The head suspension further includes a microactuator mounted to the load beam. Movement of the microactuator is transmitted through the dimple interface by action of frictional forces at the dimple interface so as to cause movement of the slider mounting region transverse to tracks on the disk. A method of precisely moving a head slider supported by a head suspension includes providing and driving a microactuator configured to transmit movement of the microactuator to a slider mounting region through a dimple interface by action of frictional forces at the dimple interface.

A dynamic memory compression architecture is disclosed which allows applications with working data sets exceeding the physical memory of an embedded system to still execute correctly. The dynamic memory compression architecture provides “on-the-fly” compression and decompression of the working data in a manner which is transparent to the user and which does not require special-purpose hardware. A new compression technique is also herein disclosed which is particularly advantageous when utilized with the above-mentioned dynamic memory compression architecture.

Methods, systems, and media for managing dynamic memory are disclosed. Embodiments may disclose identifying nodes with having memory for dynamic storage, and reserving a portion of the memory from the identified nodes for a heap pool. After generating a heap pool, embodiments may allocate dynamic storage from the heap pool to tasks received that are associated with one of the identified nodes. More specifically, embodiments identify the node or home node associated with the task, the amount of dynamic storage requested by the task, and create a heap object in the node associated with the task to provide the requested dynamic storage. Some embodiments involve de-allocating the dynamic storage assigned to the task upon receipt of an indication that the task is complete and the dynamic storage is no longer needed for the task. Several of such embodiments return the de-allocated dynamic storage to the heap pool for reuse.

The present invention is directed to a method for providing data element placement in a storage system via a Dynamic Storage Tiering (DST) mechanism, such that improved system efficiency is promoted. For example, the DST mechanism may implement an algorithm for providing data element placement. The data elements (ex.—virtual volume hot-spots) may be placed into storage pools, such that usage of higher performing storage pools is maximized. Hot-spots may be detected by dynamically measuring load on LBA ranges. Performance of the storage pools may be measured on an ongoing basis. Further, the hot-spots may be ranked according to load, while storage pools may be ranked according to measured performance. If a hot-spot's load decreases, the hot-spot may be moved to a lower performing storage pool. If a hot-spot's load increases, the hot-spot may be moved to a higher performing storage pool.

Data objects are stored on storage devices, taking into account service level agreements or other quality of service parameters. In one aspect, data objects grouped into storage volumes. In addition, the storage devices are classified into different level storage tiers, where higher level storage tiers have higher performance and lower level storage tiers have lower performance. Ranks for the data objects are calculated, based on both a data usage pattern for the data object (e.g., recency and frequency) and on quality of service (QOS) parameters for the storage volume containing the data object. Examples of QOS parameters include service level agreements, priority, minimum and maximum input/output operations per second. The data objects are then stored on storage devices, based on the data objects' ranks and the storage devices' storage tiers.

A surface-treated film, a transparent rigid layer and a transparent relaxing layer are laminated in this order to form a transparent laminate. Particularly, the transparent relaxing layer is made of an adhesive. The dynamic storage modulus G′ of the transparent rigid layer at 20° C. is not lower than 2×10⁸ Pa. On the other hand, the dynamic storage modulus G′ of the transparent relaxing layer at 20° C. is not higher than 1×10⁷ Pa. The transparent laminate is directly laminated onto a visual surface side (pen-input side) of a liquid crystal panel provided as an image display panel so that the transparent relaxing layer is placed inward. Thus, a pen-input image display device is produced.

Systems and methods for providing a dynamic memory buffer bank policy. Embodiments include a hub device for selecting a bank page policy. The hub device includes an input command stream interface and a bank page policy module. The input command stream interface detects commands from a memory controller that are directed to one or more memory devices that are connected to the hub device. The bank page policy module independently analyzes the commands to determine access patterns to the memory devices and for dynamically selecting between an open bank page policy and a closed bank page policy for the memory devices based on the analysis.

Memory architecture provides capabilities for high performance content search. The architecture creates an innovative memory derived using randomly accessible dynamic memory circuits that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. When the content being searched matches any of the rules programmed in the dynamic Programmable Intelligent Search Memory (PRISM) action(s) associated with the matched rule(s) are taken. Content search rules comprise of regular expressions which are converted to finite state automata and then programmed in dynamic PRISM for evaluating content with the search rules.

A data managing apparatus that manages various data such as contents in a simple storage/read controlling process, using a distributable recording medium. A card 10 has a first or static storage area IC7 adapted to be accessed in a first access method and having stored compressed high-quality music data and compressed high-quality image data, and a second or dynamic storage area CD2 adapted to be accessed in a second access method and having stored non-compressed high-quality music data and non-compressed high-quality image data. A portable player 10 or a household CD card reader 110' as a reproducer can retrieve and replay the high-quality music data and image data by referring to the compressed music data and image data stored in the IC7.

It has been discovered that systems, methods, apparatus and software can accommodate the addition or removal of available physical storage (storage “expansion”) in a storage virtualization environment while virtual storage devices remain online and generally available to users. When a change to the available storage has occurred, new storage device geometry and configuration information reflecting the change is obtained and/or calculated. This new information is used to update mapping information used by virtualization software and/or to update information used by an operating system to manage storage devices. Such updating occurs while some or all of the virtual storage devices associated with the physical storage devices remain available to users. In some cases, I/O operations targeting a physical device are held, in a manner transparent to a user, while updating occurs.

Various systems and methods for performing dynamic storage tiering in a virtual environment. For example, one method can involve identifying a location of a storage object within a virtual machine file, where the virtual machine file includes multiple storage objects. The method then involves detecting whether the storage object meets a criterion of a tiering policy. If the storage object meets the criterion, the storage object is moved from one tier of a multi-tier storage system to another tier of the multi-tier storage system.

Analog computational arrays for matrix-vector multiplication offer very large integration density and throughput as, for instance, needed for real-time signal processing in video. Despite the success of adaptive algorithms and architectures in reducing the effect of analog component mismatch and noise on system performance, the precision and repeatability of analog VLSI computation under process and environmental variations is inadequate for some applications. Digital implementation offers absolute precision limited only by wordlength, but at the cost of significantly larger silicon area and power dissipation compared with dedicated, fine-grain parallel analog implementation. The present invention comprises a hybrid analog and digital technology for fast and accurate computing of a product of a long vector (thousands of dimensions) with a large matrix (thousands of rows and columns). At the core of the externally digital architecture is a high-density, low-power analog array performing binary-binary partial matrix-vector multiplication. Digital multiplication of variable resolution is obtained with bit-serial inputs and bit-parallel storage of matrix elements, by combining quantized outputs from one or more rows of cells over time. Full digital resolution is maintained even with low-resolution analog-to-digital conversion, owing to random statistics in the analog summation of binary products. A random modulation scheme produces near-Bernoulli statistics even for highly correlated inputs. The approach has been validated by electronic prototypes achieving computational efficiency (number of computations per unit time using unit power) and integration density (number of computations per unit time on a unit chip area) each a factor of 100 to 10,000 higher than that of existing signal processors making the invention highly suitable for inexpensive micropower implementations of high-data-rate real-time signal processors.