168 results about "Refresh cycle" patented technology

A self-refresh method of a semiconductor memory device including: receiving a self-refresh entry command; performing a self-refresh cycle based on the self-refresh entry command; receiving a self-refresh exit command; based on receiving the self-refresh exit command, determining a refresh operation status; and based on determining that the refresh operation status indicating an idle state, executing a care refresh operation corresponding to row-hammer care.

A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh a first word line and a first protected word line during a first refresh cycle in response to a refresh signal, a random number generator configured to receive an address of the first word line and an address of the first protected word line to generate a first number, a counter electrically coupled to the random number generator. The counter is configured to receive the first number as an initial value of the counter, and configured to be turned on in response to the refresh signal. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh a second protected word line, adjacent to the second accessed word line, during a second refresh cycle.

The invention discloses a laser processing error compensation method and a processing system, and the method comprises the following steps: based on target processing graphic data, setting a decomposition step length and a galvanometer refresh cycle of laser processing, and planning a target axis track and a target galvanometer track; before machining is started, the shaft is driven to move along a preset empty track, actual motion coordinate information on a plurality of preset points is recorded, and coordinate information of the next point position of the shaft is predicted according to the coordinate information; calculating deviation information based on the actual coordinate information of the current point location on the target axis track, and correcting the track between the current point location and the next point location of the axis by using the deviation information; obtaining the correction information of the galvanometer on the corresponding galvanometer track based on the correction information of the track between the current point location and the next point location of the shaft; and the correction information of the galvanometer is issued to the galvanometer to compensate the actual position of the galvanometer, and then laser machining is started. Various machining errors are effectively compensated, and the machining precision and the product quality are improved.

Embodiments of the present invention relate to the technical field of computer graphics, and disclose a method, device, electronic device, and storage medium for image processing. The method for image processing in the present invention includes: sending the initial pose data of the terminal at the initial moment to the server, where the initial moment is a moment before the current moment; receiving the initial image data returned by the server according to the initial pose data, and the initial image data includes two-dimensional image data corresponding to the initial pose data; obtaining the target pose data of the terminal at the current moment; and adjusting the two-dimensional image data according to the initial pose data and the target pose data to obtain the target image data corresponding to the current moment. By adopting the embodiments of the present application, it is possible to avoid the problem that the virtual reality terminal cannot display an image corresponding to the terminal pose within the refresh period due to network delay, and at the same time reduce the hardware requirements of the virtual device.

The invention discloses a gate drive circuit and a display panel. The cascade adjustment module of the shift registers is used for adjusting a cascade output end to output a second power supply signal or a second clock signal according to signals on the first control node and the third control node, and the cascade output end of the ith-level shift register is electrically connected with the trigger write-in module of the (i + 1) th-level shift register; the output adjusting module is used for adjusting a scanning output end to output a target signal or a fourth power supply signal or a third clock signal according to a third control node, a signal on the cascade output end and the first control signal, the target signal comprises the third power supply signal or the fourth clock signal, and the scanning output end is used for being electrically connected with a pixel circuit; wherein the refresh cycle of the third clock signal is smaller than the refresh cycles of the first clock signal and the second clock signal. In the embodiment of the invention, the gate drive circuit can output complex waveforms to meet the requirements of the pixel circuit.

A method for obtaining a row hammer refresh address, including: after a row hammer refresh signal arrives, obtaining a current sampling address, and determining whether a high address is locked in a current row hammer refresh cycle; in response to the high address being locked, determining whether a high address of the current sampling address is identical to the locked high address; in response to being identical, updating an access frequency of the locked high address, and updating access frequencies of low addresses with a low address of the current sampling address; and when a next row hammer refresh signal arrives, using a low address with a highest access frequency stored in the group of low registers as a low address of the row hammer refresh address, and using the locked high address as a high address of the row hammer refresh address.

The invention discloses a system and a method for realizing the rhythm effect of an atmosphere lamp of a smart television, and the method comprises the following steps: a, audio feature extraction: obtaining the analog signal sampling values of a plurality of sound channels when the smart television plays music in real time, carrying out the sampling of each sound channel for multiple times in a fixed period, extracting the maximum sampling value of each sound channel, and obtaining the audio feature; determining a global maximum sampling value X; b, converting the number of the lamp beads: calculating the number of the lamp beads which need to be lighted currently through a preset algorithm based on the global maximum sampling value X, the current volume value Y and the total number Z of the atmosphere lamp beads; c, generating a gradual change effect: generating a gradual change color sequence based on a difference value between the starting RGB value and the ending RGB value according to the number of the lamp beads needing to be lightened, and distributing color values according to the serial number of the lamp beads so as to realize a rhythm gradual change effect; and d, dynamic control: dynamically adjusting a lamp bead refresh cycle according to a music playing state, and turning off the atmosphere lamp and stopping sampling in a non-music scene.

The invention discloses a high-speed refresh positioning algorithm and system based on wireless signal processing, and relates to the technical field of high-speed refresh positioning, and the algorithm specifically comprises the following steps: analyzing the cycle number of a signal data unit in a current refresh cycle, judging whether there is a signal data unit with the cycle number not equal to the current cycle number, and if yes, executing the following steps; when the signal data units exist and the number ratio of the signal data units exceeds a preset threshold value, a cross-cycle data synchronization state judgment process is started; and on the basis of the time label distribution, the historical data proportion and the source period number of the signal data units in the current refresh period, extracting feature information used for representing time consistency and a periodic structure, and inputting the feature information into a classification discrimination function to determine a cross-period data synchronization state corresponding to the current refresh period. According to the method, the problem of positioning mistaken refreshing caused by cross-cycle data dislocation is solved, refreshing control based on synchronous state judgment is realized, and the positioning accuracy and the system stability are effectively improved.

A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

The application provides an instrument verification system, method, device and instrument, wherein the system comprises: a control module configured to acquire an accumulated quantity of an instrument to be tested when receiving a verification request; a display module connected to the control module and configured to acquire the accumulated quantity and update a display result according to the current accumulated quantity every interval of a preset time length; the preset time length is less than a refresh cycle of a metering display module of the instrument to be tested; the control module is further configured to receive the display result through a shooting module, determine a test change quantity according to the display result, and determine a verification result according to the test change quantity and a standard change quantity; and the shooting module obtains the display result by shooting the display module. Through the application, the instrument verification efficiency can be effectively improved.

A memory device comprises an input interface configured to receive an erase request indicating a memory portion to be erased and control circuitry configured to trigger erasing information stored by memory cells of at least a part of the indicated memory portion of the memory device by writing a predefined pattern into the memory cells during an automatic refresh cycle.

A memory system, a method for controlling the refresh of a memory device, and a memory device are provided. The memory system includes a memory controller and a memory device. The memory controller periodically generates refresh commands at an average refresh interval. The memory device performs a normal refresh operation and a hammer refresh operation during the refresh cycle time. The memory device includes: a memory cell array including memory cells connected to the plurality of word lines; a temperature sensor configured to provide temperature information by measuring the operating temperature of the memory cell array; and a refresh controller configured to control the normal refresh operation and the hammer refresh operation. The refresh controller changes the hammer rate, which is the number of hammer executions per unit of hammer refresh operation performed during the refresh cycle time relative to the number of normal executions per unit of normal refresh operation performed during the refresh cycle time.

The application discloses a noise reduction processing method and device and electronic equipment, and belongs to the technical field of electronic equipment. The noise reduction processing method comprises the following steps: in the case that the display screen of the electronic equipment is in a bright screen state, the display refresh rate of the display screen and the change amount of the target voltage in the display refresh period are acquired; the display refresh period corresponds to the display refresh rate; the target voltage is the voltage required by each pixel point of the display screen when displaying a picture; a corresponding target anti-interference strategy is determined based on the display refresh rate and the change amount of the target voltage; and display noise is subjected to noise reduction processing based on the target anti-interference strategy.

According to one implementation of the present disclosure, a cache memory includes: a plurality of cache-lines, wherein each row of cache-lines comprises: tag bits of a tag-random access memory (tag-RAM); data bits of a data-random access memory (data-RAM), and a single set of retention bits corresponding to the tag-RAM. According to one implementation of the present disclosure, a method includes: sampling a single set of retention bits of a cache-line of a cache memory, where the cache-line comprises the single set of retention bits, tag-RAM and data-RAM, and where at least the single set of retention bits comprise eDRAM bitcells; and performing a refresh cycle of at least the data-RAM corresponding to the tag-RAM based on the sampled single set of retention bits.

The invention discloses a memory detection and check method and system based on coding, and the method comprises the steps: setting a dual-refresh constant for each memory region in a memory corresponding to each processor, and each group of dual-refresh constants comprises two refresh constants which are opposite to each other; performing periodic memory refreshing on the memory by using double refreshing constants, wherein the period comprises an odd period and an even period; wherein in the odd period, one refreshing constant in the double refreshing constants is used for carrying out memory refreshing on the corresponding memory area, and in the even period, the other refreshing constant in the double refreshing constants is used for carrying out memory refreshing on the corresponding memory area; reading back the memory area after the memory is refreshed, and calculating a check word based on data obtained by reading back; and checking the check word obtained by calculation. According to the memory detecting and checking method and system based on coding, the condition that a specific bit in the memory is wrong can be effectively detected, and the reliability and safety of the system are improved.

Disclosed is a semiconductor memory device that includes a memory cell array including a plurality of memory banks, a command decoder configured to decode a per-bank refresh command and a remaining bank refresh command received from an external source, and a refresh controller configured to control the cell array to perform a per-bank refresh operation for refreshing one memory bank among the plurality of memory banks that is based on a decoding result of the per-bank refresh command of the command decoder, wherein the refresh controller is configured to perform a remaining bank refresh operation for refreshing remaining memory banks other than the one memory bank among the plurality of memory banks, in response to the remaining bank refresh command during one refresh cycle.

A memory device and a method for protecting the same are provided. The memory device includes: a random number generator, a counter, and a controller. The random number generator includes a first logic gate and a second logic gate configured to generate a first output and a second output, respectively, according to the address of the first word line and the address of the first accessed word line. The random number generator further includes a switch configured to select one of the first output and the second output to be a first number. The counter is configured to receive the first number and count down from the first number. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh adjacent word lines of the second accessed word line during a second refresh cycle.

A network interface device operates in a normal transmit mode of operation in which the network interface device continuously receives transmission symbols from a link partner via a communication link. The network interface device determines that receiving circuitry of the network interface device transitions to a low power mode in response to receiving a sleep signal from a link partner. The network interface device then operates according to a silence / refresh cycle of the low power mode to conserve power. The silence / refresh cycle corresponds to a schedule that includes a refresh time window within which receive circuitry of the network interface device is to be energized to receive a refresh signal from the link partner. Upon transmitting the sleep signal, the network interface device transitions to a silent time window of the timeschedule within which the network interface device ignores transmissions from the link partner.

This invention relates to an artificial intelligence storage system. A string comprises multiple sets of transistor pairs connected in parallel between a source line and a bit line, with each set containing a pair of source-interconnected storage transistors. The sources of both storage transistors in each set are connected to the source line, and the drains of both storage transistors are connected to the bit line. Multiple strings are mapped to multiple weight value carriers of a neural network. The input data for each set of transistor pairs in each string is refreshed periodically. In consecutively numbered sets of transistor pairs, if the difference between the effective pulse duration of any storage transistor in the previous cycle and the effective pulse duration in the next cycle exceeds a predetermined value, then the adjacent numbered transistor pairs of that set are locked for one refresh cycle during the periodic refresh of the input data, and unlocked after the locking ends to begin the next round of input data refresh.

A network interface device operates in a normal transmit operating mode in which the network interface device continually receives transmission symbols from a link partner via the communication link. The network interface device determines that receive circuitry of the network interface device is to transition to a low power mode in response to receiving a sleep signal from the link partner. The network interface device then operates according to a quiet / refresh cycle of the low power mode to conserve power. The quiet / refresh cycle corresponds to a time schedule that includes a refresh time window in which receive circuitry of the network interface device is to be powered to receive a refresh signal from the link partner Immediately after transmission of the sleep signal, the network interface device transitions to a quiet time window of the time schedule in which the network interface device ignores transmissions from the link partner.

A dynamic random access memory (DRAM) device includes an array of DRAM storage cells. Refresh control circuitry refreshes the DRAM storage cells within a refresh period. The refresh control circuitry includes circuitry to refresh, during a first sub-period of the refresh period, at least one row of the array of DRAM storage cells in a selected one of the multiple banks in response to receipt of an activate command from a memory controller that is directed to the selected one of the multiple banks. At the end of the first sub-period of the refresh period, a value is generated indicating a remaining number of refresh operations to refresh a remaining number of unrefreshed DRAM storage cells of the array of DRAM storage cells within a remaining period of the refresh period. Transmit circuitry transmits the value to the memory controller.

The application discloses a display panel and a display device. The working process of a pixel circuit in the display panel comprises a first data refresh period, a data adjustment stage, and a second data refresh period arranged in sequence. The data adjustment stage comprises T1 first sub-data adjustment stages and T2 second sub-data adjustment stages arranged in sequence. The number of data write frames in the first sub-data adjustment stage is greater than the number of data write frames in the second sub-data adjustment stage, and the number of hold frames in the first sub-data adjustment stage is less than the number of hold frames in the second sub-data adjustment stage. Therefore, the unstable situation of the input signal of the driving transistor caused by the first data refresh period can be quickly reversed before the second data refresh period, so that the flicker phenomenon of the picture observed by the human eye during the display picture switching can be avoided.

Embodiments of the present disclosure disclose a memory and an operating method thereof, a memory system and an electronic device. The memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit comprises: a temperature sensing circuit configured to sense a temperature of the memory and generate a temperature signal based on the sensed temperature; a control logic circuit configured to determine a target refresh period based on the temperature signal and a mapping table; wherein the mapping table comprises a plurality of preset temperature signals and a plurality of preset refresh periods, and the plurality of preset temperature signals and the plurality of preset refresh periods correspond one by one; and a refresh control circuit configured to adjust a refresh period of a refresh signal to the target refresh period; wherein the refresh signal is used to instruct to perform a refresh operation on the memory cell array.

Embodiments of the present application provide a display control method and device, a display device and a storage medium, and relate to the technical field of display. The method comprises: determining first and second display areas which are adjacently arranged based on the refresh rate of different areas on a display panel in a current frame, the refresh rate of the first display area being greater than that of the second display area; determining a transition area between the first and second display areas based on the first and second display areas, the transition area comprising at least one transition sub-area; and refreshing the first display area, the second display area and the transition sub-area within a preset refresh period, wherein the number of refreshes of the transition sub-area is greater than that of the second display area and less than that of the first display area within the preset refresh period.

An interaction method of an external object and a touch display device comprises the steps that an image refresh cycle of the touch display device comprises a plurality of display driving periods and a plurality of non-display driving periods, and the display driving periods and the non-display driving periods are alternated with each other; the plurality of non-display driving periods comprise a plurality of first touch periods and a plurality of second touch periods, each first touch period or each second touch period is a non-display driving period, and one image refresh cycle comprises at least two second touch periods located between at least two first touch periods (S410); and the external object includes an active object or a passive object, the touch display device receives a communication signal from the active object, senses a touch signal of the passive object via the touch sensor during a plurality of first touch periods to detect a touch of the passive object, and outputs the touch signal to the active object during the plurality of first touch periods. A touch signal of the active object is sensed via the touch sensor during a plurality of second touch periods to detect a touch of the active object (S420).

The present application relates to a brightness adjustment method and apparatus for a display panel, and a computer device. The method comprises: when the refresh rate of a display panel decreases from an initial refresh rate to a target refresh rate, for any image refresh period during display performed according to the target refresh rate, acquiring a plurality of pulses comprised in light emission holding phases of the image refresh period, and dividing the plurality of pulses into a plurality of groups; for each group, adjusting an initial duty cycle of a light emission control signal at the target refresh rate, so as to obtain a target duty cycle of the light emission control signal for the group; and on the basis of a target brightness value corresponding to each pulse in the light emission holding phases, and the target duty cycle, adjusting the widths of the pulses in each group, so as to adjust the brightness of the display panel at the target refresh rate. The method provided in the present application can effectively alleviate the flickering visual effect during a refresh rate decreasing process.

A method for refreshing a memory element, comprising: - generating a refresh address with a refresh period, - performing each refresh at a weak cell with a first address when the refresh address is a second address, instead of a first strong cell with the second address, and - performing each refresh at a first strong cell or a second strong cell with a third address when the refresh address is the third address, - wherein address information is stored for only one of the first, second, and third addresses, and / or wherein the third address is selected from a pool of addresses with a range defined by at least two least significant bits of one of the first and second addresses.

The application discloses a high-speed refreshing positioning method and system based on wireless signal processing, relates to the technical field of high-speed refreshing positioning, and specifically comprises the following steps: analyzing the period number of a signal data unit in a current refreshing period, judging whether there is a signal data unit with a period number not equal to the current period number, and starting a cross-period data synchronization state judgment process when the signal data unit exists and the number ratio exceeds a preset threshold; based on the time tag distribution, historical data ratio and source period number of the signal data unit in the current refreshing period, feature information for representing time consistency and period structure is extracted, and the feature information is input into a classification judgment function to determine the cross-period data synchronization state corresponding to the current refreshing period. The application solves the positioning mis-refreshing problem caused by cross-period data mispositioning, realizes refreshing control based on synchronization state judgment, and effectively improves positioning accuracy and system stability.

A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh a first word line and a first protected word line during a first refresh cycle in response to a refresh signal, a random number generator configured to receive an address of the first word line and an address of the first protected word line to generate a first number, a counter electrically coupled to the random number generator. The counter is configured to receive the first number as an initial value of the counter, and configured to be turned on in response to the refresh signal. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh a second protected word line, adjacent to the second accessed word line, during a second refresh cycle.

The invention relates to a software definition timeout detection method and system for processing PCIe packet blocking, and the method comprises the steps: generating a detection time period A according to an Egress Credit Timeout Desection Interval register, generating detection periods B according to an Egress Credit Timeout Refresh Cycle register, and when each detection period B starts, returning a credit depletion counter to zero to count again; monitoring whether the credaviil signal is continuously lowered or not in a detection time period A, if the credaviil [i] in the whole process is equal to 0 in the detection time period A, adding 1 to the value of the credit blocking counter, otherwise, not counting; the method comprises the following steps: detecting a credit blocking counter value of a detection period, adding 1 to the value of the detection period counter every time a detection time period A is passed, and when the end of a detection period B is reached, if the credit blocking counter is greater than or equal to a trigger threshold register Egress Credit Timeout Threshold, triggering Credit Timeout, and executing DPC function logic. According to the invention, the detection process is divided into two stages of detection interval and detection period, so that the bit width requirement of a single counter can be obviously reduced; and the trigger threshold can be flexibly configured on different levels.