85 results about "Refresh cycle" patented technology

A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

The application provides an instrument verification system, method, device and instrument, wherein the system comprises: a control module configured to acquire an accumulated quantity of an instrument to be tested when receiving a verification request; a display module connected to the control module and configured to acquire the accumulated quantity and update a display result according to the current accumulated quantity every interval of a preset time length; the preset time length is less than a refresh cycle of a metering display module of the instrument to be tested; the control module is further configured to receive the display result through a shooting module, determine a test change quantity according to the display result, and determine a verification result according to the test change quantity and a standard change quantity; and the shooting module obtains the display result by shooting the display module. Through the application, the instrument verification efficiency can be effectively improved.

A memory device comprises an input interface configured to receive an erase request indicating a memory portion to be erased and control circuitry configured to trigger erasing information stored by memory cells of at least a part of the indicated memory portion of the memory device by writing a predefined pattern into the memory cells during an automatic refresh cycle.

A memory system, a method for controlling the refresh of a memory device, and a memory device are provided. The memory system includes a memory controller and a memory device. The memory controller periodically generates refresh commands at an average refresh interval. The memory device performs a normal refresh operation and a hammer refresh operation during the refresh cycle time. The memory device includes: a memory cell array including memory cells connected to the plurality of word lines; a temperature sensor configured to provide temperature information by measuring the operating temperature of the memory cell array; and a refresh controller configured to control the normal refresh operation and the hammer refresh operation. The refresh controller changes the hammer rate, which is the number of hammer executions per unit of hammer refresh operation performed during the refresh cycle time relative to the number of normal executions per unit of normal refresh operation performed during the refresh cycle time.

The application discloses a noise reduction processing method and device and electronic equipment, and belongs to the technical field of electronic equipment. The noise reduction processing method comprises the following steps: in the case that the display screen of the electronic equipment is in a bright screen state, the display refresh rate of the display screen and the change amount of the target voltage in the display refresh period are acquired; the display refresh period corresponds to the display refresh rate; the target voltage is the voltage required by each pixel point of the display screen when displaying a picture; a corresponding target anti-interference strategy is determined based on the display refresh rate and the change amount of the target voltage; and display noise is subjected to noise reduction processing based on the target anti-interference strategy.

The invention discloses a memory detection and check method and system based on coding, and the method comprises the steps: setting a dual-refresh constant for each memory region in a memory corresponding to each processor, and each group of dual-refresh constants comprises two refresh constants which are opposite to each other; performing periodic memory refreshing on the memory by using double refreshing constants, wherein the period comprises an odd period and an even period; wherein in the odd period, one refreshing constant in the double refreshing constants is used for carrying out memory refreshing on the corresponding memory area, and in the even period, the other refreshing constant in the double refreshing constants is used for carrying out memory refreshing on the corresponding memory area; reading back the memory area after the memory is refreshed, and calculating a check word based on data obtained by reading back; and checking the check word obtained by calculation. According to the memory detecting and checking method and system based on coding, the condition that a specific bit in the memory is wrong can be effectively detected, and the reliability and safety of the system are improved.

This invention relates to an artificial intelligence storage system. A string comprises multiple sets of transistor pairs connected in parallel between a source line and a bit line, with each set containing a pair of source-interconnected storage transistors. The sources of both storage transistors in each set are connected to the source line, and the drains of both storage transistors are connected to the bit line. Multiple strings are mapped to multiple weight value carriers of a neural network. The input data for each set of transistor pairs in each string is refreshed periodically. In consecutively numbered sets of transistor pairs, if the difference between the effective pulse duration of any storage transistor in the previous cycle and the effective pulse duration in the next cycle exceeds a predetermined value, then the adjacent numbered transistor pairs of that set are locked for one refresh cycle during the periodic refresh of the input data, and unlocked after the locking ends to begin the next round of input data refresh.

A dynamic random access memory (DRAM) device includes an array of DRAM storage cells. Refresh control circuitry refreshes the DRAM storage cells within a refresh period. The refresh control circuitry includes circuitry to refresh, during a first sub-period of the refresh period, at least one row of the array of DRAM storage cells in a selected one of the multiple banks in response to receipt of an activate command from a memory controller that is directed to the selected one of the multiple banks. At the end of the first sub-period of the refresh period, a value is generated indicating a remaining number of refresh operations to refresh a remaining number of unrefreshed DRAM storage cells of the array of DRAM storage cells within a remaining period of the refresh period. Transmit circuitry transmits the value to the memory controller.

The application discloses a display panel and a display device. The working process of a pixel circuit in the display panel comprises a first data refresh period, a data adjustment stage, and a second data refresh period arranged in sequence. The data adjustment stage comprises T1 first sub-data adjustment stages and T2 second sub-data adjustment stages arranged in sequence. The number of data write frames in the first sub-data adjustment stage is greater than the number of data write frames in the second sub-data adjustment stage, and the number of hold frames in the first sub-data adjustment stage is less than the number of hold frames in the second sub-data adjustment stage. Therefore, the unstable situation of the input signal of the driving transistor caused by the first data refresh period can be quickly reversed before the second data refresh period, so that the flicker phenomenon of the picture observed by the human eye during the display picture switching can be avoided.

Embodiments of the present disclosure disclose a memory and an operating method thereof, a memory system and an electronic device. The memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit comprises: a temperature sensing circuit configured to sense a temperature of the memory and generate a temperature signal based on the sensed temperature; a control logic circuit configured to determine a target refresh period based on the temperature signal and a mapping table; wherein the mapping table comprises a plurality of preset temperature signals and a plurality of preset refresh periods, and the plurality of preset temperature signals and the plurality of preset refresh periods correspond one by one; and a refresh control circuit configured to adjust a refresh period of a refresh signal to the target refresh period; wherein the refresh signal is used to instruct to perform a refresh operation on the memory cell array.

Embodiments of the present application provide a display control method and device, a display device and a storage medium, and relate to the technical field of display. The method comprises: determining first and second display areas which are adjacently arranged based on the refresh rate of different areas on a display panel in a current frame, the refresh rate of the first display area being greater than that of the second display area; determining a transition area between the first and second display areas based on the first and second display areas, the transition area comprising at least one transition sub-area; and refreshing the first display area, the second display area and the transition sub-area within a preset refresh period, wherein the number of refreshes of the transition sub-area is greater than that of the second display area and less than that of the first display area within the preset refresh period.

The present application relates to a brightness adjustment method and apparatus for a display panel, and a computer device. The method comprises: when the refresh rate of a display panel decreases from an initial refresh rate to a target refresh rate, for any image refresh period during display performed according to the target refresh rate, acquiring a plurality of pulses comprised in light emission holding phases of the image refresh period, and dividing the plurality of pulses into a plurality of groups; for each group, adjusting an initial duty cycle of a light emission control signal at the target refresh rate, so as to obtain a target duty cycle of the light emission control signal for the group; and on the basis of a target brightness value corresponding to each pulse in the light emission holding phases, and the target duty cycle, adjusting the widths of the pulses in each group, so as to adjust the brightness of the display panel at the target refresh rate. The method provided in the present application can effectively alleviate the flickering visual effect during a refresh rate decreasing process.

A method for refreshing a memory element, comprising: - generating a refresh address with a refresh period, - performing each refresh at a weak cell with a first address when the refresh address is a second address, instead of a first strong cell with the second address, and - performing each refresh at a first strong cell or a second strong cell with a third address when the refresh address is the third address, - wherein address information is stored for only one of the first, second, and third addresses, and / or wherein the third address is selected from a pool of addresses with a range defined by at least two least significant bits of one of the first and second addresses.

This application discloses a refresh rate adjustment method and related equipment, belonging to the field of terminal technology. The method includes: at a first moment, a first application renders frames at a first running frame rate; the screen displays image data rendered by the first application at the first refresh rate; at a second moment, in response to a refresh rate switching command, the screen displays image data corresponding to the first application at a second refresh rate, where the second refresh rate is greater than the first refresh rate; the first application renders frames at the second running frame rate; if the second running frame rate is less than the first running frame rate, at a third moment, the screen displays image data corresponding to the first application at a target refresh rate, so that the first application renders frames at a third running frame rate greater than or equal to the first running frame rate; the frame rendering of the first application is synchronized with the screen refresh cycle. This application can ensure the smoothness of the image as much as possible.

The application discloses a kind of server low-power memory dynamic energy efficiency control method and system, belong to server storage technical field.The application is by collecting the running state data corresponding to each storage unit of server memory, generates the memory load prediction result in the set time range, simultaneously completes the hierarchical processing of memory storage data, based on load prediction result and hierarchical storage data matching and switches memory power supply operating mode, adjusts the refresh cycle of corresponding memory storage unit, again in combination with memory chip temperature data and the current effective power supply operating mode adjusts heat dissipation system operating parameter, completes the collaborative control of memory power consumption and heat dissipation.The application can realize energy efficiency dynamic optimization while guaranteeing the continuity of memory read-write operation, reduce the invalid energy consumption in the whole operation cycle of memory, avoid the performance decline caused by temperature fluctuation, improve the stability and energy efficiency level of memory operation.

A display panel (100) and a display apparatus. The display panel (100) comprises a substrate (10), a plurality of data lines (110), a plurality of gate lines (120), and a plurality of fan-out lines (130), wherein the plurality of fan-out lines (130) are correspondingly connected to at least some of the plurality of data lines (110); among at least some of the plurality of fan-out lines (130), each fan-out line (130) comprises a connection sub-segment (134) and a plurality of extension sub-segments (135), adjacent extension sub-segments (135) are connected by means of the connection sub-segment (134), and the plurality of extension sub-segments (135) comprise a first extension sub-segment (1351) and a second extension sub-segment (1352); and in the same refresh cycle, the display panel satisfies at least one of the following situations: at least one voltage jump moment of a pulse of a signal on at least one gate line (120) adjacent to the first extension sub-segment (1351) is different from a voltage jump moment of a pulse of a signal on a gate line (120) adjacent to the second extension sub-segment (1352), or an amplitude polarity of a pulse of a signal on at least one gate line (120) adjacent to the first extension sub-segment (1351) is different from an amplitude polarity of a pulse of a signal on a gate line adjacent to the second extension sub-segment (1352).

The invention discloses a method for realizing DRAM (Dynamic Random Access Memory) refresh, a processor core and a chip, and the method comprises the following steps: before a refresh cycle arrives in the processor core, a refresh controller notifies each DRAM controller to stop receiving a new data access request; in response to the notification, each DRAM controller stops receiving the new data access request and continues to execute the existing task until the task is completed; when the refresh cycle arrives, the refresh controller instructs each DRAM controller to refresh the memory block managed by the DRAM controller; each DRAM controller executes a refresh operation on the memory block managed by the DRAM controller.

The invention discloses a chip refresh cycle detection method, apparatus and device, and a storage medium, relates to the technical field of testing, and discloses a chip refresh cycle detection method, which comprises the steps of determining a plurality of test tRFCs based on a refresh cycle tRFC suggested value of a to-be-tested chip; performing continuous refreshing operation on the to-be-tested chip based on each test tRFC, and acquiring power consumption data corresponding to the to-be-tested chip in the continuous refreshing operation process; and determining a minimum refresh cycle corresponding to the to-be-tested chip based on the power consumption data and the test tRFC corresponding to each power consumption data. According to the method and the device, the continuous refreshing operation is executed on the to-be-tested chip through the plurality of test tRFCs, the power consumption data of the to-be-tested chip during refreshing according to each test tRFC is obtained, and the corresponding minimum refreshing period is accurately determined according to the power consumption data and the test tRFCs, so that the minimum refreshing period of the to-be-tested chip is accurately obtained.

The present disclosure provides a decoding method, an encoding method, a device, a computer-readable storage medium, and a product. The method comprises: receiving a bitstream file, wherein the bitstream file comprises a sequence header and a video frame bitstream; decoding the sequence header to obtain a refresh period and a video frame-related feature; and when determining that a current video frame reaches the refresh period, clearing the video frame-related feature stored in a local cache of a decoding end.

The application discloses a browser self-starting, self-refreshing and full-screen displaying method based on an Android system, which comprises the following steps: starting the system; determining the self-starting delay of the browser; hiding the label bar and the address bar of the browser interface and opening the browser in full screen; if a visitor logs in, the artificial intelligence combines the bandwidth, the current page data volume and the data volume of the subpage of the region with the greatest click possibility to determine the data refreshing period; if an account logs in, the artificial intelligence determines the data refreshing period according to whether there is an unfinished task, and the determination mode comprises the following steps: calculating and determining the data refreshing period corresponding to each region of the current interface according to the importance degree score Q, and determining the data refreshing period according to the hierarchical relationship between the webpages and the data volume. The self-starting delay is dynamically adjusted according to the remaining available memory, and the network construction and the browser starting time sequence are coordinated, so that the system resource competition is effectively avoided, the self-starting success rate and efficiency are improved, and the first loading failure caused by the unprepared network is avoided.

The application provides a frame playing method, an electronic device, a chip system and a storage medium, and relates to the technical field of electronic devices. When frames are played, a touch position is collected, a touch time is determined according to the touch position, too dense touch times can be filtered, and multiple touch times are prevented from being repeatedly mapped to the same video frame when dragging is slow. One video frame is displayed in each screen refresh cycle, and when multiple touch times are concentrated in one refresh cycle, the redundant touch times also need to be filtered. After filtering, the touch times are mapped to the nearest video frame or I frame, and the I frame is mapped when dragging is fast, which can reduce the decoding time. Since decoding is in a grouped form and can only be decoded to a specified frame in decoding order, in the case that a video frame to be rendered and displayed is not decoded in time, a substitute rendering display or a rendering display abandonment mode can be used to avoid the phenomenon of always waiting for the video frame to be decoded successfully before rendering and displaying.

The invention provides a local cache refreshing method, equipment and a product. The local cache refreshing method disclosed by the invention comprises the following steps: in response to a query request for a local cache, adding a timestamp of the query request to an ordered set table of a database; determining a dynamic access frequency according to the data identifier of the query request and the corresponding timestamp, and adding the dynamic access frequency to an ordered set table; determining N data identifiers which are ranked in the front from the ordered set table according to the dynamic access frequency; determining a dynamic refresh cycle according to the dynamic access frequency; and according to the dynamic refresh cycle, acquiring update data from the database for the N data identifiers, and updating the update data to a local cache.

The invention discloses a password input method and system based on a dynamic interactive interface, and the method comprises the following steps: generating a plurality of interactive elements in a password input region, enabling each element to have a randomly determined initial position in the current refresh cycle, a motion track selected from a preset track family and updated according to frames, and limited duration; based on the session ID and the shared key, adopting HMAC to generate a random seed, executing random permutation on an element identifier set, establishing a temporary mapping table of'element identifier-password character 'which is effective only in a corresponding refresh cycle, and completing synchronization and consistency confirmation with a server side; and receiving a click event of a user on the interactive element, mapping a hit element identifier into a corresponding password character and / or an equivalent code thereof in real time according to the temporary mapping table, writing the password character and / or the equivalent code into an input buffer area according to a click sequence, and recording an event timestamp.

This invention provides a display device and its driving method, driving circuit, apparatus, medium, and program product, relating to the field of display technology, for reducing the power consumption of display products. The driving method of the display device includes a display panel, the display panel including a gate driving circuit, and the gate driving circuit including a plurality of cascaded shift register units; a screen refresh cycle of the display device includes an active phase and a blanking phase; the driving method includes: generating a frame rate switching instruction based on pre-stored frame rate switching information; sending a corresponding switching timing driving signal to the gate driving circuit during at least part of the blanking phase according to the frame rate switching instruction; and controlling all or some of the shift register units in the gate driving circuit to output scan signals based on the switching timing driving signal.

The invention discloses a display compensation method and device and electronic equipment, and belongs to the technical field of electronic equipment. The display compensation method comprises the following steps: increasing the display refresh rate of the display device when the infrared sensing module emits infrared light; or brightness compensation values corresponding to the N refresh cycles in the compensation time period are obtained, and the brightness compensation values are used for enabling the offset of the brightness mean value of the infrared irradiation area in the image frame to be smaller than the offset threshold value; according to the brightness compensation values corresponding to the N refresh cycles, brightness compensation is carried out on target pixels in an infrared irradiation area in the image frame of the N refresh cycles in the compensation time period, the starting moment of the compensation time period is the moment when the infrared sensing module starts to emit infrared light, and the starting moment of the compensation time period is the moment when the infrared sensing module starts to emit infrared light. The cut-off time of the compensation time period is the recovery time after the pixel driving circuit is influenced by the infrared light.

The invention provides a DRAM differential refreshing method and system oriented to large model reasoning, a medium, a program product and a terminal. The method comprises the steps that model parameters correspondingly stored in all storage units in a DRAM in the large model reasoning process are obtained; and acquiring a corresponding DRAM access request period according to the type of the model parameter, comparing with each DRAM access request period based on a DRAM fixed refresh period, and executing a differential refresh strategy for each storage unit according to a comparison result. Different types of model parameters are utilized to correspond to different DRAM memory access request periods to execute differential refresh strategies, so that DRAM conventional refresh operations corresponding to a DRAM fixed refresh period in the DRAM can be reduced, a large amount of invalid refresh is avoided, bandwidth is released, redundant refresh operations are reduced, energy consumption is reduced, and data integrity is guaranteed.

The application discloses a memory read interference attack defense method and module based on adaptive probability tracking and belongs to the technical field of computer memory security, and comprises the following steps: in each refresh cycle, the following operations are performed: selecting a row activation event from all row activation events in the current refresh cycle by means of a reservoir sampling algorithm, and taking the corresponding memory row as an attack row; for each attack row, the memory rows within a preset range above and below the attack row are respectively divided into two candidate victim row sets, two memory rows symmetric to the attack row are selected as victim rows by means of the reservoir sampling algorithm, and the two victim rows are refreshed; wherein when the victim rows are selected by means of the reservoir sampling algorithm, sampling is performed according to the local sampling probability of each memory row, and the local sampling probability of the victim row farther away from the attack row in the same candidate victim row set is smaller. The application can reduce the probability of memory read interference attack escape and limit the attack propagation range.

The invention relates to the technical field of industrial automation control, in particular to a human-computer interface instantaneous waveform smooth display method and system. A frequency converter controller collects real-time data and stores the real-time data in a cache; the operation control unit reads the number of channels needing to be read in the real-time data command; the frequency converter controller extracts real-time data of the number of channels in the command at the same acquisition moment from the cache; a waveform display unit of the human-computer interface draws a continuous waveform; and the operation control unit judges whether the current waveform display is full of a screen or not, and if the current waveform display is not full of the screen, the data reading process continues to be executed. The method has the advantages that a high-precision acquisition timestamp is added to each data point, so that a human-computer interface can accurately draw on a time axis according to the real acquisition time of the data instead of depending on a fixed screen refresh cycle, the problem of waveform distortion caused by the fact that the data updating rate is lower than the display refresh rate is fundamentally solved, and the accuracy of the data updating rate is improved. The actual operation state of the frequency converter is truly reflected.

A refresh address counting circuit, a refresh address counting method, and a refresh address read-write circuit are provided. The refresh address counting circuit includes: a self-oscillation clock generation circuit, configured to generate, in each of refresh cycles, a self-oscillation clock signal based on at least one array activation signal upon acquiring a refresh signal; a self-oscillation mask circuit, configured to generate a self-oscillation mask signal under a preset refresh command; and a refresh address counter, configured to counting a refresh address based on the self-oscillation clock signal and the self-oscillation mask signal and to output a self-oscillation refresh address.