210 results about "Refresh cycle" patented technology

A self-refresh method of a semiconductor memory device including: receiving a self-refresh entry command; performing a self-refresh cycle based on the self-refresh entry command; receiving a self-refresh exit command; based on receiving the self-refresh exit command, determining a refresh operation status; and based on determining that the refresh operation status indicating an idle state, executing a care refresh operation corresponding to row-hammer care.

The invention relates to a timestamp rendering method and device, computer equipment and a readable storage medium. The method comprises the following steps: displaying a test interface comprising a first layer and a second layer; the first layer is used for displaying a timestamp; the second layer is used for displaying test information; under the condition that the current moment meets the refresh cycle, acquiring system time at the current moment, and acquiring a target image matched with character elements contained in the system time from the image set; and rendering the target image matched with each character element to the first layer so as to display the timestamp of the current moment in the first layer of the test interface. By adopting the method, the target image matched with each character element in the time can be rendered with the timestamp in another layer different from the layer for displaying the test information, so that the influence of the rendering timestamp on the rendering of the test information is avoided, meanwhile, memory jitter caused by high-frequency creation of character string objects and system object recovery can be avoided, and the test efficiency is improved. Therefore, the rendering efficiency of the timestamp is improved.

A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh a first word line and a first protected word line during a first refresh cycle in response to a refresh signal, a random number generator configured to receive an address of the first word line and an address of the first protected word line to generate a first number, a counter electrically coupled to the random number generator. The counter is configured to receive the first number as an initial value of the counter, and configured to be turned on in response to the refresh signal. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh a second protected word line, adjacent to the second accessed word line, during a second refresh cycle.

The invention discloses a laser processing error compensation method and a processing system, and the method comprises the following steps: based on target processing graphic data, setting a decomposition step length and a galvanometer refresh cycle of laser processing, and planning a target axis track and a target galvanometer track; before machining is started, the shaft is driven to move along a preset empty track, actual motion coordinate information on a plurality of preset points is recorded, and coordinate information of the next point position of the shaft is predicted according to the coordinate information; calculating deviation information based on the actual coordinate information of the current point location on the target axis track, and correcting the track between the current point location and the next point location of the axis by using the deviation information; obtaining the correction information of the galvanometer on the corresponding galvanometer track based on the correction information of the track between the current point location and the next point location of the shaft; and the correction information of the galvanometer is issued to the galvanometer to compensate the actual position of the galvanometer, and then laser machining is started. Various machining errors are effectively compensated, and the machining precision and the product quality are improved.

To provide a game machine in which a performance control operation is further improved.SOLUTION: A display device includes a display driving circuit which drives a group of display elements constituting a display screen, and an illumination circuit which illuminates the display screen. An integrated VRAM area of image producing means is configured so as to be repeatedly refreshed every predetermined refresh cycle and keep a memory content.SELECTED DRAWING: Figure 21

Provided display panel includes a pixel circuit and a light emitting element. The pixel circuit includes a drive module including a drive transistor, and a bias adjustment module configured to provide a bias adjustment signal to a first pole or a second pole of the drive transistor. Data refresh frequencies of the display panel include a first data refresh frequency F1 and a second data refresh frequency F2, where F1>F2. At the first data refresh frequency F1, the bias adjustment signal is Vf1, and at the second data refresh frequency F2, the bias adjustment signal is Vf2, where Vf1≠Vf2; or, at the first data refresh frequency F1, a duration of a bias adjustment stage in one data refresh period is T1, and at the second data refresh frequency F2, a duration of a bias adjustment stage in one data refresh period is T2, where T1≠T2.

Embodiments of the present invention relate to the technical field of computer graphics, and disclose a method, device, electronic device, and storage medium for image processing. The method for image processing in the present invention includes: sending the initial pose data of the terminal at the initial moment to the server, where the initial moment is a moment before the current moment; receiving the initial image data returned by the server according to the initial pose data, and the initial image data includes two-dimensional image data corresponding to the initial pose data; obtaining the target pose data of the terminal at the current moment; and adjusting the two-dimensional image data according to the initial pose data and the target pose data to obtain the target image data corresponding to the current moment. By adopting the embodiments of the present application, it is possible to avoid the problem that the virtual reality terminal cannot display an image corresponding to the terminal pose within the refresh period due to network delay, and at the same time reduce the hardware requirements of the virtual device.

The invention discloses a gate drive circuit and a display panel. The cascade adjustment module of the shift registers is used for adjusting a cascade output end to output a second power supply signal or a second clock signal according to signals on the first control node and the third control node, and the cascade output end of the ith-level shift register is electrically connected with the trigger write-in module of the (i + 1) th-level shift register; the output adjusting module is used for adjusting a scanning output end to output a target signal or a fourth power supply signal or a third clock signal according to a third control node, a signal on the cascade output end and the first control signal, the target signal comprises the third power supply signal or the fourth clock signal, and the scanning output end is used for being electrically connected with a pixel circuit; wherein the refresh cycle of the third clock signal is smaller than the refresh cycles of the first clock signal and the second clock signal. In the embodiment of the invention, the gate drive circuit can output complex waveforms to meet the requirements of the pixel circuit.

The invention relates to a display panel and a display device. The display panel comprises a substrate, a plurality of data lines, a plurality of gate lines and a plurality of fan-out lines, wherein the fan-out lines are correspondingly connected with at least part of the data lines; in at least a part of the fan-out lines, the same fan-out line comprises a sub-connection section and a plurality of sub-extension sections, the adjacent sub-extension sections are connected through the sub-connection section, the plurality of sub-extension sections comprise a first sub-extension section and a second sub-extension section, and in the same refresh cycle, the first sub-extension section is connected with the second sub-extension section. At least one voltage jump moment of a pulse of a signal on at least one gate line adjacent to the first sub-extension section is different from a voltage jump moment of a pulse of a signal on a gate line adjacent to the second sub-extension section; the amplitude polarity of the pulse of the signal on at least one gate line adjacent to the first sub-extension segment is different from the amplitude polarity of the pulse of the signal on the gate line adjacent to the second sub-extension segment. Therefore, according to the display panel and the display device provided by the invention, the brightness uniformity of the display panel can be improved.

A method for obtaining a row hammer refresh address, including: after a row hammer refresh signal arrives, obtaining a current sampling address, and determining whether a high address is locked in a current row hammer refresh cycle; in response to the high address being locked, determining whether a high address of the current sampling address is identical to the locked high address; in response to being identical, updating an access frequency of the locked high address, and updating access frequencies of low addresses with a low address of the current sampling address; and when a next row hammer refresh signal arrives, using a low address with a highest access frequency stored in the group of low registers as a low address of the row hammer refresh address, and using the locked high address as a high address of the row hammer refresh address.

The invention discloses a system and a method for realizing the rhythm effect of an atmosphere lamp of a smart television, and the method comprises the following steps: a, audio feature extraction: obtaining the analog signal sampling values of a plurality of sound channels when the smart television plays music in real time, carrying out the sampling of each sound channel for multiple times in a fixed period, extracting the maximum sampling value of each sound channel, and obtaining the audio feature; determining a global maximum sampling value X; b, converting the number of the lamp beads: calculating the number of the lamp beads which need to be lighted currently through a preset algorithm based on the global maximum sampling value X, the current volume value Y and the total number Z of the atmosphere lamp beads; c, generating a gradual change effect: generating a gradual change color sequence based on a difference value between the starting RGB value and the ending RGB value according to the number of the lamp beads needing to be lightened, and distributing color values according to the serial number of the lamp beads so as to realize a rhythm gradual change effect; and d, dynamic control: dynamically adjusting a lamp bead refresh cycle according to a music playing state, and turning off the atmosphere lamp and stopping sampling in a non-music scene.

The invention discloses a high-speed refresh positioning algorithm and system based on wireless signal processing, and relates to the technical field of high-speed refresh positioning, and the algorithm specifically comprises the following steps: analyzing the cycle number of a signal data unit in a current refresh cycle, judging whether there is a signal data unit with the cycle number not equal to the current cycle number, and if yes, executing the following steps; when the signal data units exist and the number ratio of the signal data units exceeds a preset threshold value, a cross-cycle data synchronization state judgment process is started; and on the basis of the time label distribution, the historical data proportion and the source period number of the signal data units in the current refresh period, extracting feature information used for representing time consistency and a periodic structure, and inputting the feature information into a classification discrimination function to determine a cross-period data synchronization state corresponding to the current refresh period. According to the method, the problem of positioning mistaken refreshing caused by cross-cycle data dislocation is solved, refreshing control based on synchronous state judgment is realized, and the positioning accuracy and the system stability are effectively improved.

A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

A memory device with internal row hammer mitigation is coupled to a memory controller. A memory controller or host may assist row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an additional refresh command, the memory device may perform a refresh for row hammer mitigation, rather than a refresh for standard data integrity. The memory controller may maintain a tracking of the number of activation commands sent to the memory device, and in response to a threshold number of activation commands, the memory controller sends additional refresh commands. With additional refresh commands, the memory device may refresh a potential victim row of the potential aggressor row rather than only rows that have not been accessed for a period of time.

The application provides an instrument verification system, method, device and instrument, wherein the system comprises: a control module configured to acquire an accumulated quantity of an instrument to be tested when receiving a verification request; a display module connected to the control module and configured to acquire the accumulated quantity and update a display result according to the current accumulated quantity every interval of a preset time length; the preset time length is less than a refresh cycle of a metering display module of the instrument to be tested; the control module is further configured to receive the display result through a shooting module, determine a test change quantity according to the display result, and determine a verification result according to the test change quantity and a standard change quantity; and the shooting module obtains the display result by shooting the display module. Through the application, the instrument verification efficiency can be effectively improved.

A memory device comprises an input interface configured to receive an erase request indicating a memory portion to be erased and control circuitry configured to trigger erasing information stored by memory cells of at least a part of the indicated memory portion of the memory device by writing a predefined pattern into the memory cells during an automatic refresh cycle.

A memory system, a method for controlling the refresh of a memory device, and a memory device are provided. The memory system includes a memory controller and a memory device. The memory controller periodically generates refresh commands at an average refresh interval. The memory device performs a normal refresh operation and a hammer refresh operation during the refresh cycle time. The memory device includes: a memory cell array including memory cells connected to the plurality of word lines; a temperature sensor configured to provide temperature information by measuring the operating temperature of the memory cell array; and a refresh controller configured to control the normal refresh operation and the hammer refresh operation. The refresh controller changes the hammer rate, which is the number of hammer executions per unit of hammer refresh operation performed during the refresh cycle time relative to the number of normal executions per unit of normal refresh operation performed during the refresh cycle time.

The application discloses a noise reduction processing method and device and electronic equipment, and belongs to the technical field of electronic equipment. The noise reduction processing method comprises the following steps: in the case that the display screen of the electronic equipment is in a bright screen state, the display refresh rate of the display screen and the change amount of the target voltage in the display refresh period are acquired; the display refresh period corresponds to the display refresh rate; the target voltage is the voltage required by each pixel point of the display screen when displaying a picture; a corresponding target anti-interference strategy is determined based on the display refresh rate and the change amount of the target voltage; and display noise is subjected to noise reduction processing based on the target anti-interference strategy.

According to one implementation of the present disclosure, a cache memory includes: a plurality of cache-lines, wherein each row of cache-lines comprises: tag bits of a tag-random access memory (tag-RAM); data bits of a data-random access memory (data-RAM), and a single set of retention bits corresponding to the tag-RAM. According to one implementation of the present disclosure, a method includes: sampling a single set of retention bits of a cache-line of a cache memory, where the cache-line comprises the single set of retention bits, tag-RAM and data-RAM, and where at least the single set of retention bits comprise eDRAM bitcells; and performing a refresh cycle of at least the data-RAM corresponding to the tag-RAM based on the sampled single set of retention bits.

An asynchronous communication system configured to operate a MIL-1553 protocol. The system includes: a bus; a bus controller coupled to the bus that is configured to control access to the bus; a remote terminal connected to the bus; a device controller connected to the remote terminal; and a read / write overlap avoidance latch connected to the remote terminal. The read / write overlap avoidance latch provides an active signal to the device controller that prevents the device controller from writing data to the remote terminal while the bus controller is reading data from the device controller during a read cycle.

The invention discloses a memory detection and check method and system based on coding, and the method comprises the steps: setting a dual-refresh constant for each memory region in a memory corresponding to each processor, and each group of dual-refresh constants comprises two refresh constants which are opposite to each other; performing periodic memory refreshing on the memory by using double refreshing constants, wherein the period comprises an odd period and an even period; wherein in the odd period, one refreshing constant in the double refreshing constants is used for carrying out memory refreshing on the corresponding memory area, and in the even period, the other refreshing constant in the double refreshing constants is used for carrying out memory refreshing on the corresponding memory area; reading back the memory area after the memory is refreshed, and calculating a check word based on data obtained by reading back; and checking the check word obtained by calculation. According to the memory detecting and checking method and system based on coding, the condition that a specific bit in the memory is wrong can be effectively detected, and the reliability and safety of the system are improved.

Disclosed is a semiconductor memory device that includes a memory cell array including a plurality of memory banks, a command decoder configured to decode a per-bank refresh command and a remaining bank refresh command received from an external source, and a refresh controller configured to control the cell array to perform a per-bank refresh operation for refreshing one memory bank among the plurality of memory banks that is based on a decoding result of the per-bank refresh command of the command decoder, wherein the refresh controller is configured to perform a remaining bank refresh operation for refreshing remaining memory banks other than the one memory bank among the plurality of memory banks, in response to the remaining bank refresh command during one refresh cycle.

A memory device and a method for protecting the same are provided. The memory device includes: a random number generator, a counter, and a controller. The random number generator includes a first logic gate and a second logic gate configured to generate a first output and a second output, respectively, according to the address of the first word line and the address of the first accessed word line. The random number generator further includes a switch configured to select one of the first output and the second output to be a first number. The counter is configured to receive the first number and count down from the first number. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh adjacent word lines of the second accessed word line during a second refresh cycle.

A network interface device operates in a normal transmit mode of operation in which the network interface device continuously receives transmission symbols from a link partner via a communication link. The network interface device determines that receiving circuitry of the network interface device transitions to a low power mode in response to receiving a sleep signal from a link partner. The network interface device then operates according to a silence / refresh cycle of the low power mode to conserve power. The silence / refresh cycle corresponds to a schedule that includes a refresh time window within which receive circuitry of the network interface device is to be energized to receive a refresh signal from the link partner. Upon transmitting the sleep signal, the network interface device transitions to a silent time window of the timeschedule within which the network interface device ignores transmissions from the link partner.

This invention relates to an artificial intelligence storage system. A string comprises multiple sets of transistor pairs connected in parallel between a source line and a bit line, with each set containing a pair of source-interconnected storage transistors. The sources of both storage transistors in each set are connected to the source line, and the drains of both storage transistors are connected to the bit line. Multiple strings are mapped to multiple weight value carriers of a neural network. The input data for each set of transistor pairs in each string is refreshed periodically. In consecutively numbered sets of transistor pairs, if the difference between the effective pulse duration of any storage transistor in the previous cycle and the effective pulse duration in the next cycle exceeds a predetermined value, then the adjacent numbered transistor pairs of that set are locked for one refresh cycle during the periodic refresh of the input data, and unlocked after the locking ends to begin the next round of input data refresh.

Embodiments of this application provide a wake-up method and an electronic device, and are applied to the field of terminal technologies. When it is detected that the electronic device enters a deep suspend state, the electronic device can automatically reboot, so that the electronic device restores to normal, and can be normally used by a user, thereby improving user experience. In the method, the electronic device starts timing. Suspend duration is obtained if a working state of the electronic device is a suspend state when timing duration reaches a preset refresh period, where the suspend duration is a difference between a moment at which the electronic device enters the suspend state and a timing refresh moment. The electronic device triggers, if the suspend duration is greater than or equal to a first preset threshold, an operation of rebooting a system.

A network interface device operates in a normal transmit operating mode in which the network interface device continually receives transmission symbols from a link partner via the communication link. The network interface device determines that receive circuitry of the network interface device is to transition to a low power mode in response to receiving a sleep signal from the link partner. The network interface device then operates according to a quiet / refresh cycle of the low power mode to conserve power. The quiet / refresh cycle corresponds to a time schedule that includes a refresh time window in which receive circuitry of the network interface device is to be powered to receive a refresh signal from the link partner Immediately after transmission of the sleep signal, the network interface device transitions to a quiet time window of the time schedule in which the network interface device ignores transmissions from the link partner.

A dynamic random access memory (DRAM) device includes an array of DRAM storage cells. Refresh control circuitry refreshes the DRAM storage cells within a refresh period. The refresh control circuitry includes circuitry to refresh, during a first sub-period of the refresh period, at least one row of the array of DRAM storage cells in a selected one of the multiple banks in response to receipt of an activate command from a memory controller that is directed to the selected one of the multiple banks. At the end of the first sub-period of the refresh period, a value is generated indicating a remaining number of refresh operations to refresh a remaining number of unrefreshed DRAM storage cells of the array of DRAM storage cells within a remaining period of the refresh period. Transmit circuitry transmits the value to the memory controller.

The invention provides an open circuit detection method and system based on an MBI5034 chip, a medium, a program and an electronic terminal, and the method comprises the steps: building a mapping relation between each brightness level and display lightening duration in a frame of image through employing a binary rule, and enabling each brightness level to have display turn-off time in a refresh cycle; setting the display turn-off time corresponding to all the brightness levels at the tail end of the refresh cycle; the image data updating operation is executed at the tail end of the last refresh cycle, the open circuit detection triggering action is executed at the starting end of the current refresh cycle, and the image display operation is executed after the open circuit detection is triggered, so that the image data updated in the last refresh cycle is displayed, and the black screen phenomenon caused by open circuit detection is eliminated.

The application discloses a display panel and a display device. The working process of a pixel circuit in the display panel comprises a first data refresh period, a data adjustment stage, and a second data refresh period arranged in sequence. The data adjustment stage comprises T1 first sub-data adjustment stages and T2 second sub-data adjustment stages arranged in sequence. The number of data write frames in the first sub-data adjustment stage is greater than the number of data write frames in the second sub-data adjustment stage, and the number of hold frames in the first sub-data adjustment stage is less than the number of hold frames in the second sub-data adjustment stage. Therefore, the unstable situation of the input signal of the driving transistor caused by the first data refresh period can be quickly reversed before the second data refresh period, so that the flicker phenomenon of the picture observed by the human eye during the display picture switching can be avoided.