Dram cam cell with hidden refresh

Abstract

A Dynamic Content Addressable Memory (DCAM) cell topology that contains fewer that can perform a "hidden" refresh of stored data that does not delay nor interrupt the CAM search cycle, thereby providing SCAM-like performance. A non-destructive read operation, is performed such that the stored-data does not have to be written back because of a refresh-read operation. A reliable CAM search can be performed after a read operation and before or even while the refresh-data is being written back. Soft-error detection processes can be performed on each CAM entry during the pendency of the refresh cycle. The DCAM cell can be used in a digital system such as a digital computer and a Network Router.

Description

[0001] 1. Technical Field

[0002] The invention relates generally to semiconductor memory devices, and more specifically to a Dynamic Content Addressable Memory (DCAM) Cell.

[0003] 2. Related Art

[0004] Modern telecommunication networks comprise digital data networks that transmit data in packets or blocks containing address fields for dynamically routing the data packets or blocks through the network (e.g., to the destination address) at high speeds. The fastest searching of stored data may be accomplished using a Content Addressable Memory (CAM).

[0005] As the size of networks (e.g., intranets and the Internet) increase the need for larger CAM arrays increases, and accordingly, the need to attach more CAM cells to a common bit line increases. Content Addressable Memory (CAM) arrays of the related art are generally implemented with either conventional Static RAM (SRAM) or conventional destructive-read Dynamic RAM (DRAM) hardware designs, and therefore have all the disadvantages and limi...

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