1653results about "Digital storage" patented technology

The embodiment of the invention discloses an in-memory computing circuit based on a magnetic cache, and the circuit comprises at least one magnetic cache unit, at least one in-memory computing unit, and a timer. The magnetic cache unit in the at least one magnetic cache unit is used for caching data output by the corresponding in-memory computing unit as to-be-processed data within the corresponding data retention time; the timer is used for respectively setting data retention time for the at least one magnetic cache unit; and the in-memory computing unit in the at least one in-memory computing unit is used for extracting the data to be processed from the corresponding magnetic cache unit for calculation and outputting the computed data to other magnetic cache units. According to the embodiment of the invention, the invention achieves the flexible adjustment of the data retention time of the magnetic cache unit in various in-memory calculation scenes, and achieves the provision of a high-capacity cache for the data needed by in-memory computing under the lower power consumption.

Embodiments of the present application provide a driving circuit and a driving method thereof, a display panel and a display device. The driving circuit is used for driving a pixel circuit. The pixel circuit comprises a driving transistor, a gate reset transistor, a data write transistor and a threshold value capture transistor which are electrically connected with the driving transistor. The driving circuit comprises a plurality of cascaded shift register units. The shift register unit comprises a first type signal output module and a second type signal output module. The output end of the first type signal output module is electrically connected with the gate of the gate reset transistor and / or the threshold value capture transistor. The output end of the second type signal output module is electrically connected with the gate of the data write transistor. The present application can reduce the number of peripheral driving circuits required by the pixel circuit, which is conducive to realizing narrow frame and low power consumption of the display panel.

A method of operating a nonvolatile memory device is provided. The method includes: performing a program operation on a selected word-line of a plurality of cell strings during a program execution period of a program loop by applying a program voltage to the selected word-line; and performing a program verification operation during a program verification period of the program loop by applying a program verification voltage to the selected word-line and by applying a first verification pass voltage to a first zone of unselected word-lines among and a second verification pass voltage to a second zone of the unselected word-lines. A voltage level of the second verification pass voltage is lower than a voltage level of the first verification pass voltage.

An interactive communication apparatus, which connects to a computer, comprises an interactive communication device, having a tag, that is removably placed on or adjacent to an interactive communication device holder, having a sensor, wherein the tag communicates information to the sensor. The interactive communication system enables a user to transfer, store or retrieve information about and / or to a person that is identified with that interactive communication device. Once the interactive communication device is placed on or adjacent to the interactive communication device holder, certain communication applications, which include, photo slideshow, chat, e-mails, music, videos, and RSS feed, launch. The user can terminate the applications by removing the interactive communication device from the interactive communication device holder. The user can access content related to a new person by placing another interactive communication device, that corresponds to the new person, on or adjacent to the interactive communication device holder.

This disclosure relates to the field of semiconductor circuit design, and particularly to amplifier circuits, control methods, and memories, including: a sensing amplifier circuit, including a readout node, a complementary readout node, a first node, and a second node; an isolation circuit coupled to the readout node, the complementary readout node, a bit line, and a complementary bit line; the isolation circuit is configured to couple the readout node to the bit line and the complementary readout node to the complementary bit line during the sensing amplification phase; an offset cancellation circuit coupled to the bit line, the complementary bit line, the readout node, and the complementary readout node; the offset cancellation circuit is configured to couple the bit line to the complementary readout node and the complementary bit line to the readout node during the offset cancellation phase; and a processing circuit coupled to the offset cancellation circuit, configured to acquire the memory temperature and adjust the duration of the offset cancellation phase based on the memory temperature to dynamically adjust the processing time of the offset cancellation phase based on the temperature to optimize memory performance.

A semiconductor memory device and a memory system are provided. The semiconductor memory device includes memory cells, local bit lines, global bit lines, word lines, control lines, local bit line multiplexers, and first and second control contacts. The memory cells are arranged along a first direction, a second direction, and a third direction. Each local bit line extends along the first direction and is shared by the memory cells adjacent to a first side and a second side of each local bit line. The global bit lines are disposed on the local bit lines. The control lines are disposed on the word lines. Each word line and each control line extends along the third direction. The local bit line multiplexers control electrical connections between the local bit lines and the global bit lines. At least two of the local bit line multiplexers share one of the control lines. The first and second control contacts are connected to first and second ends of the control lines, respectively. Each of the first and second control contacts extends along the first direction.

A photonic random access memory employs series connected photosensors to define switching nodes driving optical modulators, the series connection operating to reduce the effect of photosensor dark current.

A memory device includes several computing memory cells each storing a weight value and comprising a first and a second switch elements and a first and a second resistors. The first switch element receives a sensing current and a first input signal related to the input value. The first resistor selectively receives the sensing current through the first switch element in response to the first input signal. The second switch element receives the sensing current and a second input signal related to the input value. The second resistor selectively receives the sensing current through the second switch element in response to the second input signal. When the sensing current flows through the first resistor or the second resistor, the computing memory cell generates a first voltage difference or a second voltage difference corresponding to an output value equal to product of an input value and a weight value.

In some examples, a method for minimising bit flips in memory write operations comprises partitioning a data word to be written into a memory into multiple chunks, wherein each chunk comprises a respective number of bits, grouping the multiple chunks into multiple partitions, wherein each of the multiple partitions comprises a plurality of the multiple chunks, permutating the chunks within each of the multiple partitions, whereby to obtain multiple encoded codewords, wherein each of the multiple encoded codewords comprises metadata describing a permutation applied to the partition in order to obtain the codeword, selecting the encoded codeword of the multiple encoded codewords that has a smallest Hamming distance to the previous codeword, and writing the selected codeword in the memory.

The application discloses a kind of analog field full-precision in-memory computing circuit and method based on magnetic tunnel junction computing unit, including 3 transistor 2 magnetic tunnel junction (3T2M) magnetic random access memory (MRAM) computing array, pulse generation circuit, timing control circuit, accumulation circuit, multiplexer, input sensitive parallel analog / digital converter (Flash ADC), enable signal generation circuit and digital shift accumulator.The invention realizes built-in multiplication operation in in-memory computing mode using 3T2M computing unit and improves computing unit yield through two complementary magnetic tunnel junctions (MTJ), based on Kirchhoff's current law, uses parallel transistor and capacitor to realize accumulation operation.Compared with traditional von Neumann architecture accelerator and existing MRAM analog field in-memory computing architecture, the application can effectively adapt to sparse vector matrix multiplication accumulation operation, reduce power consumption overhead and improve circuit energy efficiency.

A memory device comprising a stacking structure including a plurality of electrodes and an insulation layer between the plurality of electrodes. The stacking structure has a recess portion corresponding to the plurality of electrodes or the insulation layer at a side surface of the stacking structure. The memory device also comprising a resistance variable layer on the side surface of the stacking structure having the recess portion, and includes a portion extending in an extension direction crossing the stacking structure. The resistance variable layer includes a first portion including a first expanded portion along a recess surface of the recess portion, a second portion including a second expanded portion along the recess surface of the recess portion on the first portion, and a third portion on the second portion. The second portion has a resistance smaller than a resistance of the first portion.

Apparatuses and techniques are described implementing power-efficient monitoring for usage-based-disturbance mitigation. In a first aspect, a memory device takes a less strict approach for monitoring worse-case conditions associated with usage-based disturbance. In particular, the memory device conserves power by foregoing updating a list of rows associated with worse-case conditions until an unlisted row has a substantially worse condition than any one of the listed rows. This decreases how often the memory device expends power to update the list. In an optional second aspect, the memory device performs a partial bit-width comparison operation to evaluate the “substantially worse” criterion. The partial bit-width comparison enables a comparator to be implemented with a smaller footprint and operate with less power as compared to a comparator that is capable of performing a full bit-width comparison operation.

The application discloses a continuous resonator network computing method based on a resistive memory array, and belongs to the fields of semiconductors, analog computing and integrated circuits. The application sequentially decomposes resonator network computing into three parts of logic computing, matrix-matrix-vector multiplication operation and sign taking computing, and sequentially connects a feedback loop formed by a logic element, a resistive memory array and an operational amplifier to realize hardware, takes a voltage corresponding to a to-be-decomposed hyper vector as input, and obtains a voltage of a corresponding decomposition signal at an output end after the circuit is stable, so that self-convergent resonator network computing in a continuous time domain is realized. Compared with existing resonator network computing implementation schemes, the application can fully exert the performance advantages of analog computing, does not need discrete iteration and data transfer, thereby reducing hardware overhead and operation complexity, and greatly improving speed, energy efficiency and area efficiency.

The application relates to the technical field of storage testing, and discloses a DRAM data retention time testing method, device, equipment and medium. The method comprises the following steps: writing all storage units of a DRAM to a first state; taking each storage unit of the DRAM as a target storage unit in sequence, writing the target storage unit to a second state for each target storage unit, reading data of the target storage unit, determining a data retention time of the target storage unit based on a data reading result; and determining a data retention time of the DRAM based on the data retention times of all target storage units. The capacitor charges in all storage units are cleared, the target storage unit is written to make one storage unit in the DRAM store data "1", a severe environment encountered by the DRAM in actual operation is constructed, and the data retention time of the DRAM is tested again, so that the accuracy of the determined data retention time is improved.

Embodiments provide a semiconductor memory device and method capable of reducing the amount of data that needs to be held in advance in a memory controller as much as possible without compromising data reliability. The circuit of the semiconductor memory device of the embodiments sets the threshold voltages of a plurality of memory cells in a manner that two first distributions are formed in a first interval on the lowest voltage side among two intervals. N After that, the circuit sets the threshold voltages of the plurality of memory cells in a manner that two second distributions are formed separately in units of two. (1+M) After that, the circuit sets two third distributions in the two intervals. N N ​​

The application discloses an in-memory computing circuit, a control method and a chip, relates to the technical field of integrated circuits, and the in-memory computing circuit comprises a transmission line and at least one in-memory computing subcircuit, and the in-memory computing subcircuit comprises: a storage module, two ends of the storage module are respectively connected with a first bit line and a second bit line; a first switch, the first switch is connected with an analog-digital conversion circuit through the transmission line; and a decoupling module, the second bit line is connected with a control end of the first switch through the decoupling module, in the in-memory computing operation, the storage module controls on-off of the first switch through the decoupling module, so as to improve linearity between voltage change of the second bit line and a calculation result. The application can make the bit line voltage and the calculation result present a linear relationship, reduce quantization error of the analog-digital conversion circuit, and improve accuracy of the in-memory computing system.

Systems, methods, and apparatus are provided for a pillar selector for wafer-on-wafer memory. A plurality of pillars can include an array of memory cells on a die, semiconductor material below the plurality of pillars, and a plurality of buried recessed access device (BRAD) transistors formed in the semiconductor material. Each of the plurality of BRAD transistors are coupled to a respective one of the plurality of pillars and configured to selectively couple the respective pillar to a sense line.

The application provides a ferroelectric random access memory and an electronic device, data is stored through a transistor and a plurality of capacitors, which not only increases the capacity of the ferroelectric random access memory, but also improves the storage density of the ferroelectric random access memory. The ferroelectric random access memory provided by the application can include one or more storage units. The storage unit can include a transistor and a plurality of capacitors. The plurality of capacitors can correspond to a plurality of capacitor lines one by one. The first end of each capacitor in the plurality of capacitors can be used to connect with a corresponding capacitor line, and the second end of each capacitor can be used to connect with the first pole of the transistor. The control pole of the transistor can be used to connect with a word line, and the second pole of the transistor can be used to connect with a bit line. The transistor can be used to select any one capacitor in the plurality of capacitors according to the voltages of the capacitor line, the word line and the bit line. Each capacitor is used to store data.

A system and technique for buffering data locally within a memory device to allow access to data associated with a plurality of different rows within the memory device. The memory device includes a storage bank circuit having memory cells and a sense amplifier circuit coupled to the storage bank circuit. The memory device also includes a buffer circuit coupled to an output of the sense amplifier circuit. In addition, the memory device includes a selection circuit. The selection circuit receives a first data signal from the sense amplifier circuit and a second data signal from the buffer circuit and outputs a selected one of the first data signal and the second data signal.

It suppresses transistor degradation. [Solution] The method comprises a first period and a second period. In the first period, the first transit The zista and the second transistor repeatedly switch on and off alternately, and the third transistor and The fourth transistor is turned off. During the second period, the first transistor and the second The transistor turns off, and the third and fourth transistors turn on alternately. It repeatedly switches between being on and off. In this way, the time the transistor is on can be shortened. Therefore, it suppresses the degradation of transistor characteristics.

This invention discloses a phase-change memory (PCM) device simulation system and method, relating to the field of computer technology. The system includes: a physics engine module that receives an operation request and calculates physical quantity data of the memory unit based on the device's physical parameters, simulation configuration parameters, and phase-change state data of the memory unit; a state controller module that controls the phase-change process of the memory unit based on changes in the physical quantity data and generates corresponding phase-change commands; a crystallinity and melting rate update module that updates the crystallinity and melting rate of the memory unit based on the phase-change commands and physical quantity data to obtain the phase-change state data of the memory unit and upload it to the physics engine module; and an energy consumption statistics module that monitors the voltage, current, and time parameters in the physical quantity data, calculates the energy consumption for each operation cycle, and generates an energy consumption analysis report. This enables accurate simulation of the entire process of PCM devices, improves simulation accuracy and efficiency, shortens the cycle time, and provides reliable support for device optimization and main control design.

A semiconductor memory device capable of performing a suitable write operation is provided. The device performs a write operation including a plurality of first write cycles each including a first programming operation of supplying a first programming voltage to a first conductive layer and supplying a first write path voltage smaller than the first programming voltage to a second conductive layer, the first programming voltage being increased by a first offset voltage as the number of the first write cycles increases, and an erase operation including a programming voltage control operation including a plurality of second write cycles each including a second programming operation of supplying a second programming voltage to a third conductive layer and supplying a second write path voltage smaller than the second programming voltage to a fourth conductive layer, the second programming voltage being increased by a second offset voltage as the number of the second write cycles increases, the magnitude of the first programming voltage being adjusted according to the magnitude of the second programming voltage, and an erase voltage supply operation of supplying an erase voltage to the first wiring after the control operation is performed.

Integrated circuit structure, comprising: an SRAM cell (10) (SRAM: static random access memory), comprising: a first pull-up MOS device (PU-1) (MOS: metal oxide semiconductor) and a second pull-up MOS device (PU-2), and a first pull-down MOS device (PD-1) and a second pull-down MOS device (PD-2), forming inverters cross-locked to the first pull-up MOS device (PU-1) and the second pull-up MOS device (PD-2); an elongated contact (54) located over and electrically connected to a source of the first pull-down MOS device (PD-1); a first metal layer (M1) containing a bit line and a CVdd line; a first CVss contact island (52B) overlapping the elongated contact (54) and is electrically connected to this, wherein the first CVss contact island (52B) has a part in the SRAM cell (10) which has a first length and a first width,which are smaller than a second length and a second width of the SRAM cell (10), wherein the SRAM cell (10) has a first boundary (10A) and a second boundary (10B) that are parallel to each other, and a third boundary (10C) and a fourth boundary (10D) that are parallel to each other, and the first CVss contact island (52B) overlaps the first boundary (10A) and the fourth boundary (10D) but does not extend beyond the second boundary (10B) and the third boundary (10C); a first word line (50) having a first longitudinal direction, wherein the first word line (50) extends from the third boundary (10C) to the fourth boundary (10D), wherein the first word line (50) and the first CVss contact island (52B) are located in a second metal layer (M2) above the first metal layer (M1), and wherein the first word line (50) forms a strip portion (50A) and has a protruding part (50B),which is connected to a part of a first side wall of the strip section (50A) in the first longitudinal direction and extends in a direction perpendicular to the first longitudinal direction, wherein the projecting part (50B) extends in the direction of the first boundary (10A) and is spaced from the first boundary (10A) and further extends from the third boundary (10C) in the direction of the fourth boundary (10D) and is spaced from the fourth boundary (10D), wherein the CVss contact island (52B) and the projecting part (50B) are spaced apart by a distance S1 so that they do not electrically short-circuit, wherein the word line has a width W1 and the projecting part (50B) has a width W2 and wherein 0.1 <= W2 / W1 <= 0.5,wherein the width of the first word line (50) is increased by the projecting part (50B) and thereby the resistance of the first word line (50) is reduced; and a first CVss line (58) in a third metal layer (M3) above the second metal layer (M2), wherein the first CVss line (58) is electrically connected to the first CVss contact island (52B) and has a second longitudinal direction that is perpendicular to the direction of the first longitudinal direction.

A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

Control logic in a memory device receives a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and performs a first coarse valley tracking calibration operation on the segment of the memory array. The control logic further configures a read voltage level and one or more parameters associated with the read operation based on a result of the first coarse valley tracking calibration operation and performs a second fine valley tracking calibration operation on the segment of the memory array using the configured read voltage level and the configured one or more parameters.

In a method of operating a storage device including a first storage device and a second storage device connected to each other via a host device, a data migration request for a first namespace included in the first storage device is received. A second namespace is generated in the second storage device. The second namespace corresponds to the first namespace. A pointer table for performing a data migration operation corresponding to the data migration request is set. First data and second data are migrated to the second namespace based on the pointer table. The first data is stored in the first namespace. The second data is stored in a first buffer memory included in the first storage device and corresponds to the first namespace. Based on the data migration operation being performed, the second data is directly sent from the first buffer memory to the second namespace.

Embodiments of the present application provide a shift register and a driving method thereof, a light emitting control circuit and a display device. The shift register is electrically connected with a first signal line and a second signal line respectively. The first signal line is a trigger signal line or a cascade line between the shift register and other stage shift registers. In a first working mode, the shift register outputs a first driving signal in response to a first signal of the first signal line. In a second working mode, the shift register outputs a second driving signal in response to a second signal of the second signal line. The embodiments of the present application can solve the problem that the working mode of the shift register in the related art is relatively single.

A method of operating a non-volatile memory device includes receiving a suspend command at the non-volatile memory device, suspending a programming operation being performed at the non-volatile memory device in response to the suspend command, receiving a resume command at the non-volatile memory device, and resuming the suspended programming operation at the non-volatile memory device in response to the resume command. The programming operation includes programming cycles, each of the programming cycles including a bit line set interval, a program interval, and a verify interval. A level of a program voltage to be applied to selected memory cells of the non-volatile memory device is increased by a first voltage in the program interval of each of the programming cycles. A difference between a level of a program voltage last applied before the suspension and a level of a program voltage first applied after the resume is different from the first voltage.

A semiconductor memory device that receives a data DQ signal and a data strobe DQS signal from an external device includes a DQS clock tree including a first DQS input buffer that receives the DQS signal for sampling the DQ signal, and a DQS oscillator that simulates a path of the DQS clock tree using a second DQS input buffer and one or more repeaters. The DQS oscillator matches an input terminal voltage of the second DQS input buffer to an input terminal voltage of the first DQS input buffer using a termination circuit.

Spin-Hall (SH) material (135) is provided near free regions (110) of magnetoresistive devices that include magnetic tunnel junctions (110, 115, 120). Current flowing through such SH material injects spin current into the free regions such that spin torque is applied to the free regions. The spin torque generated from SH material can be used to switch the free region or to act as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction, in order to improve the reliability, endurance, or both of the magnetoresistive device. Further, one or more additional regions or manufacturing steps may improve the switching efficiency and the thermal stability of magnetoresistive devices.