1949 results about "Random access memory" patented technology

The embodiment of the invention provides memory equipment based on a computing fast link protocol and a control method. The memory device comprises a plurality of dynamic random access memories, a plurality of nonvolatile memories and a controller of the memory device, wherein the controller comprises a CXL subsystem; the cache manager is used for storing a cache table recording the mapping relation between the physical address of the equipment and the cache address; the controller of the dynamic random access memory is set to perform read or write operation on the dynamic random access memory according to the cache address; and the controller of the nonvolatile memory is set to perform read or write operation on the nonvolatile memory according to the equipment physical address so as to write the data from the dynamic random access memory into the nonvolatile memory, or read out the data from the nonvolatile memory so as to store the data into the dynamic random access memory. According to the embodiment of the invention, based on the existing server architecture, the expansion of the memory is realized, and the use cost of the memory is reduced.

The invention relates to a ZNS SSD-based B + tree index construction method for dynamic placement of cold and hot data. A persistent memory PM, a dynamic random access memory DRAM and a ZNS SSD hard disk are included. The persistent memory PM and the dynamic random access memory DRAM are directly connected with a CPU memory bus and have the capability of being accessed by the CPU according to bytes; internal nodes of the B + tree are stored in a dynamic random access memory (DRAM), and the internal nodes only store index information used for positioning leaf nodes; the pseudo leaf nodes of the B + tree are stored in a persistent memory PM, and only the key index information of the leaf nodes is stored in the pseudo leaf nodes; leaf nodes really storing the key value pairs in the B + tree are divided into hot leaf nodes and cold leaf nodes according to the data access frequency, the hot leaf nodes are stored in a persistent memory PM, and the cold leaf nodes are stored in a ZNS SSD. According to the method, the leaf nodes are quickly positioned by using the DRAM, so that the query time is shortened; hot leaf nodes are stored in the PM, and the real-time service read-write requirement is met; and hot data is stored in a high-speed DRAM and PM, so that the random read-write delay is reduced, and the performance is excellent in scenes such as big data analysis and the like.

A method for training or performing inference using a neural network involves performing per-layer decompression and compression of neural network weights. More particularly, compressed weights are retrieved for a particular layer of the neural network. The weights correspond to neurons in the layer. The compressed weights are decompressed, and input data for that layer is subsequently processed using the decompressed weights. This dynamic decompression and recompression of weights allows memory, and in particular random access memory of graphical processing units, to be efficiently used.

An accelerator architecture is presented for a Transformer machine learning model. The accelerator is comprised of: one or more memory devices, each memory device has a random access memory and is configured for processing in memory, where a key matrix, a value matrix, a query weight matrix, a key weight matrix, and a value weight matrix for an attention mechanism of the Transformer machine learning model are stored in the one or more memory devices; and a control device interfaced with each of the one or more memory devices, the control device is used to coordinate the vector matrix multiplication operations performed on the memory devices, perform other arithmetic and logic operations used in attention blocks that are not suited for the memory devices, and coordinate the updates of the key and value matrices in the one or more memory devices.

The invention discloses a lattice-based cryptographic algorithm-oriented side channel attack-resistant NTT circuit, which comprises a control unit, which is mainly used for controlling the enabling of a bottom layer component in the structure and the data flow direction among modules; the storage unit is used for storing the coefficient, the random twiddle factor address and the twiddle factor; the address generation unit is used for calculating and generating a storage RAM (Random Access Memory) address of a twiddle factor participating in operation and a read address required by the coefficient storage unit; and the coefficient transposing unit is used for realizing coefficient reading meeting the index distance among all NTT stages. According to the side channel attack resisting NTT circuit oriented to the lattice-based cryptographic algorithm, when a low delay base-4CT / GS butterfly unit is masked, the increment of modular multiplication resources is reduced, and the resource consumption is remarkably reduced while high security is kept.

An information handling system may determine a personality flag value during a boot process and execute, responsive to detecting that the information handling system entered a secure environment and based on the personality flag value, a system update handler configured for discovering and connecting to a control plane. The system may also provision a secure ephemeral operating system, including receiving an image of the secure ephemeral operating system from the control plane responsive to a secure profile and validating the image prior to loading the secure ephemeral operating system to a random access memory.

An integrated circuit includes a host interface coupled to a host device executing a tenant operating system (OS) on bare metal and hardware accelerator(s) coupled to the host interface and a network interface. The hardware accelerator(s) receive, over the host interface, a snapshot request relating to a snapshot of tenant OS. Snapshot request includes a location, in a physical memory of the host device, of a swap file having contents of random access memory of the host device. The hardware accelerator(s) encrypt the swap file and initiate transfer of the encrypted swap file to a network storage device coupled to a cloud-based server. The hardware accelerator(s) send, over the network interface, to a snapshot manager hosted by the cloud-based server, metadata associated with storing the encrypted swap file in the cloud-based server, to allow the snapshot manager to manage the snapshot of the tenant OS.

Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.

The invention relates to the technical field of system-on-chip service interrupt processing, in particular to a hardware Sequence-based SoC interrupt processing method, which comprises the following steps of: pre-programming an interrupt processing instruction sequence into an instruction random access memory (RAM), and configuring an instruction set, a sequence processor and an interrupt priority strategy of a task scheduler Sequence; receiving the interrupt signal by a task scheduler, and selecting a corresponding sequence processor according to an interrupt type; for the interrupt with low priority, the Sequencer directly executes the pre-stored instruction sequence to complete the interrupt response; and for high-priority interruption, the Sequencer caches the state of the register and sends a message packet to notify the CPU to perform cooperative processing. According to the method, interrupt autonomous response is achieved through hardware Sequence, zero CPU intervention is achieved in low-priority interrupt, a lightweight message mechanism is adopted in high-priority interrupt, and bandwidth occupation and power consumption are reduced while efficiency is improved.

The invention belongs to the field of chip design, and provides a packet bus interconnection architecture of an SoC system, which comprises a system bus matrix SYSBUSMatrix, at least one processor bus matrix CBM, at least one high-speed peripheral bus matrix HPBM, at least one memory bus matrix RBM and one low-speed peripheral bus matrix SPBM, the CBM, the HPBM, the RBM and the SPBM are all connected with the SYSBUSMatrix through a bus bridge; the embedded processor is mounted on the CBM, and meanwhile, the CBM is connected with the RMB; a high-speed peripheral is mounted on the HPBM, and meanwhile, the HPBM is connected with the RMB; a random access memory (RAM) is mounted on the RBM, and meanwhile, the RBM is connected with the CBM and the HPBM; the SPBM is connected with a plurality of paths of AHB buses through an AXI-AHB bridge, the SPBM is connected with a plurality of paths of APB buses through an AXI-APB bridge, meanwhile, the SPBM is connected with SYSBUSMatrix, and a plurality of paths of low-speed peripherals are mounted on the AHB buses or the APB buses. According to the method, bus transmission among modules such as a processor, a high-speed peripheral and a storage can be balanced, bus competition among high-speed interfaces is effectively reduced, data transmission efficiency is improved, chip rear-end implementation is simplified, and therefore the performance of the whole SOC is optimized.

A system in package platform includes a processor chip having a runtime processor core, an accelerator core and a processor-memory interface exposed on a chip-to-chip bonding surface, a first memory chip such as 3D NAND flash memory storing a collection of executable models of inference engines, and a second memory chip storing weights of a selected executable model. The second memory chip can comprise a nonvolatile, random access memory, such as phase change memory. Direct vertical connections such as via-to-via connections, are provided between the processor chip and the second memory chip.

A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.

The embodiment of the invention discloses a static random access memory in-memory computing system and method, and the system comprises a feature memory which is used for storing an input signal of a neural network model; the SRAM storage array is used for storing each weight of the neural network model and performing logical operation on an input signal and each weight to obtain a plurality of logical operation results, each weight is divided into a plurality of binary blocks after CSD coding, complementary mode blocks are reserved after processing of eliminating all-zero mode blocks, and each binary block is divided into a plurality of binary blocks; after information is extracted from each complementary mode block, an index, a symbol and a value are obtained, and each weight is stored in a complementary mode block mode; the metadata storage is used for storing indexes and symbols; the adder tree is used for performing decoding and additive operation on the plurality of logical operation results according to the indexes and the symbols; the shift accumulation unit is used for performing shift accumulation on the addition result; and the post-processing unit is used for post-processing the shift accumulation result to obtain an output signal of the neural network model.

Sensor data may be received from a plurality of sensors installed on a vehicle and characterizing driving conditions of the vehicle. The sensor data may be continuously stored in a ring buffer implemented using a random access memory (RAM). A recording trigger to record event data related to a driving event of the vehicle may be received. A subset of sensor data may be extracted from the ring buffer, based on the recording trigger. The subset of the sensor data may be recorded in an event file in a second memory.

The invention discloses a digital filter and a filtering processing method, the digital filter comprises a single-port random access memory, an operation module and a control module, and the control module writes a filtering parameter group corresponding to a current filtering task into the single-port random access memory; each filtering parameter group comprises a filtering coefficient and an input sample; the control module reads sub-data groups from the single-port random access memory according to a first-in first-out sequence and distributes the sub-data groups to the computing units in an idle state, each sub-data group comprises a filtering sub-coefficient and an input sub-sample, the filtering sub-coefficient is a part of the filtering coefficient, and the input sub-sample is a part of the input sample; and the control module is also used for obtaining a corresponding output sample according to a final result of the calculation unit participating in the current filtering task, and writing the output sample into the single-port random access memory. According to the invention, a small-size digital filter is realized, and the requirement of a digital filter with a smaller nanometer level is met.

In a matrix of SOT-MRAM cells, a first row is selected for writing and a second row is selected for reading. A first SOT-MRAM cell of the first row and a second SOT-MRAM of the second row are in a first column, while a third SOT-MRAM cell of the first row and a fourth SOT-MRAM of the second row are in a second column. The currents for writing the first SOT-MRAM cell and the third SOT-MRAM cell are in opposite direction. A first sense amplifier is configured to detect a voltage change on the first read bit line which is charged with a first read current in the second SOT-MRAM cell. A second sense amplifier is configured to detect a voltage change on the second read bit line which is discharged with a second read current in a fourth SOT-MRAM cell.

The invention discloses a heterogeneous Chiplet hybrid precision Transformer acceleration system based on an MRAM-SRAM (Magnetic Random Access Memory-Static Random Access Memory), which adopts a Chiplet block integration technology, gives full play to the modularization advantages of high yield and low cost of the Chiplet block integration technology, and internally integrates two types of heterogeneous calculation cores of MRAM calculation Chiplet and SRAM-NPU calculation Chiplet and two types of scheduling management Chiplet and data interaction Chiplet control units. In a Transform calculation process, an MRAM (Magnetic Random Access Memory) calculates a Chiplet to carry out approximate token relationship prediction in a self-attention mechanism, an SRAM-NPU (Synchronous Random Access Memory-Network Processing Unit) calculates the Chiplet to realize accurate attention calculation by utilizing a high-speed read-write characteristic of an SRAM (Static Random Access Memory) and a flexible calculation capability of the NPU, meanwhile, a scheduling management Chiplet coordinates calculation task allocation, and a data interaction Chiplet ensures efficient data flow; according to the acceleration system, optimal combination of different process node devices is realized through a Chiplet heterogeneous integration technology, and three dimensions of calculation efficiency, energy consumption and precision are balanced by combining the high-density low-power-consumption storage and calculation integrated advantage of an MRAM and high-precision calculation of an SRAM-NPU.

A first command including data to be stored in non-volatile random access memory (NVRAM) of a storage device is received from a storage system controller by a storage device controller. In response to receiving the first command, the data is stored in the NVRAM. One or more second commands including a location in flash memory of the storage device for storing the data and an instruction to store the data in the location of the flash memory are received from the storage system controller. In response to receiving the one or more second commands, the data is stored in the location of the flash memory.

Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. The random access memory is configured to store input data from a sensor, parameters of a first portion of an Artificial Neural Network (ANN), instructions executable by the Deep Learning Accelerator to perform matrix computation of the first portion of the ANN, and data generated outside of the device according to a second portion of the ANN. The Deep Learning Accelerator may execute the instructions to generate, independent of the data from the second portion of the ANN, a first output based on the input data from the sensor and generate a second output based on a combination of the data from the sensor and the data from the second portion of the ANN.

The invention discloses a single event upset reinforced magnetic random access memory reading circuit, and belongs to the field of nonvolatile memories. Interlocked transistors are added on the basis of a traditional 6T reading circuit, meanwhile, a PMOS tube and an NMOS tube are introduced, and errors caused by the single event upset effect can be effectively corrected. The method has the following advantages that single event effect sensitive nodes are considered, zero upset nodes do not exist in the reinforcement method, meanwhile, 1 upset can be rapidly corrected, the single event upset resistance is higher, and the method can be used for reliable storage of data in the space radiation environment.

The embodiment of the invention provides a function test method and device for a random access memory and a storage medium, and belongs to the technical field of memories. The method comprises the following steps: configuring a test function instruction, an input parameter item and an output verification item corresponding to the test function instruction, and a parameter combination mode corresponding to the input parameter item in a preset test view; determining a plurality of target input data of the test function instruction according to the input parameter item and the parameter combination mode; calling a test template of the test function instruction, and generating a plurality of test cases according to the test template and the plurality of target input data; generating a verification script according to the output verification item; issuing a test instruction to a target random access memory according to the test case; and querying a test result from the target random access memory according to the verification script and outputting the test result. The embodiment of the invention can improve the test efficiency.

A semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.

Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth long distance communication, e.g. photonic or electronic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; one or more computational devices configured for simultaneously launching a plurality of data signals including memory read and / or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the one or more computational devices for transferring the data therebetween.

The invention discloses a reading static noise margin measurement method of a static random access memory, computing equipment and a storage medium. The method comprises the following steps: acquiring test data of a static random access memory, and extracting test voltage of each chip; carrying out format conversion on the test voltage; and performing curve fitting interpolation on the test voltage after format conversion to obtain a first fitting curve and a second fitting curve, obtaining a fitting curve intersection point for the first fitting curve and the second fitting curve, then calculating the maximum square side length on the curves on the left side and the right side of the intersection point, and further judging the reading static noise margin of the static random access memory. According to the method, the RSNML value and the RSNMR value can be more accurately determined by utilizing curve fitting interpolation and interpolation operation, the dependence on experiences of engineers is reduced, and the estimation error is reduced. According to the method, the automation, the accuracy, the efficiency and the reliability are remarkably improved, and a novel efficient tool is provided for the field of SRAM design and test.

A clock domain crossing (CDC) circuit receives a first data. The CDC circuit includes a first buffer and a second buffer. The first buffer includes a single-clock static random-access memory. The second buffer includes a plurality of data flip-flops. Logic coupled to the first buffer and the second buffer can determine that first buffer is not full at a first time. Responsive to the determination that the second buffer is not full at the first time, the processing logic can bypass the first buffer to write the first data to the second buffer according to the first clock domain. The processing logic can provide the first data as output from the second buffer according to the second clock domain.

A synergistic approach to mitigating crosstalk in a Dynamic Random-Access Memory (DRAM) implements the use of a random number generator to increment a counter in a probabilistic manner. The counter is formed by reclaiming bytes of a double data rate (DDR) fault isolation feature. The random number generator value may be compared against a predetermined parameter value and a determination may be made whether or not to extract and increment the counter based on a result of the comparison. A logic controller compares the counter value to a predetermined hotness threshold parameter and a flag is set based on an existence of an address match in local memory. Based on the results of the comparison, access to the DRAM is reduced.

A magnetic tunnel junction (MTJ) stack, a vertical side surface of the MTJ stack includes a saw tooth edge, the MTJ stack includes vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, the free layer of the MTJ stack has a tapered edge including a first width at an upper portion of the free layer and a second width at a lower portion of the free layer, the first width is greater than the second width. Forming a first bottom electrode of a first MTJ stack, a second bottom electrode of a second MTJ stack, a first inter-layer dielectric between the first and the second bottom electrode, a first reference layer of the first MTJ stack, a second reference layer of the second MTJ stack, a second inter-layer dielectric between the first reference layer and the second reference layer.

The invention provides a magnetic random access memory and a preparation method thereof. The magnetic random access memory is applied to a comparison circuit, and comprises a magnetic tunnel junction comprising a free layer, a barrier layer and a reference layer which are stacked in sequence; the spin-orbit torque layer is located on the side, away from the reference layer, of the free layer, the conductive material layer is located on the side, away from the spin-orbit torque layer, of the magnetic tunnel junction, and a conductive material of the conductive material layer has the following characteristics that spontaneous magnetization capacity is achieved, and the resistance temperature coefficient is smaller than 0; the conductive material layer comprises a first part and a second part which are arranged at an interval, the first part is in contact with the reference layer, a first input end of the comparison circuit is electrically connected with the first part, and a second input end of the comparison circuit is electrically connected with the second part. According to the invention, the technical problems that the reading window of the magnetic tunnel junction becomes small and even the reading is wrong and the magnetic random access memory needs to apply an auxiliary magnetic field along the current direction to realize the deterministic overturning of the magnetic moment are at least solved.

The invention discloses a storage circuit and a random access memory. The storage circuit comprises a control chip and a storage chip, wherein the storage chip is connected with the control chip; wherein one of the control chip and the storage chip comprises a redundancy repairing module, and the control chip is configured to obtain information of a damaged storage unit in the storage chip according to a preset triggering requirement; the redundancy repair module is configured to store the information of the damaged storage unit and send a redundancy replacement address to the storage chip based on the information of the damaged storage unit in response to the storage operation instruction so as to execute the corresponding storage operation. By means of the mode, the storage circuit can repair the damaged storage unit in the storage chip in real time through the redundancy repair module in the use process of the random access memory, so that the stability of the random access memory is improved, and the possibility that the random access memory reads and writes data mistakenly is reduced.

The embodiment of the invention provides a resource scheduling system, method, device and equipment, a medium and a product, and the resource scheduling system comprises a host end and a substrate management controller chip. Video data processing sub-modules, random access memory management control modules and a random access memory resource overall management control scheduling module are carried on the substrate management controller chip, and each video data processing sub-module is correspondingly provided with one random access memory management control module. Obtaining random access memory resource information corresponding to each video data processing sub-module; and determining a public random access memory corresponding to each video data processing sub-module according to the random access memory resource information, and storing the video data to be shunted. According to the application, the random access memory resource in each sub-module in the video processing path is taken as an integral resource for management and control; the defect that random access memory resources in each sub-module can only be used by the current sub-module is avoided.