119 results about "Random access memory" patented technology

A photonic random access memory employs series connected photosensors to define switching nodes driving optical modulators, the series connection operating to reduce the effect of photosensor dark current.

Disclosed in the embodiments of the present application are a root file system loading method and a related apparatus. In the method, a part of a virtual memory is simulated as a random access memory disk (RAMDISK) mechanism used by a block device. First, a read-only memory file system (ROMFS) mirror image file on an initial physical address is acquired; and then, a virtual address corresponding to the initial physical address of the ROMFS mirror image file is directly used as the starting address of the block device, such that the copy operation of copying the ROMFS mirror image file to the block device is executed on the initial physical address, thereby formatting the block device. Then, a kernel can be booted by means of mounting the ROMFS mirror image file in the block device as a root file system. By using the ROMFS image file as a root file system and reducing copy operations during a boot process, the kernel boot time is shortened in read‑only application scenarios requiring fast boot, thereby achieving fast kernel boot.

By having a non-secure CPU handle MACsec key management, this semiconductor device provides a solution that compensates for the performance shortcomings of a secure CPU. [Solution] The semiconductor device comprises a RAM storing an encryption key, a secure CPU capable of accessing the encryption key stored in the RAM, and a first non-secure CPU connected to the RAM via a key access protection module and having a first user ID. The key access protection module stores user ID information of the non-secure CPU that is permitted to access the encryption key stored in the RAM, linked to the encryption key. When the first non-secure CPU attempts to access the encryption key stored in the RAM, the key access protection module grants the first non-secure CPU access to the encryption key if the stored user ID information matches the first user ID.

A system to generate true random numbers includes a RAM array, a null-read controller and a hash generator. The RAM array has memory cells and a sense amplifier. The memory cells store data therein, the cells are connected in rows to word lines and in columns to pairs of bit lines, and the sense amplifier senses a differential input signal. The null-read controller implements a null-read operation by the sense amplifier of a portion of the RAM array. The hash generator receives a null-read result from the null-read operation and outputs a partial true random number based on the null-read result.

Aspects of the present disclosure provide a method of fabricating a resistive random access memory (RRAM). For example, the method can include providing a substrate, forming a first electrode on the substrate, and forming a first metal oxide layer on the first electrode. The first metal oxide layer can act as a sink or reservoir of oxygen atoms that interact with a current conducting filament. The method can further include forming a second metal oxide layer on the first metal oxide layer. The second metal oxide layer can be configured to form conduction paths. The method can further include forming a second electrode on the second metal oxide layer. In an embodiment, the first metal oxide layer can be formed on a portion of the first electrode.

This invention provides a method for implementing complementary logic based on magnetic random access memory (MRM). The method includes: applying an initial voltage and an initial current to the control terminal of a first MLM and a common control terminal of a second MLM, causing the first and second units to be in a logically complementary initial magnetization state; applying a logic input voltage to the common control terminal and a logic input current to the first and second units, causing the first and second units to obtain corresponding first magnetization states based on their respective initial magnetization states, enabling the first unit to perform an AND logic operation; applying a logic inverse signal of the initial voltage to the control terminal of the first unit, applying a logic inverse signal of the logic input voltage to the common control terminal, and applying a logic inverse signal of the logic input current to the second unit, causing the second unit to obtain a second magnetization state based on its corresponding first magnetization state, enabling it to perform an XOR logic operation. This achieves integrated storage and computation.

The application relates to the technical field of computers, in particular to a chip serial port loading retransmission system and method. The system comprises a chip and a serial port tool; the chip comprises a processor, a static random access memory, a serial port module and a watchdog module; the processor is used for executing the configuration of the serial port module, the issuing of instructions and the analysis of a starting program; the static random access memory is used for storing stack data in the process of executing the program by the processor and storing starting program data transmitted from the serial port module; the serial port module is used for receiving instructions from the processor and receiving starting program data transmitted from outside the chip; the serial port module is used for sending a serial port retransmission flag according to the starting state of the chip; the watchdog module is used for counting down, and when the watchdog is not disabled after a certain time, the watchdog triggers a system soft reset restart; the serial port tool comprises a plurality of program files.

A system and method for providing a neural network model to an artificial intelligence (AI) field programmable gate array (FPGA) are provided. A flash memory stores a neural network model. A tunnel is created between a flash memory and a random access memory (RAM) over a multi-line serial peripheral interface (QSPI) interface. Using the tunnel, the RAM reads one or more layers of the neural network model from the flash memory and writes the one or more layers into pages in the RAM. The AI FPGA reads the one or more layers of the neural network model from the RAM over a wide input / output interface and executes the one or more layers.

A transaction method includes initializing a first read counter according to a first predefined read count by a microcontroller unit (MCU), writing data to a cache by a first processing element, reading the data from the cache by a second processing element, transmitting a first read done message from the second processing element to the MCU after the data of the cache is read by the second processing element, decrementing the first read counter according to the first read done message by the MCU, and transmitting a first frame-discard cache maintenance operations (CMO) command from the MCU to the cache when the first read counter is decremented to zero.

Systems, devices, and methods related to a deep learning accelerator and memory are described. For example, a wearable electronic device may be configured to execute instructions with matrix operands and configured with: a housing to be worn on a person; a sensor having one or more sensor elements generate measurements associated with the person; random access memory to store instructions executable by the deep learning accelerator and store matrices of an artificial neural network; a transceiver; and a controller to monitor an output of the artificial neural network, generated using the measurements as an input to the artificial neural network. Based on the output, the controller may control selective storage of measurement data from the sensor, and / or selective communication of data from the wearable electronic device to a separate computer system.

A stacked die device includes a first master dynamic random access memory (DRAM) die having a first command interface to receive first commands and a first data interface to transfer first data. A second master DRAM die is stacked with the first master DRAM die and includes a second command interface to receive second commands that are independent of the first commands, and a second data interface to transfer second data that is independent of the first data. The first and second master DRAM die form respective portions of first and second memory channels. A third DRAM die is stacked with the first and second master DRAM die and includes a first selectively-enabled data input / output (I / O) circuit coupled to the first master DRAM die. A fourth DRAM die is stacked with the other die, and includes a second selectively-enabled data input / output (I / O) circuit coupled to the second master DRAM die.

The application provides a data transmission method under an automobile open system architecture, which comprises the following steps: creating a complex device driver socket module on a transmission control protocol / internet protocol layer; pre-allocating a random access memory via the complex device driver socket module and locking the pre-allocated random access memory; transmitting data in the locked random access memory via the complex device driver socket module; counting the number of times of transmitting data in the pre-allocated random access memory; in response to the number of times of transmitting data being greater than a predetermined threshold, calling a transmission confirmation function to confirm whether the transmission is completed and releasing the random access memory resource for completing the transmission. The method and interrupt scenario provided by the application can send frames without RAM limitation. In a large data transmission scenario, this mode does not cause frequent in-out interrupts, so that the whole system runs more smoothly.

This invention discloses a SOT-MRAM device, belonging to the field of magnetic random access memory technology. The SOT-MRAM device includes, from bottom to top, a bottom electrode, a spin orbital layer, a magnetic tunnel junction, an antiferromagnetic coupling layer, and a top electrode. The current propagation direction in the spin orbital layer is the same as its own long axis direction. The magnetic moment of the magnetic tunnel junction is perpendicular to its own film surface direction. The magnetic tunnel junction includes a free layer with bulk vertical anisotropy. An inclined sidewall is formed on one side of the free layer using an etching process, creating a continuous thickness gradient along the short axis of the spin orbital layer. This invention introduces structural asymmetry through the thickness gradient of the free layer, breaking the symmetry and replacing the effect of the traditional external magnetic field to achieve zero-magnetic-field flipping.

Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source / drain feature and a second source / drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source / drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source / drain feature.

In one embodiment, the invention provides a memory cell having a first and second optical modulator. Each optical modulator has a light input and at least one light output and receives an electrical input determining a switching state of the optical modulator defining a switching of light between the light input and light output. A first photodiode is connected to conduct current to a first node when illuminated, and a second photosensor is connected to conduct current away from the first node when illuminated. Similarly, a third photosensor is connected to conduct current to a second node when illuminated, and a fourth photosensor is connected to conduct current away from the second node when illuminated. The first and second optical modulators control light directed to at least one of a respective photosensor and have their electrical inputs connected to one of the first and second nodes to provide bistable switching states.

This invention relates to a stability optimization method for static random access memory (SRAM). It constructs a SRAM cell structure with separate read and write paths and establishes a basic stability model. Based on real-time monitoring of threshold deviations and extraction of environmental parameters according to the operating state, it calculates compensation parameters based on the stability state vector and performs adaptive adjustments. It also calculates the substrate compensation voltage and dynamically adjusts the read and write timing of the SRAM array based on the state vector. Based on the compensation parameters, it performs compensation adjustment and dynamic scheduling of the SRAM array, evaluates stability based on the execution results, and generates feedback information. Dynamic scheduling and conflict management implemented through a state machine ensure the orderly execution of read and write operations and data integrity. Combined with a feedback mechanism, it achieves closed-loop stability control, achieving a synergistic optimization effect that improves the stability and energy efficiency of SRAM cells under dynamic operating conditions, while also considering reliability and real-time performance.

This invention discloses an accelerated convolutional neural network operation system, computing device, and computer storage medium. The operation system includes a first static random access memory (SRAM), a global-local buffer, and a cluster of operation units. The first SRAM stores the data required for the entire convolution operation. The global-local buffer stores frequently accessed data during the convolution operation. The cluster of operation units includes multiple operation units for performing multiplication and accumulation operations. The global-local buffer includes: an input feature map buffer for storing input feature map data and providing data sequentially according to a predefined loop order; a weight buffer, which includes a second SRAM, a feature map temporary storage area, and a first loop engine; and a partial sum buffer for storing partial summation results, including a third SRAM and a second loop engine. This invention is applicable to convolutional neural networks.

This invention proposes a large-scale language model inference system and method. The large-scale language model inference system includes a first computing unit. The first computing unit is used to set a model file to be inferred and select an inference framework for inferring the large-scale language model based on the model file. The first computing unit detects hardware performance information of multiple dynamic random access memories (DRAMs) and multiple video random access memories (VRAMs) and obtains multiple model loading parameters. The first computing unit allocates model data of the large-scale language model to at least one of the DRAMs and VRAMs based on the hardware performance information and the multiple model loading parameters. The first computing unit operates at least one of the DRAMs and VRAMs to perform inference operations on the large-scale language model based on at least one inference output filtering parameter.

The present disclosure relates to systems, devices, and methods related to deep learning accelerators and memory. An integrated circuit can be configured to execute instructions with matrix operands and configured with a random access memory configured to store instructions executable by the deep learning accelerator and matrices of an artificial neural network, a connection between the random access memory and the deep learning accelerator, a first interface to a memory controller of a central processing unit, and a second interface to an image generator, such as a camera. While the deep learning accelerator processes a current input to the artificial neural network using the random access memory to generate a current output from the artificial neural network, the deep learning accelerator can concurrently load a next input from the camera into the random access memory; meanwhile, the central processing unit can concurrently retrieve a previous output from the random access memory.

An exemplary magnetoresistive random-access memory (MRAM) cell is configured to store more than one bit. The MRAM cell includes a first magnetic tunneling junction (MTJ) and a second MTJ connected in parallel. The first MTJ has a first diameter, the second MTJ has a second diameter, and the second diameter is less than the first diameter. The MRAM cell further includes a transistor connected to the first MTJ and the second MTJ, a bit line connected to the first MTJ and the second MTJ, a word line connected to the transistor, and a source line connected to the transistor. A method of writing to the MRAM cell can include supplying one or more write voltages to the MRAM cell (e.g., having different levels) depending on an initial memory state and a desired memory state of the MRAM cell.

This invention discloses a dynamic random access memory (DRAM) and its manufacturing method, relating to the field of memory technology, to reduce the parasitic capacitance of memory cells. The DRAM includes a substrate and a plurality of memory cells. Each memory cell includes a first transistor and a second transistor disposed along the thickness direction of the substrate, with the second transistor located on the first transistor. The first transistor includes a first stacked structure, a first channel layer, a first gate dielectric layer, and a first gate. The first channel layer covers a second isolation layer and the inner wall of a first opening, the first gate dielectric layer is located on the first channel layer, and the first gate is located within a first via formed by the first gate dielectric layer. The second transistor includes a second stacked structure, a second channel layer, a second gate dielectric layer, and a second gate. The second channel layer covers a third conductive layer and the inner wall of a second opening, the second gate dielectric layer is located on the second channel layer, and the second gate is located at least within a second via formed by the second gate dielectric layer.

An image display method and a related device. In a scenario where a partial region (ROI), i.e., a first region (ROI), in a display panel is refreshed, a display processing unit (DPU) acquires third image data for updating the first region (ROI) and corresponding positional information of the first region (ROI) in the display panel, and indicates the first region (ROI) to a display driver integrated circuit (DDIC) and transmits the third image data; and on the basis of the third image data, the DDIC only refreshes the first region (ROI) without refreshing other regions in the display panel. Neither the DPU nor the DDIC is able to process image data for updating regions other than the first region (ROI), and the DDIC also does not refresh regions in the display panel other than the first region (ROI), thereby improving touch responsiveness and reducing display power consumption. Implementing partial screen refresh in video mode without relying on random access memory offers greater universality and practicality than methods in command mode.

A CMO-based metallic filament (MF) resistive random access memory (MF-ReRAM) cell is provided in which the metallic filament is specifically designed to confine electric potential of the top electrode in a circular plug area of the MF. The CMO-based MF-ReRAM cell has non- volatile-multilevel storage capability in the back-end-of-the-line (BEOL), and such a memory cell can be integrated in a highly dense crossbar architecture.

Various aspects include a circuit having single-rail static operating global data lines for a synchronous random access memory (SRAM). The circuit can include one or more auto tri-state drivers coupled to the single-rail static operating global data lines of the SRAM. The circuit can include one or more sense amplifiers coupled to the one or more auto tri-state drivers. The circuit can include latches coupled to the single-rail static operating global data lines. Some embodiments can include a method for operating global data lines of a multi-array SRAM. The method can include connecting single-rail static operating global data lines of the SRAM to one or more auto tri-state drivers of the SRAM, and operating the one or more auto tri-state drivers without a strobe signal. The method can include operating the single-rail global data lines of the SRAM with a static signal.

The purpose is to enhance the enjoyment of the game. [Solution] In a gaming machine, the game control microprocessor comprises a CPU, a program executed by the CPU, a ROM storing information referenced by the program, a RAM capable of storing information updated by the program, a general-purpose register, a data register, and a flag register. The CPU writes first information to the RAM at the start of a variation performance indicating the result of a lottery. When the power to the gaming machine is cut off during the execution of the variation performance and then power is turned on to the gaming machine, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor. When the variation performance resumes after the machine has entered a waiting state for customers, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor.

Techniques herein use in-memory column vectors to process data that is external to a database management system (DBMS) and logically join the external data with data that is native to the DBMS. In an embodiment, a computer maintains a data dictionary for native data that is durably stored in an DBMS and external data that is not durably stored in the DBMS. From a client through a connection to the DBMS, the computer receives a query. The computer loads the external data into an in-memory column vector that resides in random access memory of the DBMS. Based on the query and the data dictionary, the DBMS executes a data join of the in-memory column vector with the native data. To the client through said connection, the computer returns results of the query based on the data join.

The system discloses a pixel including a memory and a single-photon avalanche diode (SPAD). The pixel is operable in a first mode and a second mode. The system further includes using high density static random-access memory (SRAM) based pixels for multi-bin histogramming for time-of-flight measurements and multi-frame storage intensity imaging.

A memory sub-system having: a host interface operable on a connection from the host interface to a host system outside of the memory sub-system; random access memory cells configured to provide a memory space accessible to the host system over the connection via a memory access protocol; non-volatile memory cells configured to provide a storage space accessible to the host system over the connection via a storage access protocol; and a controller configured to execute a storage access request, received from the host system over the connection according to the storage access protocol, to read data into the memory space from a logical block address in the storage space. The controller can also execute a storage access request, received over the connection according to the storage access protocol, to write data available in the memory space to a logical block address in the storage space.

This application relates to the field of terminal technology, and more particularly to a log storage method and an electronic device. The method enables the storage of the top N log blocks (those whose write times are closest to the time of the fault occurrence) from a plurality of log blocks stored in a circular buffer of a random access memory before the electronic device restarts due to a fault, in a non-volatile memory, where N is an integer greater than 1. The method includes: in response to a fault in the electronic device, obtaining a first offset for each of the plurality of log blocks stored in the circular buffer; determining a target log block from the plurality of log blocks based on the first offset; the first offset indicating the starting storage location of the log block when the plurality of log blocks are written to memory sequentially according to their write times.