877 results about "Random access memory" patented technology

A method for training or performing inference using a neural network involves performing per-layer decompression and compression of neural network weights. More particularly, compressed weights are retrieved for a particular layer of the neural network. The weights correspond to neurons in the layer. The compressed weights are decompressed, and input data for that layer is subsequently processed using the decompressed weights. This dynamic decompression and recompression of weights allows memory, and in particular random access memory of graphical processing units, to be efficiently used.

The invention provides a magnetic random access memory and a preparation method thereof. The magnetic random access memory is applied to a comparison circuit, and comprises a magnetic tunnel junction comprising a free layer, a barrier layer and a reference layer which are stacked in sequence; the spin-orbit torque layer is located on the side, away from the reference layer, of the free layer, the conductive material layer is located on the side, away from the spin-orbit torque layer, of the magnetic tunnel junction, and a conductive material of the conductive material layer has the following characteristics that spontaneous magnetization capacity is achieved, and the resistance temperature coefficient is smaller than 0; the conductive material layer comprises a first part and a second part which are arranged at an interval, the first part is in contact with the reference layer, a first input end of the comparison circuit is electrically connected with the first part, and a second input end of the comparison circuit is electrically connected with the second part. According to the invention, the technical problems that the reading window of the magnetic tunnel junction becomes small and even the reading is wrong and the magnetic random access memory needs to apply an auxiliary magnetic field along the current direction to realize the deterministic overturning of the magnetic moment are at least solved.

The invention discloses an SRAM (Static Random Access Memory) memory cell, a static random access memory and a preparation method thereof, and belongs to the field of semiconductors. Channel directions of two transmission gate transistors are set as a first direction, channel directions of two pull-up transistors are set as a second direction, and channel directions of two pull-down transistors are set as a third direction; the third direction and the first direction are crystal orientations of the same family, and the two pull-up transistors are arranged in a sinking manner; active regions of the pull-up transistor and other transistors are staggered so as to improve the heat dissipation capability; in order to manufacture the structure, a corresponding preparation method is designed, in the preparation process, the grid electrode of the pull-up transistor is stepped, so that the grid electrode of the pull-up transistor can be connected with the active region of the transmission grid transistor through a metal silicification technology, the contact resistance is greatly reduced, and the performance of the device is improved. Therefore, the performance of the whole device is improved, and the read-write speed is higher than that of the prior art under the same condition.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes a clock, one or more local controllers, programmable logic units implementing a systolic array to compute a matrix multiplication, and embedded memory blocks. The embedded memory blocks include a single port random access memory (SPRAM). The one or more local controllers are configured to, on a first set of alternating clock cycles of the clock, load matrix sub-elements from two rows of a matrix into corresponding matrix element of the SPRAM. The one or more local controllers are configured to, on a second set of alternating clock cycles of the clock, read out the matrix elements from the SPRAM to the systolic array to compute the matrix multiplication.

The invention relates to the technical field of computer encryption, and discloses a fully homomorphic encryption system based on a coprocessor architecture, which comprises a main processor, a coprocessor realized by an FPGA (Field Programmable Gate Array) and an upper computer, in the coprocessor, a data transmission and storage module is connected with a block random access memory through an on-chip bus to store data; the encryption module is used for encoding and encrypting the data; the KNN algorithm implementation module is used for performing distance calculation and sorting on ciphertext or plaintext data; the decryption module is used for decrypting and decoding the encrypted classification result based on a key issued by the upper computer; and the FPGA main processing module is used for controlling data input selection and comparing classification results. Through the control of the FPGA main processing module, the standardized data processing flow and the hardware collaborative architecture, the problem of difficulty in chip branch prediction is solved, and the stability and the safety of data processing are improved.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

The invention provides a firmware online upgrading method, embedded equipment, a medium and a product, and relates to the technical field of intelligent terminals. The method comprises the following steps: after the embedded equipment is powered on, running a primary bootstrap program, and checking a first mark state: if the state is a state of updating a secondary bootstrap program, executing online updating of the program and resetting a system; and if the state is the default state, loading and running the secondary bootstrap program. Checking a second mark state; if the second mark state is an updating mirror image state, executing firmware mirror image online updating and resetting; and if the state is the default state, determining a target mirror image, copying the target mirror image from the nonvolatile memory to the random access memory, and skipping to run. And the equipment simultaneously monitors the running state of the target mirror image in real time, and executes successful confirmation or abnormal recovery operation according to the state. In this way, quick response of faults is achieved through running state feedback, the stability and reliability of firmware upgrading of the embedded device are effectively improved, and the risk of device paralysis in the upgrading process is reduced.

The invention relates to the field of power system clean low-carbon evaluation, and discloses an RAM-based power system clean low-carbon evaluation method and system. The method comprises the following steps: collecting multi-source heterogeneous data in real time and carrying out exception cleaning and structured processing to construct a standardized data set; dynamically adjusting the weight based on an entropy weight method and expert experience, calculating an efficiency value by using an RAM model, and optimizing a constraint condition; recognizing input redundancy and output insufficiency by decomposing slack variables, and generating a high-value improvement list in combination with principal component analysis and analytic hierarchy process; and finally, matching the optimization strategy library to form a decision report and realizing closed-loop updating of the index library. The system can dynamically evaluate the clean low-carbon level of the electric power system, accurately identify energy efficiency improvement key points, realize evaluation-optimization-feedback full-process automatic management, and significantly improve the accuracy of an evaluation result and the effectiveness of decision support.

Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication and augment existing memory systems to allow them to be both high capacity and high bandwidth simultaneously. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and / or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.

Embodiments herein relate to scaling of Static Random Access Memory (SRAM) cells. An SRAM cell include nMOS transistors on one level above pMOS transistors on a lower level. Transistors on the two levels can have overlapping footprints to save space. Additionally, the SRAM cell can use pMOS access transistors in place of nMOS access transistors to allow reuse of areas of the cell which would otherwise be used by the nMOS access transistors. In one approach, gate interconnects are provided in these areas, which have an overlapping footprint with underlying pMOS access transistors to save space. The SRAM cells can be connected to bit lines and word lines in overhead and / or bottom metal layers. In another aspect, SRAM cells of a column are connected to bit lines in an overlying M0 metal layer and an underlying BM0 metal layers to reduce capacitance.

The embodiment of the invention provides cross-chip NVMe write channel data replication, and relates to the technical field of storage. The storage device provided by the embodiment of the invention comprises a master control component and a slave control component, the master control component comprises a DMA data replication unit, and the slave control component comprises a bus data replication unit; under the condition that the host command indicates that the data is transferred to the first NVM chip, the DMA data copying unit transfers the data of the host to the first static random access memory and the first dynamic random access memory; under the condition that the host command indicates that the data is moved to the second NVM chip, the DMA data replication unit generates a bus write transaction for accessing the special address space and transmits the bus write transaction to the bus data replication unit; the bus data replication unit generates two bus write transactions in response to the received bus write transaction accessing the special address space, and transfers the data of the host to the second static random access memory and the second dynamic random access memory through the two bus write transactions.

A collection of data is maintained by at least first and second nodes of a distributed database. The first node maintains a first subset of the collection of data in a first random-access memory, and the second node maintains a second subset of the collection of data in a second random access memory. The first node sends an HTTP-based request to obtain updates to the first subset of the collection of data. The request comprises a unique sortable identifier. The first node receives data from the second node, and updates the first subset of the collection of data based on the receive data.

The utility model discloses a dynamic signal acquisition circuit based on an FPGA kernel, and belongs to the technical field of signal acquisition. Comprising a field programmable gate array (FPGA) which is connected with a first synchronous dynamic random access memory (SDRAM), an ARM processor and a plurality of analog-to-digital converters (ADC). The input end of the analog-to-digital converter ADC is connected with the output end of the signal conditioning board; the input end of the signal conditioning board is connected with the dynamic acceleration sensor, the strain sensor and the displacement sensor and receives signals output by the sensors; the ARM processor is connected with a nonvolatile storage device FLASH and a second synchronous dynamic random access memory SDRAM; and the field programmable gate array FPGA is used for filtering and converting the acquired data and transmitting the data to the ARM processor. According to the utility model, synchronous acquisition, synchronous processing, synchronous analysis and synchronous transmission can be realized; the signal conditioning circuit adopts a modular design and can be compatible with sensors of various dynamic signals.

The invention discloses an aging test system and method for a high-speed dynamic random access memory, and the system comprises a test board which is used for bearing at least one to-be-tested memory chip; the controller is used for generating and outputting a test excitation signal conforming to a corresponding memory technical standard; the power management module is used for providing adjustable power supply voltage for the memory chip to be tested according to the control instruction; the communication interface is used for realizing data interaction between the controller and an upper computer and reading configuration information of the memory chip to be tested; wherein a test parameter template library associated with various memory technical standards and product specifications is preset in the controller, and corresponding test parameter templates are automatically matched and loaded according to chip configuration information read by the communication interface so as to adapt to memory chips with different standards. According to the invention, a single hardware platform can be used for universally and adaptively testing various high-speed dynamic random access memories, and the testing efficiency and the equipment utilization rate are remarkably improved.

A computer express link fabric having: a plurality of computer express link switches; a plurality of computer express link connections among the computer express link switches; and a controller. The controller is configured to: map memory addresses in a mapped memory space to physical addresses of random access memory cells of memory devices connected to the computer express link fabric; and implement, in a storage space of a memory sub-system connected to the computer express link fabric and having non-volatile memory cells, a persistent copy of data stored by memory access requests received in the computer express link fabric and having memory addresses in the mapped memory space.

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

A MRAM circuit is provided in the present invention, wherein each memory cell includes a first transistor with a first gate, a first source and a first drain and the first gate is connected to a first word line, a second transistor with a second gate, a second source and a second drain and a second gate is connected to a second word line, and the second source and the second drain are connected respectively with the first source and the first drain, a first MTJ with one terminal connected to the first source and the second source and another terminal connected to a source line, and a second MTJ with one terminal connected to the first drain and the second drain and another terminal connected to a bit line.

The invention discloses a magnetic electronic device for generating track torque by using a metal vanadium or titanium track Hall effect and a manufacturing method thereof. The device comprises a substrate, a track Hall structure containing a vanadium or titanium layer, and a heavy metal layer and a ferromagnetic layer which are adjacent to the track Hall structure, when a charge current passes through the vanadium or titanium layer, a transverse track current is generated based on the track Hall effect, and the track current is injected into the ferromagnetic layer and then converted into an effective track torque for controlling the magnetization state of the ferromagnetic layer. Preferably, the ferromagnetic layer has a perpendicular magnetic anisotropy. According to the invention, the light transition metal vanadium or titanium is used as the track Hall material, the experiment proves that a huge track Hall angle greater than 0.45 can be obtained, and meanwhile, the resistivity of the material is lower, so that the shunting phenomenon can be reduced in an actual device, and the critical current density for realizing write-in flipping can be obviously reduced. The device is simple in structure and compatible with an existing semiconductor process, and a brand new material platform is provided for developing a low-power-consumption and high-density magnetic random access memory (MRAM).

Embodiments of present invention provide a magnetoresistive random-access-memory (MRAM) device. The MRAM device includes a reference layer; a tunnel barrier layer next to the reference layer; and a free layer next to the tunnel barrier layer, where the free layer includes a crystalline AIMnGe layer in a C38 structure formed on a magnetic seed layer, and the magnetic seed layer is a crystallized MnCo2Si layer or a crystallized MnCo2Ge layer having a cubic Heusler structure with a (001) texture. A method of forming the MRAM device is also provided.

The invention provides a duty ratio detection device and a random access memory. The duty ratio detection device comprises a duty ratio detection module which is configured to receive a calibration clock signal in a calibration execution process and execute duty ratio detection on the calibration clock signal to obtain a duty ratio detection result; the adjustment control module is connected with the duty ratio detection module, the adjustment control module is configured to generate a corresponding target adjustment code based on a duty ratio detection result in the calibration execution process, and the duty ratio detection module adjusts a response threshold value based on the target adjustment code so as to eliminate the deviation between the response threshold value and a target response threshold value; and the duty ratio detection module performs duty ratio detection on the input clock signal based on the target response threshold value in the normal detection execution process. According to the scheme, the duty ratio detection module can respond when the duty ratio of the input clock signal is equal to the target response threshold value, that is, the response threshold value of the duty ratio detection module is adjusted to the target response threshold value, so that the detection deviation of the duty ratio detection device is reduced.

The invention discloses a double-patch updating method, device, equipment, medium and product of a starting read-only memory, and relates to the technical field of chip updating, the starting read-only memory is located in a server management chip, and the server management chip is provided with a one-time programmable memory isolated from the starting read-only memory. The method for burning the preset shadow patch code by the one-time programmable memory comprises the following steps of: starting the read-only memory, and detecting whether the read-only memory is successfully started within a preset time period; if the starting is not successful, triggering a shadow patch process, and executing a preset shadow patch code in the one-time programmable memory; if starting succeeds, triggering an online patch updating process based on the patch updating request, and loading a target segment patch code; and loading the target segment patch code subjected to segment security verification to a random access memory of the server management chip so as to redirect the access request to a new patch code address in the random access memory. And patch updating in the read-only memory starting process is realized.

Integrated cells may perform matrix multiplication (MatMul) operations. An integrated cell may include a random-access memory (RAM) cell, dot product unit(s), multiplexer(s), adder, route-in unit, control unit, and vector machine. The RAM cell may store weights and activations. The dot product unit(s) may compute dot products from the weights and activations. The adder may accumulate the dot products. The route-in unit may facilitate data transfer from the RAM cell to the dot product unit(s) or data transfer from another integrated cell to the integrated cell. The control unit may manage memory operations and detect and repair errors in memory operations. The vector machine may provide instructions to the dot product unit(s) and multiplexers to direct the flow of multiply-accumulate operations. Counters may be used to control weight fetching from RAM cells. A MatMul operation may be decomposed, and the integrated cells may perform the MatMul operation through multiple clock cycles.

The invention relates to an intelligent robot control system based on an ROS, and the system is characterized in that the system comprises a control module; the system comprises a control module, a driving module, a sensor module and a power management module, data transmission is carried out among the control module, the driving module, the sensor module and the power management module through a high-speed communication bus, and node communication and information interaction among the modules are realized based on an ROS framework. The control module comprises a microprocessor and a memory, the memory is used for storing ROS system files, control programs and data, the memory comprises a flash memory and a random access memory, and the random access memory is used for storing runtime data; the communication interface can be in communication connection with an upper computer, a mobile device and a network device, and publish and subscribe messages based on an ROS communication mechanism. The advantages of an ROS framework are fully utilized, and high real-time performance, high precision, high energy efficiency, high safety, good expandability and intelligent interaction experience of robot control are achieved.

Described herein are memory devices that include a cooling structure for cooling one or more memory arrays. The memory arrays may be static random access memory (SRAM) arrays formed in multiple layers as a stacked memory device. The cooling structure may cool one or more layers of an SRAM device. For example, a cooling structure may be formed around the SRAM device and coupled to a cooling device. Alternatively, a cooling layer may be included in a memory device and coupled to one or more thermal interface layers in thermal contact with a memory layer by cold vias. The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.

The invention provides a pre-crash log pre-freezing method of an embedded system and related equipment, and relates to the technical field of embedded systems.The method comprises the steps that running logs of the system are collected, after log content of a plurality of time slices is obtained, difference calculation and compression are conducted, and incremental compression slices are obtained; writing the incremental compression fragments into a first circular buffer area and a second circular buffer area which are circularly stored according to a preset condition; and when a crash early warning event is monitored, writing the latest incremental compression fragment in the first circular buffer area or the second circular buffer area into a pre-configured RAM (Random Access Memory) through a Zab protocol. Through combination of a double-buffering mechanism and a Zab protocol, complete storage of the running log can be completed before crash, reliability and integrity of log content are guaranteed, and through difference calculation and incremental compression, storage occupation and processing time are greatly reduced, and recovery speed and accuracy after system crash are improved.

The present application relates to a computer readable storage medium, a data reading method and device for a flash memory chip, the method is implemented when a processing unit loads and executes program code, comprising: issuing a read instruction to a flash interface, driving the flash interface to start a data reading operation for reading data from a location of the chip; calculating an output time point corresponding to the read instruction; and when the current time reaches or is later than the output time point, issuing a random output instruction corresponding to the read instruction to the flash interface, driving the flash interface to store the data to a random access memory. Thus, the present application determines the timing of issuing the random output instruction by the output time point as described above, which can avoid the NAND bus being occupied by unnecessary waiting for a read busy instruction and inquiring a NAND state instruction.

The present disclosure provides a semiconductor package structure and a semiconductor packaging method, and relates to the technical field of semiconductor. The semiconductor package structure comprises a package substrate, a random access memory chip bonded with a first connecting part on the package substrate, a package layer covering the random access memory chip on the package substrate, a redistribution layer on the package layer, a second conductive wire at least partially located in the package layer and connecting a second connecting part on the package substrate and a bottom surface of the redistribution layer, and a flash memory chip on the redistribution layer and bonded with a top surface of the redistribution layer. The redistribution layer comprises a signal line and a reference line, the signal line is used for signal transmission between the flash memory chip and the package substrate, and the reference line is used for providing a reference plane for signal transmission. The present disclosure can improve the warping, delamination and other problems of semiconductor devices, and improve signal integrity and power integrity.

The present disclosure provides an automatic driving controller data idle uploading method, system, medium and equipment, relates to the technical field of intelligent network connected vehicles, and comprises an automatic driving domain controller, a double rate synchronous random access memory, an embedded memory, a regional network management controller, a vehicle-mounted communication terminal and a vehicle domain controller. When the vehicle power supply mode is in an ON mode, the automatic driving domain controller writes and stores the backhaul data generated during the automatic driving function operation in the embedded memory through the double rate synchronous random access memory. When the vehicle is powered off, the regional network management controller sends a CAN message maintenance request, wakes up the vehicle-mounted communication terminal and the vehicle domain controller which need data uploading, and then uploads the temporarily stored data in the embedded memory.

A static random access memory (SRAM) and its formation method are disclosed, comprising a substrate; a plurality of SRAM cells on the substrate, each SRAM cell including a plurality of channel layers, a plurality of gate structures, and a plurality of source / drain doped layers; a first dielectric layer on the substrate; a first conductive structure electrically connected to a portion of the gate structures and a portion of the source / drain doped layers; and a shared conductive structure including a second conductive structure and a shared conductive layer on the second conductive structure, wherein the top surface of the shared conductive structure is lower than the top surface of the first conductive structure. Because the top surface of the shared conductive structure is lower than the top surface of the first conductive structure, a larger formation space is provided for the subsequently formed power conductive layer, thereby increasing the process window of the power conductive layer, reducing the contact resistance between the power conductive layer and the subsequently formed second pull-up conductive layer, and effectively improving the performance of the SRAM.