468 results about "Random access memory" patented technology

The invention provides a firmware online upgrading method, embedded equipment, a medium and a product, and relates to the technical field of intelligent terminals. The method comprises the following steps: after the embedded equipment is powered on, running a primary bootstrap program, and checking a first mark state: if the state is a state of updating a secondary bootstrap program, executing online updating of the program and resetting a system; and if the state is the default state, loading and running the secondary bootstrap program. Checking a second mark state; if the second mark state is an updating mirror image state, executing firmware mirror image online updating and resetting; and if the state is the default state, determining a target mirror image, copying the target mirror image from the nonvolatile memory to the random access memory, and skipping to run. And the equipment simultaneously monitors the running state of the target mirror image in real time, and executes successful confirmation or abnormal recovery operation according to the state. In this way, quick response of faults is achieved through running state feedback, the stability and reliability of firmware upgrading of the embedded device are effectively improved, and the risk of device paralysis in the upgrading process is reduced.

Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication and augment existing memory systems to allow them to be both high capacity and high bandwidth simultaneously. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and / or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.

The embodiment of the invention provides cross-chip NVMe write channel data replication, and relates to the technical field of storage. The storage device provided by the embodiment of the invention comprises a master control component and a slave control component, the master control component comprises a DMA data replication unit, and the slave control component comprises a bus data replication unit; under the condition that the host command indicates that the data is transferred to the first NVM chip, the DMA data copying unit transfers the data of the host to the first static random access memory and the first dynamic random access memory; under the condition that the host command indicates that the data is moved to the second NVM chip, the DMA data replication unit generates a bus write transaction for accessing the special address space and transmits the bus write transaction to the bus data replication unit; the bus data replication unit generates two bus write transactions in response to the received bus write transaction accessing the special address space, and transfers the data of the host to the second static random access memory and the second dynamic random access memory through the two bus write transactions.

The utility model discloses a dynamic signal acquisition circuit based on an FPGA kernel, and belongs to the technical field of signal acquisition. Comprising a field programmable gate array (FPGA) which is connected with a first synchronous dynamic random access memory (SDRAM), an ARM processor and a plurality of analog-to-digital converters (ADC). The input end of the analog-to-digital converter ADC is connected with the output end of the signal conditioning board; the input end of the signal conditioning board is connected with the dynamic acceleration sensor, the strain sensor and the displacement sensor and receives signals output by the sensors; the ARM processor is connected with a nonvolatile storage device FLASH and a second synchronous dynamic random access memory SDRAM; and the field programmable gate array FPGA is used for filtering and converting the acquired data and transmitting the data to the ARM processor. According to the utility model, synchronous acquisition, synchronous processing, synchronous analysis and synchronous transmission can be realized; the signal conditioning circuit adopts a modular design and can be compatible with sensors of various dynamic signals.

The invention discloses an aging test system and method for a high-speed dynamic random access memory, and the system comprises a test board which is used for bearing at least one to-be-tested memory chip; the controller is used for generating and outputting a test excitation signal conforming to a corresponding memory technical standard; the power management module is used for providing adjustable power supply voltage for the memory chip to be tested according to the control instruction; the communication interface is used for realizing data interaction between the controller and an upper computer and reading configuration information of the memory chip to be tested; wherein a test parameter template library associated with various memory technical standards and product specifications is preset in the controller, and corresponding test parameter templates are automatically matched and loaded according to chip configuration information read by the communication interface so as to adapt to memory chips with different standards. According to the invention, a single hardware platform can be used for universally and adaptively testing various high-speed dynamic random access memories, and the testing efficiency and the equipment utilization rate are remarkably improved.

A computer express link fabric having: a plurality of computer express link switches; a plurality of computer express link connections among the computer express link switches; and a controller. The controller is configured to: map memory addresses in a mapped memory space to physical addresses of random access memory cells of memory devices connected to the computer express link fabric; and implement, in a storage space of a memory sub-system connected to the computer express link fabric and having non-volatile memory cells, a persistent copy of data stored by memory access requests received in the computer express link fabric and having memory addresses in the mapped memory space.

Integrated cells may perform matrix multiplication (MatMul) operations. An integrated cell may include a random-access memory (RAM) cell, dot product unit(s), multiplexer(s), adder, route-in unit, control unit, and vector machine. The RAM cell may store weights and activations. The dot product unit(s) may compute dot products from the weights and activations. The adder may accumulate the dot products. The route-in unit may facilitate data transfer from the RAM cell to the dot product unit(s) or data transfer from another integrated cell to the integrated cell. The control unit may manage memory operations and detect and repair errors in memory operations. The vector machine may provide instructions to the dot product unit(s) and multiplexers to direct the flow of multiply-accumulate operations. Counters may be used to control weight fetching from RAM cells. A MatMul operation may be decomposed, and the integrated cells may perform the MatMul operation through multiple clock cycles.

Described herein are memory devices that include a cooling structure for cooling one or more memory arrays. The memory arrays may be static random access memory (SRAM) arrays formed in multiple layers as a stacked memory device. The cooling structure may cool one or more layers of an SRAM device. For example, a cooling structure may be formed around the SRAM device and coupled to a cooling device. Alternatively, a cooling layer may be included in a memory device and coupled to one or more thermal interface layers in thermal contact with a memory layer by cold vias. The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.

The invention provides a pre-crash log pre-freezing method of an embedded system and related equipment, and relates to the technical field of embedded systems.The method comprises the steps that running logs of the system are collected, after log content of a plurality of time slices is obtained, difference calculation and compression are conducted, and incremental compression slices are obtained; writing the incremental compression fragments into a first circular buffer area and a second circular buffer area which are circularly stored according to a preset condition; and when a crash early warning event is monitored, writing the latest incremental compression fragment in the first circular buffer area or the second circular buffer area into a pre-configured RAM (Random Access Memory) through a Zab protocol. Through combination of a double-buffering mechanism and a Zab protocol, complete storage of the running log can be completed before crash, reliability and integrity of log content are guaranteed, and through difference calculation and incremental compression, storage occupation and processing time are greatly reduced, and recovery speed and accuracy after system crash are improved.

The present disclosure provides a semiconductor package structure and a semiconductor packaging method, and relates to the technical field of semiconductor. The semiconductor package structure comprises a package substrate, a random access memory chip bonded with a first connecting part on the package substrate, a package layer covering the random access memory chip on the package substrate, a redistribution layer on the package layer, a second conductive wire at least partially located in the package layer and connecting a second connecting part on the package substrate and a bottom surface of the redistribution layer, and a flash memory chip on the redistribution layer and bonded with a top surface of the redistribution layer. The redistribution layer comprises a signal line and a reference line, the signal line is used for signal transmission between the flash memory chip and the package substrate, and the reference line is used for providing a reference plane for signal transmission. The present disclosure can improve the warping, delamination and other problems of semiconductor devices, and improve signal integrity and power integrity.

A photonic random access memory employs series connected photosensors to define switching nodes driving optical modulators, the series connection operating to reduce the effect of photosensor dark current.

Methods of forming DRAM bit lines to improve line edge roughness (LER) and reduce resistance are described. The methods include the steps of implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size, the second grain size being smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and the amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.

Disclosed in the embodiments of the present application are a root file system loading method and a related apparatus. In the method, a part of a virtual memory is simulated as a random access memory disk (RAMDISK) mechanism used by a block device. First, a read-only memory file system (ROMFS) mirror image file on an initial physical address is acquired; and then, a virtual address corresponding to the initial physical address of the ROMFS mirror image file is directly used as the starting address of the block device, such that the copy operation of copying the ROMFS mirror image file to the block device is executed on the initial physical address, thereby formatting the block device. Then, a kernel can be booted by means of mounting the ROMFS mirror image file in the block device as a root file system. By using the ROMFS image file as a root file system and reducing copy operations during a boot process, the kernel boot time is shortened in read‑only application scenarios requiring fast boot, thereby achieving fast kernel boot.

The application provides a static random access memory structure and a preparation method thereof. The static random access memory structure comprises a substrate, an isolation structure, at least two static random access memory cells sharing a word line, and a plurality of active regions defined by the isolation structure on the substrate. Each static random access memory cell comprises at least two inverter groups and at least two transfer transistor groups. Each inverter group comprises two inverters cross-coupled, each inverter being formed by a pull-up transistor and a pull-down transistor stacked in the same active region along the vertical direction of the substrate. The plurality of active regions comprises at least two common regions shared by different static random access memory cells. Each transfer transistor group is formed by two transfer transistors stacked in the same common region along the vertical direction of the substrate, and the two transfer transistors in the same common region belong to different static random access memory cells. Thus, the coupled two static random access memory cells save 50% of the area.

By having a non-secure CPU handle MACsec key management, this semiconductor device provides a solution that compensates for the performance shortcomings of a secure CPU. [Solution] The semiconductor device comprises a RAM storing an encryption key, a secure CPU capable of accessing the encryption key stored in the RAM, and a first non-secure CPU connected to the RAM via a key access protection module and having a first user ID. The key access protection module stores user ID information of the non-secure CPU that is permitted to access the encryption key stored in the RAM, linked to the encryption key. When the first non-secure CPU attempts to access the encryption key stored in the RAM, the key access protection module grants the first non-secure CPU access to the encryption key if the stored user ID information matches the first user ID.

Embodiments herein relate to Static Random-Access Memory (SRAM) where a write assist technique is facilitated using power supply lines (Vcc) which extend in a word line direction. The SRAM can be implemented using complementary field-effect transistor (CFET) technology, where n-type and p-type transistors are arranged in a stacked configuration on top and bottom levels, respectively of a stack. In one aspect, a power supply line is shared by a row of adjacent memory cells. In another aspect, a power supply line is shared by a row of memory cells in alternate columns. The configurations avoid disturb of unselected cells due to a Vcc collapse during writing. In another aspect, an eight-transistor SRAM memory cell includes transistor gates to reduce Vmin, the minimum supply voltage at which a memory array can operate without failure.

A system to generate true random numbers includes a RAM array, a null-read controller and a hash generator. The RAM array has memory cells and a sense amplifier. The memory cells store data therein, the cells are connected in rows to word lines and in columns to pairs of bit lines, and the sense amplifier senses a differential input signal. The null-read controller implements a null-read operation by the sense amplifier of a portion of the RAM array. The hash generator receives a null-read result from the null-read operation and outputs a partial true random number based on the null-read result.

The invention provides a memory device and a data storage method thereof. The data storage method includes: generating, by a data controller, a first user data feature of user data stored in a random access memory; sending, by the data controller, the first user data characteristic of the user data to an IMS memory device; comparing the first user data feature with a plurality of second user data features in a plurality of feature values stored in the IMS memory device to generate a comparison result, the feature values including the second user data features and a plurality of entity block addresses corresponding to data stored in the storage device; sending, by the IMS memory device, the comparison result to the data controller; and determining, by the data controller, whether to write the user data into the storage device based on the comparison result.

The invention provides a self-adaptive dynamic random access memory based on double-Bank heterogeneity, a control method, a medium, a terminal and a program product, the self-adaptive dynamic random access memory based on double-Bank heterogeneity comprises a plurality of first Bank groups, each first Bank group comprises a plurality of low-delay Banks, and the low-delay Banks are used for accessing small data block data; a plurality of second Bank groups, each second Bank group comprises a plurality of high-capacity Banks, and the high-capacity Banks are used for accessing big data block data; the line number of the storage array of the high-capacity Bank is greater than that of the storage array of the low-delay Bank; the time sequence parameter switching module is used for switching time sequence parameters of the low-delay Banks according to the real-time working temperature of each low-delay Bank; the time sequence parameters comprise an optimized time sequence parameter corresponding to a typical working temperature interval and a standard time sequence parameter corresponding to a high temperature interval; and the memory control module is used for controlling the small data block to access the low-delay Bank or the big data block to access the high-capacity Bank based on the size of the data block. According to the invention, delay and high capacity can be decoupled, the time sequence is saved, and the load adaptability is enhanced.

The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode including a metal nitride; a second electrode comprising a first conductive material; and a switching oxide layer positioned between the first electrode and the second electrode. The switching oxide layer includes at least one transition metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and / or tantalum nitride. The first electrode does not include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc.

Among other things, we describe a method of receiving a portion of metadata from a data source, the portion of metadata describing nodes and edges; generating instances of a data structure representing the portion of metadata, at least one instance of the data structure including an identification value that identifies a corresponding node, one or more property values representing respective properties of the corresponding node, and one or more pointers to respective identification values, each pointer representing an edge associated with a node identified by the corresponding respective identification value; storing the instances of the data structure in random access memory; receiving a query that includes an identification of at least one particular element of data; and using at least one instance of the data structure to cause a display of a computer system to display a representation of lineage of the particular element of data.

The application provides a pipeline structure-based computing engine acceleration device, method, equipment and medium in the technical field of neural network hardware acceleration, the device comprises: a circular row buffer, comprising: a first multiplexer, used for determining the storage position of n feature map pixels of an input feature map, wherein n is a positive integer greater than 0; m random access memories, used for caching n feature map pixels according to the storage position, wherein m is a positive integer greater than 0; a second multiplexer, used for outputting the feature map pixels written into the m random access memories; a stream driving filler, used for performing boundary filling on the feature map pixels output by the second multiplexer according to the position of the feature map pixels and the boundary parameter of the convolution layer in the neural network; a computing unit array, used for performing convolution calculation on the filled feature map pixels; and a weight memory, used for caching the weight data of the neural network.

Aspects of the present disclosure provide a method of fabricating a resistive random access memory (RRAM). For example, the method can include providing a substrate, forming a first electrode on the substrate, and forming a first metal oxide layer on the first electrode. The first metal oxide layer can act as a sink or reservoir of oxygen atoms that interact with a current conducting filament. The method can further include forming a second metal oxide layer on the first metal oxide layer. The second metal oxide layer can be configured to form conduction paths. The method can further include forming a second electrode on the second metal oxide layer. In an embodiment, the first metal oxide layer can be formed on a portion of the first electrode.

The real-time video acquisition and processing board card of the PXIe specification comprises a connector assembly, a CameraLink Base receiver, a CameraLink Medium receiver, a CameraLink Full receiver, a TTL IO chip, a differential IO chip, an FPGA nonvolatile flash memory, a field programmable logic device, an FPGA high-speed dynamic random access memory, a DSP nonvolatile flash memory, a digital signal processor, a DSP high-speed dynamic random access memory, a PCIe bus interface and a power management module.

This invention provides a method for implementing complementary logic based on magnetic random access memory (MRM). The method includes: applying an initial voltage and an initial current to the control terminal of a first MLM and a common control terminal of a second MLM, causing the first and second units to be in a logically complementary initial magnetization state; applying a logic input voltage to the common control terminal and a logic input current to the first and second units, causing the first and second units to obtain corresponding first magnetization states based on their respective initial magnetization states, enabling the first unit to perform an AND logic operation; applying a logic inverse signal of the initial voltage to the control terminal of the first unit, applying a logic inverse signal of the logic input voltage to the common control terminal, and applying a logic inverse signal of the logic input current to the second unit, causing the second unit to obtain a second magnetization state based on its corresponding first magnetization state, enabling it to perform an XOR logic operation. This achieves integrated storage and computation.

The invention provides a static random access memory unit, a preparation method thereof and electronic equipment. The static random access memory unit comprises a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor; a first transfer transistor and a second transfer transistor; a first power rail and a second power rail disposed on a back surface of the SRAM cell; in the vertical direction, the position of the first power supply rail corresponds to the first pull-up transistor and the second pull-up transistor, and the first power supply rail is electrically connected with the first pull-up transistor and the second pull-up transistor through back source drain contact metal; the position of the second power rail corresponds to the first pull-down transistor and the second pull-down transistor, and the second power rail is electrically connected with the first pull-down transistor and the second pull-down transistor through the back source drain contact metal. According to the invention, the unit height of the SRAM unit is reduced, and high-density integration of the SRAM unit is realized.

The application relates to the technical field of computers, in particular to a chip serial port loading retransmission system and method. The system comprises a chip and a serial port tool; the chip comprises a processor, a static random access memory, a serial port module and a watchdog module; the processor is used for executing the configuration of the serial port module, the issuing of instructions and the analysis of a starting program; the static random access memory is used for storing stack data in the process of executing the program by the processor and storing starting program data transmitted from the serial port module; the serial port module is used for receiving instructions from the processor and receiving starting program data transmitted from outside the chip; the serial port module is used for sending a serial port retransmission flag according to the starting state of the chip; the watchdog module is used for counting down, and when the watchdog is not disabled after a certain time, the watchdog triggers a system soft reset restart; the serial port tool comprises a plurality of program files.

A system and method for providing a neural network model to an artificial intelligence (AI) field programmable gate array (FPGA) are provided. A flash memory stores a neural network model. A tunnel is created between a flash memory and a random access memory (RAM) over a multi-line serial peripheral interface (QSPI) interface. Using the tunnel, the RAM reads one or more layers of the neural network model from the flash memory and writes the one or more layers into pages in the RAM. The AI FPGA reads the one or more layers of the neural network model from the RAM over a wide input / output interface and executes the one or more layers.

A transaction method includes initializing a first read counter according to a first predefined read count by a microcontroller unit (MCU), writing data to a cache by a first processing element, reading the data from the cache by a second processing element, transmitting a first read done message from the second processing element to the MCU after the data of the cache is read by the second processing element, decrementing the first read counter according to the first read done message by the MCU, and transmitting a first frame-discard cache maintenance operations (CMO) command from the MCU to the cache when the first read counter is decremented to zero.

Systems, devices, and methods related to a deep learning accelerator and memory are described. For example, a wearable electronic device may be configured to execute instructions with matrix operands and configured with: a housing to be worn on a person; a sensor having one or more sensor elements generate measurements associated with the person; random access memory to store instructions executable by the deep learning accelerator and store matrices of an artificial neural network; a transceiver; and a controller to monitor an output of the artificial neural network, generated using the measurements as an input to the artificial neural network. Based on the output, the controller may control selective storage of measurement data from the sensor, and / or selective communication of data from the wearable electronic device to a separate computer system.