1405 results about "Random access memory" patented technology

The invention relates to a ZNS SSD-based B + tree index construction method for dynamic placement of cold and hot data. A persistent memory PM, a dynamic random access memory DRAM and a ZNS SSD hard disk are included. The persistent memory PM and the dynamic random access memory DRAM are directly connected with a CPU memory bus and have the capability of being accessed by the CPU according to bytes; internal nodes of the B + tree are stored in a dynamic random access memory (DRAM), and the internal nodes only store index information used for positioning leaf nodes; the pseudo leaf nodes of the B + tree are stored in a persistent memory PM, and only the key index information of the leaf nodes is stored in the pseudo leaf nodes; leaf nodes really storing the key value pairs in the B + tree are divided into hot leaf nodes and cold leaf nodes according to the data access frequency, the hot leaf nodes are stored in a persistent memory PM, and the cold leaf nodes are stored in a ZNS SSD. According to the method, the leaf nodes are quickly positioned by using the DRAM, so that the query time is shortened; hot leaf nodes are stored in the PM, and the real-time service read-write requirement is met; and hot data is stored in a high-speed DRAM and PM, so that the random read-write delay is reduced, and the performance is excellent in scenes such as big data analysis and the like.

A method for training or performing inference using a neural network involves performing per-layer decompression and compression of neural network weights. More particularly, compressed weights are retrieved for a particular layer of the neural network. The weights correspond to neurons in the layer. The compressed weights are decompressed, and input data for that layer is subsequently processed using the decompressed weights. This dynamic decompression and recompression of weights allows memory, and in particular random access memory of graphical processing units, to be efficiently used.

The invention discloses a lattice-based cryptographic algorithm-oriented side channel attack-resistant NTT circuit, which comprises a control unit, which is mainly used for controlling the enabling of a bottom layer component in the structure and the data flow direction among modules; the storage unit is used for storing the coefficient, the random twiddle factor address and the twiddle factor; the address generation unit is used for calculating and generating a storage RAM (Random Access Memory) address of a twiddle factor participating in operation and a read address required by the coefficient storage unit; and the coefficient transposing unit is used for realizing coefficient reading meeting the index distance among all NTT stages. According to the side channel attack resisting NTT circuit oriented to the lattice-based cryptographic algorithm, when a low delay base-4CT / GS butterfly unit is masked, the increment of modular multiplication resources is reduced, and the resource consumption is remarkably reduced while high security is kept.

An integrated circuit includes a host interface coupled to a host device executing a tenant operating system (OS) on bare metal and hardware accelerator(s) coupled to the host interface and a network interface. The hardware accelerator(s) receive, over the host interface, a snapshot request relating to a snapshot of tenant OS. Snapshot request includes a location, in a physical memory of the host device, of a swap file having contents of random access memory of the host device. The hardware accelerator(s) encrypt the swap file and initiate transfer of the encrypted swap file to a network storage device coupled to a cloud-based server. The hardware accelerator(s) send, over the network interface, to a snapshot manager hosted by the cloud-based server, metadata associated with storing the encrypted swap file in the cloud-based server, to allow the snapshot manager to manage the snapshot of the tenant OS.

The invention relates to the technical field of system-on-chip service interrupt processing, in particular to a hardware Sequence-based SoC interrupt processing method, which comprises the following steps of: pre-programming an interrupt processing instruction sequence into an instruction random access memory (RAM), and configuring an instruction set, a sequence processor and an interrupt priority strategy of a task scheduler Sequence; receiving the interrupt signal by a task scheduler, and selecting a corresponding sequence processor according to an interrupt type; for the interrupt with low priority, the Sequencer directly executes the pre-stored instruction sequence to complete the interrupt response; and for high-priority interruption, the Sequencer caches the state of the register and sends a message packet to notify the CPU to perform cooperative processing. According to the method, interrupt autonomous response is achieved through hardware Sequence, zero CPU intervention is achieved in low-priority interrupt, a lightweight message mechanism is adopted in high-priority interrupt, and bandwidth occupation and power consumption are reduced while efficiency is improved.

A system in package platform includes a processor chip having a runtime processor core, an accelerator core and a processor-memory interface exposed on a chip-to-chip bonding surface, a first memory chip such as 3D NAND flash memory storing a collection of executable models of inference engines, and a second memory chip storing weights of a selected executable model. The second memory chip can comprise a nonvolatile, random access memory, such as phase change memory. Direct vertical connections such as via-to-via connections, are provided between the processor chip and the second memory chip.

A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.

In a matrix of SOT-MRAM cells, a first row is selected for writing and a second row is selected for reading. A first SOT-MRAM cell of the first row and a second SOT-MRAM of the second row are in a first column, while a third SOT-MRAM cell of the first row and a fourth SOT-MRAM of the second row are in a second column. The currents for writing the first SOT-MRAM cell and the third SOT-MRAM cell are in opposite direction. A first sense amplifier is configured to detect a voltage change on the first read bit line which is charged with a first read current in the second SOT-MRAM cell. A second sense amplifier is configured to detect a voltage change on the second read bit line which is discharged with a second read current in a fourth SOT-MRAM cell.

The invention discloses a heterogeneous Chiplet hybrid precision Transformer acceleration system based on an MRAM-SRAM (Magnetic Random Access Memory-Static Random Access Memory), which adopts a Chiplet block integration technology, gives full play to the modularization advantages of high yield and low cost of the Chiplet block integration technology, and internally integrates two types of heterogeneous calculation cores of MRAM calculation Chiplet and SRAM-NPU calculation Chiplet and two types of scheduling management Chiplet and data interaction Chiplet control units. In a Transform calculation process, an MRAM (Magnetic Random Access Memory) calculates a Chiplet to carry out approximate token relationship prediction in a self-attention mechanism, an SRAM-NPU (Synchronous Random Access Memory-Network Processing Unit) calculates the Chiplet to realize accurate attention calculation by utilizing a high-speed read-write characteristic of an SRAM (Static Random Access Memory) and a flexible calculation capability of the NPU, meanwhile, a scheduling management Chiplet coordinates calculation task allocation, and a data interaction Chiplet ensures efficient data flow; according to the acceleration system, optimal combination of different process node devices is realized through a Chiplet heterogeneous integration technology, and three dimensions of calculation efficiency, energy consumption and precision are balanced by combining the high-density low-power-consumption storage and calculation integrated advantage of an MRAM and high-precision calculation of an SRAM-NPU.

A first command including data to be stored in non-volatile random access memory (NVRAM) of a storage device is received from a storage system controller by a storage device controller. In response to receiving the first command, the data is stored in the NVRAM. One or more second commands including a location in flash memory of the storage device for storing the data and an instruction to store the data in the location of the flash memory are received from the storage system controller. In response to receiving the one or more second commands, the data is stored in the location of the flash memory.

Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. The random access memory is configured to store input data from a sensor, parameters of a first portion of an Artificial Neural Network (ANN), instructions executable by the Deep Learning Accelerator to perform matrix computation of the first portion of the ANN, and data generated outside of the device according to a second portion of the ANN. The Deep Learning Accelerator may execute the instructions to generate, independent of the data from the second portion of the ANN, a first output based on the input data from the sensor and generate a second output based on a combination of the data from the sensor and the data from the second portion of the ANN.

A semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.

Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth long distance communication, e.g. photonic or electronic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; one or more computational devices configured for simultaneously launching a plurality of data signals including memory read and / or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the one or more computational devices for transferring the data therebetween.

A clock domain crossing (CDC) circuit receives a first data. The CDC circuit includes a first buffer and a second buffer. The first buffer includes a single-clock static random-access memory. The second buffer includes a plurality of data flip-flops. Logic coupled to the first buffer and the second buffer can determine that first buffer is not full at a first time. Responsive to the determination that the second buffer is not full at the first time, the processing logic can bypass the first buffer to write the first data to the second buffer according to the first clock domain. The processing logic can provide the first data as output from the second buffer according to the second clock domain.

A magnetic tunnel junction (MTJ) stack, a vertical side surface of the MTJ stack includes a saw tooth edge, the MTJ stack includes vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, the free layer of the MTJ stack has a tapered edge including a first width at an upper portion of the free layer and a second width at a lower portion of the free layer, the first width is greater than the second width. Forming a first bottom electrode of a first MTJ stack, a second bottom electrode of a second MTJ stack, a first inter-layer dielectric between the first and the second bottom electrode, a first reference layer of the first MTJ stack, a second reference layer of the second MTJ stack, a second inter-layer dielectric between the first reference layer and the second reference layer.

The invention provides a magnetic random access memory and a preparation method thereof. The magnetic random access memory is applied to a comparison circuit, and comprises a magnetic tunnel junction comprising a free layer, a barrier layer and a reference layer which are stacked in sequence; the spin-orbit torque layer is located on the side, away from the reference layer, of the free layer, the conductive material layer is located on the side, away from the spin-orbit torque layer, of the magnetic tunnel junction, and a conductive material of the conductive material layer has the following characteristics that spontaneous magnetization capacity is achieved, and the resistance temperature coefficient is smaller than 0; the conductive material layer comprises a first part and a second part which are arranged at an interval, the first part is in contact with the reference layer, a first input end of the comparison circuit is electrically connected with the first part, and a second input end of the comparison circuit is electrically connected with the second part. According to the invention, the technical problems that the reading window of the magnetic tunnel junction becomes small and even the reading is wrong and the magnetic random access memory needs to apply an auxiliary magnetic field along the current direction to realize the deterministic overturning of the magnetic moment are at least solved.

The invention discloses an SRAM (Static Random Access Memory) memory cell, a static random access memory and a preparation method thereof, and belongs to the field of semiconductors. Channel directions of two transmission gate transistors are set as a first direction, channel directions of two pull-up transistors are set as a second direction, and channel directions of two pull-down transistors are set as a third direction; the third direction and the first direction are crystal orientations of the same family, and the two pull-up transistors are arranged in a sinking manner; active regions of the pull-up transistor and other transistors are staggered so as to improve the heat dissipation capability; in order to manufacture the structure, a corresponding preparation method is designed, in the preparation process, the grid electrode of the pull-up transistor is stepped, so that the grid electrode of the pull-up transistor can be connected with the active region of the transmission grid transistor through a metal silicification technology, the contact resistance is greatly reduced, and the performance of the device is improved. Therefore, the performance of the whole device is improved, and the read-write speed is higher than that of the prior art under the same condition.

The invention discloses a line speed bit mask message matching method based on an FPGA (Field Programmable Gate Array), the FPGA comprises at least one block RAM (Random Access Memory), the block RAM comprises a plurality of storage addresses, and the method comprises the following steps: acquiring N matching rules, each matching rule comprising a rule number, a keyword and a mask; and executing configuration of the matching rules in the block RAM according to the N matching rules: for each matching rule, determining at least one storage address corresponding to the matching rule according to an effective bit of a mask in the matching rule and a corresponding keyword, and determining a bit to be configured in N bits of the storage address according to a rule number of the matching rule, writing an effective bit value in the bit; and taking quintuple information in the received message as a storage address of the block RAM, reading a plurality of effective bit values corresponding to the storage address, and determining a rule number of each matching rule hit by the message based on each effective bit value. According to the invention, bit mask rule matching of the message can be realized at a line speed.

Various embodiments of information handling systems (IHS) and related methods are provided to prevent tampering and verify the integrity of non-volatile data stored within non-volatile memory, such as but not limited to non-volatile random access memory (NVRAM). More specifically, information handling systems and methods are provided herein to: (a) prevent tampering of non-volatile data stored within non-volatile memory by preventing unauthorized write operations to the non-volatile memory, and either (b) verify the integrity of the non-volatile data read from the non-volatile memory, or (c) detect tampering, if the integrity of the non-volatile data cannot be verified.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes a clock, one or more local controllers, programmable logic units implementing a systolic array to compute a matrix multiplication, and embedded memory blocks. The embedded memory blocks include a single port random access memory (SPRAM). The one or more local controllers are configured to, on a first set of alternating clock cycles of the clock, load matrix sub-elements from two rows of a matrix into corresponding matrix element of the SPRAM. The one or more local controllers are configured to, on a second set of alternating clock cycles of the clock, read out the matrix elements from the SPRAM to the systolic array to compute the matrix multiplication.

The invention relates to the technical field of computer encryption, and discloses a fully homomorphic encryption system based on a coprocessor architecture, which comprises a main processor, a coprocessor realized by an FPGA (Field Programmable Gate Array) and an upper computer, in the coprocessor, a data transmission and storage module is connected with a block random access memory through an on-chip bus to store data; the encryption module is used for encoding and encrypting the data; the KNN algorithm implementation module is used for performing distance calculation and sorting on ciphertext or plaintext data; the decryption module is used for decrypting and decoding the encrypted classification result based on a key issued by the upper computer; and the FPGA main processing module is used for controlling data input selection and comparing classification results. Through the control of the FPGA main processing module, the standardized data processing flow and the hardware collaborative architecture, the problem of difficulty in chip branch prediction is solved, and the stability and the safety of data processing are improved.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

The invention provides a firmware online upgrading method, embedded equipment, a medium and a product, and relates to the technical field of intelligent terminals. The method comprises the following steps: after the embedded equipment is powered on, running a primary bootstrap program, and checking a first mark state: if the state is a state of updating a secondary bootstrap program, executing online updating of the program and resetting a system; and if the state is the default state, loading and running the secondary bootstrap program. Checking a second mark state; if the second mark state is an updating mirror image state, executing firmware mirror image online updating and resetting; and if the state is the default state, determining a target mirror image, copying the target mirror image from the nonvolatile memory to the random access memory, and skipping to run. And the equipment simultaneously monitors the running state of the target mirror image in real time, and executes successful confirmation or abnormal recovery operation according to the state. In this way, quick response of faults is achieved through running state feedback, the stability and reliability of firmware upgrading of the embedded device are effectively improved, and the risk of device paralysis in the upgrading process is reduced.

A DRAM is provided including a block with a 3D array of memory cells. The block includes a set of planes stacked along a first axis, including a subset of stacked planes. Each plane of the subset includes a 2D array of memory cells organized in rows and columns. The block has multiple sub-blocks arranged along the second axis with each sub-block containing one column of memory cells of each plane. The DRAM has a plurality of bit lines extending along the first axis in one of the sub-blocks and connected to one memory cell in each plane and includes a plurality of global bit lines connected to the bit lines in each sub-block. Bit line selector transistors of the DRAM connect bit lines to global bit lines and bit line pre-charge transistors of the DRAM connect bit lines to charging lines to charge the bit line.

The invention introduces a method for read retry, performed by a processing unit, includes: providing a first set of re-read voltages in an iteration of a read retry mechanism; obtaining a second set of re-read voltages with a maximum distance from the first set of re-read voltages; driving a flash interface (I / F) to use the second set of re-read voltages to read a designated page and obtain second data from a flash module; and in response that the second data is correct, or the second data is successfully corrected by an error correction unit, exiting the read retry mechanism and replying with the second data or corrected second data to a host side or storing the second data or the corrected second data at a designated address of a random access memory (RAM).

In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.

The invention provides a ferroelectric storage array and a preparation method thereof, a memory and electronic equipment, relates to the technical field of semiconductors, and aims to enlarge a read-write data window of the memory and reduce power consumption of the memory. The ferroelectric storage array comprises a plurality of storage units, each storage unit comprises a ferroelectric capacitor and a transistor, the ferroelectric capacitor comprises a first electrode and a second electrode which are oppositely arranged, and a ferroelectric layer and an insertion layer which are located between the first electrode and the second electrode. An insertion layer can be arranged between the ferroelectric layer and the first electrode, or between the ferroelectric layer and the second electrode, or between the ferroelectric layer and the first electrode and between the ferroelectric layer and the second electrode. The intercalation layer comprises electric dipoles, and the electric dipoles are distributed on the two opposite surfaces of the intercalation layer in the direction from the first electrode to the second electrode. The ferroelectric memory array can be applied to a ferroelectric random access memory to realize reading and writing of data.

A resistive random access memory is provided including an asymmetrical or symmetrical bottom electrode which has an angled profile which forms an interface with a memory switching layer. The angled profile can include a slanted surface or one including a plurality of slanted surfaces that converge into a point. Bottom electrodes having such angled profiles provide more forming area, which can reduce forming voltage without area penalty. In some embodiments in which the slanted surfaces converge into a point, bottom electrodes having such an angled profile can also provide a more controlled area for the forming process to occur.

A semiconductor device includes a first dielectric layer, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, an ferroelectric random-access memory (FeRAM) cell in the second dielectric layer, a third dielectric layer over the second dielectric layer, and a second conductive feature in the third dielectric layer, the second conductive feature being electrically coupled to the top electrode. The FeRAM cell includes a bottom electrode contacting the first conductive feature, a ferroelectric material layer completely covering an upper surface of the bottom electrode, and a top electrode on the ferroelectric material layer.

The embodiment of the invention provides a photoelectric Transform accelerator cooperation method and device, and aims to efficiently process Transform model calculation. Firstly, according to the size M of an optical chip static random access memory on an optical computing chip and feature dimensions d of a query matrix Q, a key matrix K and a value matrix V, Q is divided into Tr sub-blocks, and K and V are respectively divided into Tc sub-blocks. Then, the universal computing chip and the optical computing chip are in interactive communication, the jth sub-block of K and V is transmitted to the optical computing chip firstly, and then the ith sub-block of Q is transmitted circularly for the sub-block. The optical computing chip computes a local attention score matrix Sij and then transmits the matrix back, the general computing chip carries out nonlinear processing on the matrix to obtain a local attention weight matrix Pij, the maximum value mij of each row of the Sij and the sum lij of each row of the Pij are computed, and m, l and O are updated until all sub-blocks K and V are processed. According to the method, through photoelectric collaboration and block calculation, resource utilization is optimized, and calculation efficiency is improved.