461results about "Electric analogue stores" patented technology

In an implementation, a device includes: a first inverter; a first sense amplifier connected to the first inverter; a first match line connected to the first sense amplifier; a first analog content addressable memory cell including: a first pull-down transistor; a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first match line and a reference node; a first memory circuit configured to store a first upper bound of a first range and to activate the first pull-down transistor when an analog input value is less than the first upper bound of the first range; and a second memory circuit configured to store a first lower bound of the first range and to activate the second pull-down transistor when the analog input value is greater than the first lower bound of the first range.

The invention relates to a circuit with a CMOS inverter and a variable resistor (R). fb ), where the variable resistance (R fb ) the entrance (V in ) of the CMOS inverter with the output (V out ) electrically connects the CMOS inverter. The invention also relates to a camera with such a circuit. This makes it possible to realize a circuit that can function both like an analog camera and like a digital camera.

A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

According to one embodiment, a semiconductor integrated circuit includes: a first buffer including an input end to which a first signal is configured to be supplied; a first switching element including a first end coupled to an output end of the first buffer and a second end coupled to a first node; a first capacitor including a first end coupled to the first node and a grounded second end; a second switching element including a first end coupled to the first node and a second end coupled to a second node; a second buffer including an input end coupled to the second node; and a first converter configured to determine a first bit string from a first output from the second buffer. The first and second switching elements being configured to switch between states based on a first clock signal.

There is provided an trapped ion processor comprising a DAC chamber, an ASIC, a digital control line between the DAC chamber and the ASIC and an analogue control line between the DAC chamber and the ASIC. The ASIC comprises a plurality of channels, each channel comprising a DC electrode, a first analogue memory cell and a second analogue memory cell. The DAC chamber comprises a DAC configured to generate an analogue signal and a DAC controller configured to generate timing control signals, the timing control signals comprising one or more sample timing signals to control when the analogue signal is sampled, as a voltage signal, by one or more of the plurality of the channels, and one or more synchronisation signals to control when the sampled voltage signal is applied to the respective DC electrode. The analogue control line transmits the analogue signal from the DAC to the plurality of channels and wherein the digital control line transmits the timing control signals from the DAC controller to the plurality of channels, the timing control signals controlling when the analogue signal is sampled, as a voltage, by either the first or the second analogue memory cell of each of a plurality of channels and controlling when the sampled voltage signal is applied to the respective DC electrode of each of a plurality of channels.

The basis of calculating memory capacity of modern computing is bit. Thus, the number of bits is the unit of information quantity of modern communication. The number of neurons (node number) in the neural networks in human brain is not the unit of the memory capacity of the human being. The complexity of neural network is much greater than the bit capacity. Hence, the current AI, which tries to imitate the human brain using computing with the basis on bits, performs inherently different processing of information from the human brain. In addition, computing based on bit number is always facing the limitation of integration. The present disclosure provides a system of information memory without relying on bits using three-dimensional neural networks. By replacing the electrical connection of non-volatile memory cells, which are distributed in a three-dimensional array, the mechanism of the information processing of the human brain can be imitated.

A method is disclosed for programming analog-valued weights in a non-volatile memory array using feedback-based estimation and adaptive pulse modulation. The method includes initializing a target weight, applying one or more programming pulses to a memory cell, estimating a weight state of the memory cell based on analog-to-digital conversion, determining a residual error between the estimated weight state and the target weight, and computing a subsequent programming pulse based on the residual error. The subsequent pulse may be adjusted by selecting a programming voltage from a quantized set of levels responsive to the recent weight response dynamics. The programming process may iterate until convergence may be achieved within a defined threshold. The technique supports precise control of conductance programming using closed-loop feedback and may be compatible with pulse-width, amplitude, and polarity modulation schemes.

A multi-reference-voltage sampled-bandgap system is provided in which a sample-and-hold circuit samples a bandgap reference voltage to produce a sampled bandgap reference voltage. The sample-and-hold circuit includes a voltage divider to divide the sampled bandgap reference into an at least one divided reference voltage.

The present disclosure relates to the field of memory technologies and provides a data sampling circuit, comprising a first sampling module configured to respond to a signal from the data signal terminal and a signal from the reference signal terminal and to act on the first node and the second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on the third node and the fourth node; a latch module configured to input a high level to the first output terminal and input a low level to the second output terminal, or to input the low-level signal to the first output terminal and input the high-level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and an offset compensation module connected in parallel to the second sampling module and configured to compensate an offset voltage of the second sampling module. In this data sampling circuit, the second sampling module is additionally provided, and the offset compensation module is connected in parallel to the second sampling module, such that kickback noise is reduced.

In an aspect, a circuit includes a first bootstrap capacitor configured to sample a varying input voltage during a first sample period. In an aspect, the circuit further includes a second bootstrap capacitor configured to sample the varying input voltage during a second sample period. In an aspect, the circuit also includes a switching circuit configured to connect and disconnect the first bootstrap capacitor and the second bootstrap capacitor from the varying input voltage during at least one hold period. In an aspect, the circuit additionally includes an input circuit configured to provide the varying input voltage to the first bootstrap capacitor and the second bootstrap capacitor responsive to a connection configuration of the switching circuit. The input circuit includes three complementary switch pairs. At least two of the three switch pairs are configured to share a common node that is, in turn, configured to receive the varying input voltage.

A system includes a bootstrap circuit having an input and an output. The bootstrap circuit includes a boost capacitor having a first terminal and a second terminal, a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit, a second transistor, and a third transistor, wherein the second transistor and the third transistor are coupled in series between a gate of the first transistor and the second terminal of the boost capacitor. The system also includes a switch transistor, wherein a gate of the switch transistor is coupled to the output of the bootstrap circuit, and a terminal of the switch transistor is coupled to the input of the bootstrap circuit.

To provide an analog neural memory system and method that has an input block and an output block which are configurable and a physical layout and that uses a nonvolatile memory cell.SOLUTION: In a vector matrix multiplication (VMM) system 3400, an input circuit block 3409 (3410) supports different numbers of arrays 3401, 3402 (3403, 3404) arranged in a horizontal direction, and an output circuit block 3411 (3412) supports different numbers of arrays 3401, 3403 (3402, 3404) arranged in a vertical direction.SELECTED DRAWING: Figure 34

The present disclosure relates to a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to, according to a signal from the third node and a signal from the fourth node, input high level and low level signals to a first output terminal and a second output terminal; and a decision feedback equalization module configured to reduce intersymbol interference. The data sampling circuit provided in the present disclosure can reduce intersymbol interference and have lower power consumption.

An analog in-memory computing (AIMC) system includes a plurality of tiles. A plurality of vertically stacked tiers are present on each tile. Each tier comprises a crossbar of resistive memory devices, configured to encode a matrix of weights. A digital to analog convert (DAC) is shared by the plurality of tiles. The DAC is configured to encode an input vector to voltage pulses applied on the crossbar. An analog to digital converter (ADC) is shared by the plurality of tiles, and includes a register of counters. The ADC is configured to measure an induced current on each column of the crossbar and digitize the induced current into a digital value. A programmable logic controller is configured to: control the ADC to retain integration values between integrations performed for each tier. An accumulation of partial integration results is performed in-situ of the tile.

The present disclosure relates to a three-terminal synaptic device for artificial neural network learning, a synaptic array using the same, and a method of operating the same. The three-terminal synaptic device includes a first transistor; an electrochemical memory (ECRAM) connected in parallel to the first transistor; and a second transistor connected in series to the parallel structure. Accordingly, the present disclosure can achieve an accuracy improvement of inference and learning operations in an artificial neural network through parallel operation by configuring a cross-point array based on the synaptic device with the three-terminal structure comprised of the electrochemical memory and two transistors.

To provide an improved decoding system and physical layout for an analog neural memory system which uses a non-volatile memory cell.SOLUTION: An analog neural memory system includes a plurality of vector matrix multiplication arrays, a plurality of low voltage row decoders, and a plurality of global high voltage row decoders. Each of the low voltage row decoders provides a row decoder function for one of the plurality of vector matrix multiplication arrays, and each of the global high voltage row decoders is shared by two of the plurality of vector matrix multiplication arrays and provides a high voltage signal to two of the plurality of low voltage row decoders.SELECTED DRAWING: None

The present disclosure provides a storage array, comprising storage units distributed in a matrix array, wherein each storage unit comprises two memories, and one P-channel field effect transistor and two N-channel field effect transistors which are alternately connected; the source electrode of the P-channel field effect transistor is connected to the drain electrode of each N-channel field effect transistor; the drain electrode of the P-channel field effect transistor is connected to the source electrode of the N-channel field effect transistor; the two memories are respectively connected to the source electrode of the P-channel field effect transistor and the source electrode of the N-channel field effect transistor. Use of the present invention can improve the density of the storage array and reduce the requirements for the driving capability of field effect transistors.

The present disclosure provides for crossbar circuits with minimized write disturbance. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of select lines, a plurality of cross-point devices, and a ramp-rate adjustable DAC that comprises a control circuit and an operational amplifier. An input of the operational amplifier is connected to a capacitor. The control circuit may generate, based on a digital input, a control signal. To program a cross-point device of the crossbar circuit, the capacitor may be charged using a reference current. As the charging rate of the capacitor is limited by the reference current, and the charging duration is controlled by the control signal, thus the output of the operational amplifier corresponds to the digital input and may be applied to the cross-point device as a programming signal with limited slew-rate adjustable by the reference current.

The present invention discloses various embodiments of a word line decoder, a control gate decoder, a bit line decoder, a low voltage row decoder, and a high voltage row decoder, as well as various types of physical layout designs for simulating a non-volatile flash memory array in a neural system. The present invention discloses shared and segmented embodiments of a high voltage row decoder.

In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a first bit line terminal, a first erase gate terminal, a first control gate terminal, a first floating gate, a word line, a second floating gate, a second control gate terminal, a second erase gate terminal, and a second bit line terminal, wherein the first floating gate can store a first digital or analog value and the second floating gate can store a second digital or analog value; and a bit line decoder for a column to selectively provide a first voltage to the first bit line terminals of non-volatile memory cells in the column and a second voltage to the second bit line terminals of the non-volatile memory cells in the column.

A top-plate sampling circuitry (10) for sampling a voltage input signal (11), the circuitry comprising: a sampling transistor (110) and a sampling capacitor (120); the sampling transistor being operable as a switch by a gate node (14) according to a tracking phase and a holding phase; a bootstrapper sub-circuitry (140) configured to bootstrap the voltage input signal with a fixed surplus voltage to a bootstrapped voltage (155), and to, during the tracking phase, provide the bootstrapped voltage to the gate node; and a gate switch (190) between the gate node and a fixed reference voltage (160), wherein the gate switch is configured to transition from open to closed during the switching, thereby opening the sampling transistor at a sampling time; wherein the circuitry is further configured to, during the switching from the tracking phase to the holding phase, provide a resistive coupling (180) between the bootstrapped voltage and the gate node.

A recursive Analog Content Addressable Memory (ACAM) device includes a first comparison stage and a second comparison stage. The first comparison stage includes a first match line, a first base segment comparator connected between the first match line and a reference node, a first incremented segment comparator, and a first pass transistor. The first pass transistor and the first incremented segment comparator are connected in series between the first match line and the reference node. The second comparison stage includes a first inverter connected to the first pass transistor, a second match line connected to the first inverter, and a second base segment comparator connected between the second match line and the reference node. The device enables efficient comparison of multi-bit values.

Embodiments provide a storage device that can improve characteristics of the storage device. According to one embodiment, a device includes a sense amplifier that senses a first signal based on first data in a cell and a second signal based on second data in the cell. The sense amplifier includes a current mirror that causes a first current to flow into a first node connected to the cell and causes a second current to flow into a second node based on a potential of the first node, a first switch connected to the second node and a third node, a transistor including a terminal connected to the second node and a gate connected to the third node, a second switch connected to the second node and a fourth node, and a circuit connected to the second node and the third node and causing a third current to flow into the second node based on a potential of the third node.

To provide an information storage system which simulates a neural network on a silicon chip without using a bit.SOLUTION: A neural network has: a plurality of islands periodically disposed in a first axis direction and a second axis direction on a surface of a semiconductor device; a first link and a second link disposed between two islands adjacent to each other in the first direction and the second direction among the plurality of islands; and a first word line in a third axis direction; and a second word line in a fourth axis direction. Each of the plurality of islands has a diffusion layer formed on the surface of the semiconductor device. The first link is a first selection gate for bridging the two islands adjacent to each other in the first direction among the plurality of islands. The second link is a second selection gate for bridging the two islands adjacent to each other in the second direction among the plurality of islands. The first selection gate and the second selection gate have respective selection gate contacts. The selection gate contact is selected by the first word line and the second word line.SELECTED DRAWING: Figure 7

An analog-to-digital converter (ADC) circuit includes a signal input terminal (101), a sample-and-hold circuit (110), and a successive approximation register (SAR) ADC (112). The sample-and-hold circuit (110) includes an input terminal (110A) coupled to the signal input terminal (101). The SAR ADC (112) includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

A sample and hold circuit includes a sampling circuit including a first amplifier configured to amplify an input voltage to generate an amplification voltage, the sampling circuit configured to perform a sampling operation of sampling the amplification voltage. The sample and hold circuit also includes a holding circuit configured to perform a holding operation of setting an output voltage to a voltage level of the input voltage, based on the sampling operation and an amplification operation of a second amplifier.

The invention relates to a memcapacitor element (1) for operating under a non-linear capacitance-voltage curve (2). The memcapacitor element (1) comprises a plurality of electrical contacts for making electrical contact with the memcapacitor element, a first electrode (3a) and a second electrode (3b). The memcapacitor element (1) further comprises at least one dielectric layer (5a, 5b) arranged between the first electrode and the second electrode, where the electrical contacts, the electrodes (3a, 3b) and / or the at least one dielectric layer (5a, 5b) have charge trapping sites forming potential wells of different depths for trapping different numbers of charges. In addition, the invention also relates to a method for operating the memcapacitor element.

A number of examples are described for providing an artificial neural network system with analog and digital arrays. In certain examples, the analog and digital arrays are coupled to shared bit lines. In other examples, the analog and digital arrays are coupled to separate bit lines.