118results about "Electric analogue stores" patented technology

A method is disclosed for programming analog-valued weights in a non-volatile memory array using feedback-based estimation and adaptive pulse modulation. The method includes initializing a target weight, applying one or more programming pulses to a memory cell, estimating a weight state of the memory cell based on analog-to-digital conversion, determining a residual error between the estimated weight state and the target weight, and computing a subsequent programming pulse based on the residual error. The subsequent pulse may be adjusted by selecting a programming voltage from a quantized set of levels responsive to the recent weight response dynamics. The programming process may iterate until convergence may be achieved within a defined threshold. The technique supports precise control of conductance programming using closed-loop feedback and may be compatible with pulse-width, amplitude, and polarity modulation schemes.

In an aspect, a circuit includes a first bootstrap capacitor configured to sample a varying input voltage during a first sample period. In an aspect, the circuit further includes a second bootstrap capacitor configured to sample the varying input voltage during a second sample period. In an aspect, the circuit also includes a switching circuit configured to connect and disconnect the first bootstrap capacitor and the second bootstrap capacitor from the varying input voltage during at least one hold period. In an aspect, the circuit additionally includes an input circuit configured to provide the varying input voltage to the first bootstrap capacitor and the second bootstrap capacitor responsive to a connection configuration of the switching circuit. The input circuit includes three complementary switch pairs. At least two of the three switch pairs are configured to share a common node that is, in turn, configured to receive the varying input voltage.

A system includes a bootstrap circuit having an input and an output. The bootstrap circuit includes a boost capacitor having a first terminal and a second terminal, a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit, a second transistor, and a third transistor, wherein the second transistor and the third transistor are coupled in series between a gate of the first transistor and the second terminal of the boost capacitor. The system also includes a switch transistor, wherein a gate of the switch transistor is coupled to the output of the bootstrap circuit, and a terminal of the switch transistor is coupled to the input of the bootstrap circuit.

The present disclosure relates to a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to, according to a signal from the third node and a signal from the fourth node, input high level and low level signals to a first output terminal and a second output terminal; and a decision feedback equalization module configured to reduce intersymbol interference. The data sampling circuit provided in the present disclosure can reduce intersymbol interference and have lower power consumption.

A top-plate sampling circuitry (10) for sampling a voltage input signal (11), the circuitry comprising: a sampling transistor (110) and a sampling capacitor (120); the sampling transistor being operable as a switch by a gate node (14) according to a tracking phase and a holding phase; a bootstrapper sub-circuitry (140) configured to bootstrap the voltage input signal with a fixed surplus voltage to a bootstrapped voltage (155), and to, during the tracking phase, provide the bootstrapped voltage to the gate node; and a gate switch (190) between the gate node and a fixed reference voltage (160), wherein the gate switch is configured to transition from open to closed during the switching, thereby opening the sampling transistor at a sampling time; wherein the circuitry is further configured to, during the switching from the tracking phase to the holding phase, provide a resistive coupling (180) between the bootstrapped voltage and the gate node.

A recursive Analog Content Addressable Memory (ACAM) device includes a first comparison stage and a second comparison stage. The first comparison stage includes a first match line, a first base segment comparator connected between the first match line and a reference node, a first incremented segment comparator, and a first pass transistor. The first pass transistor and the first incremented segment comparator are connected in series between the first match line and the reference node. The second comparison stage includes a first inverter connected to the first pass transistor, a second match line connected to the first inverter, and a second base segment comparator connected between the second match line and the reference node. The device enables efficient comparison of multi-bit values.

Embodiments provide a storage device that can improve characteristics of the storage device. According to one embodiment, a device includes a sense amplifier that senses a first signal based on first data in a cell and a second signal based on second data in the cell. The sense amplifier includes a current mirror that causes a first current to flow into a first node connected to the cell and causes a second current to flow into a second node based on a potential of the first node, a first switch connected to the second node and a third node, a transistor including a terminal connected to the second node and a gate connected to the third node, a second switch connected to the second node and a fourth node, and a circuit connected to the second node and the third node and causing a third current to flow into the second node based on a potential of the third node.

To provide an information storage system which simulates a neural network on a silicon chip without using a bit.SOLUTION: A neural network has: a plurality of islands periodically disposed in a first axis direction and a second axis direction on a surface of a semiconductor device; a first link and a second link disposed between two islands adjacent to each other in the first direction and the second direction among the plurality of islands; and a first word line in a third axis direction; and a second word line in a fourth axis direction. Each of the plurality of islands has a diffusion layer formed on the surface of the semiconductor device. The first link is a first selection gate for bridging the two islands adjacent to each other in the first direction among the plurality of islands. The second link is a second selection gate for bridging the two islands adjacent to each other in the second direction among the plurality of islands. The first selection gate and the second selection gate have respective selection gate contacts. The selection gate contact is selected by the first word line and the second word line.SELECTED DRAWING: Figure 7

An analog-to-digital converter (ADC) circuit includes a signal input terminal (101), a sample-and-hold circuit (110), and a successive approximation register (SAR) ADC (112). The sample-and-hold circuit (110) includes an input terminal (110A) coupled to the signal input terminal (101). The SAR ADC (112) includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

A sample and hold circuit includes a sampling circuit including a first amplifier configured to amplify an input voltage to generate an amplification voltage, the sampling circuit configured to perform a sampling operation of sampling the amplification voltage. The sample and hold circuit also includes a holding circuit configured to perform a holding operation of setting an output voltage to a voltage level of the input voltage, based on the sampling operation and an amplification operation of a second amplifier.

The invention relates to a memcapacitor element (1) for operating under a non-linear capacitance-voltage curve (2). The memcapacitor element (1) comprises a plurality of electrical contacts for making electrical contact with the memcapacitor element, a first electrode (3a) and a second electrode (3b). The memcapacitor element (1) further comprises at least one dielectric layer (5a, 5b) arranged between the first electrode and the second electrode, where the electrical contacts, the electrodes (3a, 3b) and / or the at least one dielectric layer (5a, 5b) have charge trapping sites forming potential wells of different depths for trapping different numbers of charges. In addition, the invention also relates to a method for operating the memcapacitor element.

To improve an operation speed of a circuit.SOLUTION: There are provided: a first transistor; a second transistor in which a first terminal is connected to a gate of the first transistor, and has a function for setting a value of a potential of the gate of the first transistor to a value where the first transistor is ON; a third transistor that sets a value of the potential of the gate of the second transistor to a value where the second transistor is ON, and has a function for setting the gate of the second transistor to be in a floating state; and a fourth transistor that has a function for setting a value of the potential of the gate of the second transistor to a value where the second transistor is OFF. By such a construction, a potential difference between the gate and a source of the second transistor can be maintained so as to be a value that is larger than a threshold value voltage of the second transistor, and can improve an operation speed.SELECTED DRAWING: Figure 1

A compute-in-memory (CIM) circuit includes a processing circuit. The processing circuit includes a data-selection circuit and a charge-domain passive summation circuit. The data-selection circuit includes a memory array and a selection circuit. The memory array stores a plurality of candidate weights. The selection circuit selects a target weight from the plurality of candidate weights stored in the memory array. The charge-domain passive summation circuit generates an analog computation result of an input received by the processing circuit and the target weight stored in the memory array through a weighted capacitor array integrated with the memory array.

A satisfiability modulo theories (SMT) solver accelerator is implemented with analog content addressable memory (CAM) cells. A job-shop scheduling problem (JSSP) may be mapped to expression clauses that are stored in an analog CAM array. A test cycle may be performed by searching for a test vector of input variables in the analog CAM array, selecting a candidate variable of the test vector that is violating a largest number of the expression clauses, and changing the candidate variable of the test vector. The test cycle may be repeated until none of the expression clauses are violated by the test vector of the input variables. The resulting test vector of the input variables that violates no expression clauses is a solution for the JSSP.

The present disclosure provides for crossbar circuits with minimized write disturbance. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of select lines, a plurality of cross-point devices, and a ramp-rate adjustable DAC that comprises a control circuit and an operational amplifier. An input of the operational amplifier is connected to a capacitor. The control circuit may generate, based on a digital input, a control signal. To program a cross-point device of the crossbar circuit, the capacitor may be charged using a reference current. As the charging rate of the capacitor is limited by the reference current, and the charging duration is controlled by the control signal, thus the output of the operational amplifier corresponds to the digital input and may be applied to the cross-point device as a programming signal with limited slew-rate adjustable by the reference current.

Image sensor, which includes the following: a pixel array including multiple pixels configured and functional to detect light from a scene, wherein the scene includes an object to be detected and a background image, wherein each pixel of the multiple pixels is configured to generate a new voltage signal in response to the intensity of light received by the pixel; a memory for storing digital values ​​corresponding to a predetermined voltage bandwidth around a prior voltage signal R of at least some of the multiple pixels corresponding to the light detected from the background image, wherein the voltage bandwidth defines a positive delta voltage +Δ and a negative delta voltage -Δ relative to the background voltage signal R; a sample-and-hold or track-and-hold module capable of sampling the new voltage signal corresponding to one of the several pixels selected; a digital-to-analog converter that generates a reference voltage R+Δ or R-Δ from the digital values ​​stored in the memory; a comparator that receives the new voltage signal sample value from the hold module and receives one of the reference voltages R+Δ or R-Δ for the selected pixel to compare it with the voltage signal sample value, wherein the comparator is configured to produce a high-voltage output signal if the voltage signal sample value is greater than the reference voltages R+Δ or R-Δ, and to produce a low- or zero-voltage output if the voltage signal sample value is less than the reference voltages R+Δ or R-Δ; a two-bit register containing a most significant bit (MSB) and a least significant bit (LSB), wherein the two-bit register provides a two-bit output signal; and a logic module that receives the voltage output from the comparator, wherein the logic module is configured and functional as follows: Selecting the reference voltage R+Δ to be supplied to the comparator, and setting the MSB to a logic "0" in response to a low-voltage output signal from the comparator or to a logic "1" in response to a high-voltage output signal from the comparator; and then Selecting the reference voltage R-Δ to be supplied to the comparator and setting the LSB to a logic "0" in response to a low-voltage output signal from the comparator or to a logic "1" in response to a high-voltage output signal from the comparator; a background subtraction module configured and functional to receive the two-bit output signal from the two-bit register for the selected pixel and, based on the two-bit output signal, to identify the selected pixel as detecting light from a scene that is different from the light detected by the same pixel in the background image; and a processing module for generating an output image that includes the selected pixel identified by the background subtraction module.

One aspect of the invention relates to an electrochemical storage device comprising an ionic transistor and an ionic capacitor electrically connected in series.

A reference buffer is disclosed. The reference buffer includes an amplifier configured to amplify a difference between a reference output voltage and a reference input voltage during a closed-loop phase of the reference buffer. The reference buffer also includes a sample circuit configured to sample an amplifier output voltage during the closed-loop phase. The reference buffer further includes a buffer circuit having a buffer input coupled to the sample circuit and a buffer output configured to provide the reference output voltage. The reference buffer also includes first and second switch circuits. The first switch circuit is configured to isolate the sample circuit from the output stage of the amplifier during an open-loop phase of the reference buffer. The second switch circuit is configured to isolate the input stage from the output of the reference buffer during the open-loop phase.

Computational weight data for an in-memory computation operation is written to memory cells in a memory array with a randomly selected polarity inversion. During execution of the in-memory computation operation, the computational weight data is read from memory cells in the memory array. A polarity inversion is applied to the read computational weight data when that read computational weight data was written to memory cells in the memory array with the randomly selected polarity inversion.

An apparatus includes a discrete time analog front-end circuit. The discrete time analog front-end circuit includes: a sample and hold circuit; a discrete time linear equalizer circuit having an input coupled to the output of the sample and hold circuit; and a discrete time programmable gain amplifier circuit having an input coupled to the output of the discrete time linear equalizer circuit. The sample and hold circuit is to generate a discrete time modulated signal based at least in part on the continuous time modulated signal. The discrete-time linear equalizer circuit is configured to generate an equalized discrete-time modulated signal based at least in part on the discrete-time modulated signal. The discrete-time programmable gain amplifier circuit is to generate an amplified equalized discrete-time modulated signal based at least in part on the equalized discrete-time modulated signal. A discrete-time analog front-end circuit may include a quantizer circuit having an input coupled to an output of a discrete-time programmable gain amplifier circuit.

To provide an input block for an analog neural memory in a deep learning artificial neural network.SOLUTION: The invention provides an input block for providing an input to a vector-by-matrix multiplication array (VMM array 3506) in a neural memory system. The vector-by-matrix multiplication array comprises non-volatile memory cells arranged in rows and columns. The input block comprises: a global digital-to-analog converter 3501; a plurality of row registers 3502, each row register corresponding to a row in the VMM array; and a plurality of row sample-and-hold buffers 3504, each row sample-and-hold buffer corresponding to a row in the VMM array.SELECTED DRAWING: Figure 35A

The present disclosure relates to sample-and-hold techniques for reading charger current in discontinuous conduction mode. The current monitoring system may include a sample-and-hold circuit to generate a sample-and-hold signal (S / H signal), where the S / H signal corresponds to a peak value of a current in the charging circuit during a switching period of the charging circuit. The system may also include a first analog-to-digital channel (ADC channel) for sampling the S / H signal; and a second ADC channel configured to sample a current in the charging circuit. The system may then determine an average current of the charging circuit based on the first ADC channel when the charging circuit is operating in the discontinuous conduction mode, and determine an average current of the charging circuit based on the second ADC channel when the charging circuit is operating in the continuous conduction mode.

Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.

A semiconductor device capable of holding analog data SOLUTION: Two holding circuits, two bootstrap circuits, and one source follower circuit are formed using four transistors and two capacitors. Each of the two holding circuits is provided with a memory node, a data potential is written to one of the memory nodes, and a reference potential is written to the other memory node. When data is read, the potential of one storage node is boosted by one bootstrap circuit, and the potential of the other storage node is boosted by the other bootstrap circuit. To output a potential difference between two storage nodes by using a source follower circuit. By using the source follower circuit, the output impedance can be reduced.SELECTED DRAWING: Figure 1

The embodiment of the invention relates to the field of semiconductors, and provides a data receiving circuit which comprises a data receiving module, a data inverting module, a feedback equalization module and a data judgment module, the feedback equalization module and the data receiving module are independently arranged, and the feedback equalization module is configured to execute judgment feedback equalization based on an enable signal and a feedback signal, wherein the feedback signal is obtained based on previously received data, so that the first voltage signal and the second voltage signal which have a first time difference are adjusted into a third voltage signal and a fourth voltage signal which have a second time difference; a third voltage signal and a fourth voltage signal are sequentially received through a data judgment module according to the time of reaching a third node and a fourth node, and a first output signal and a second output signal are output through a fifth node and a sixth node respectively.

A hybrid digital-analog memory device for secure storage and computation and an operating method thereof are disclosed. A nonvolatile memory device according to an embodiment includes a plurality of memory cells arranged in a matrix form; a plurality of word lines extending in a first direction, wherein each memory cell is connected with one of the plurality of word lines; a plurality of bit lines extending in a second direction different from the first direction, wherein each memory cell is connected with one of the plurality of bit lines; a word line control circuit connected with the word lines and configured to control the word lines; a first bit line control circuit configured to control the bit lines, wherein the first bit line control circuit is connected with a first end of each bit line; and a second bit line control circuit configured to control the bit lines, wherein the second bit line control circuit is connected with a second end of each bit line, the second end being opposite to the first end.

A method of operating memory cells includes programming memory cells at a first temperature to different program states associated with first read current values confirmed by using nominal read conditions. Modified read conditions are determined such that a second read current for the one memory cells at a second temperature is approximately equal to the first read current value for the one memory cell. A read operation is performed on the memory cells at the second temperature using the modified read conditions to determine respective third read current values. Error read current values are determined as respective differences between the first and third read current values. Upper and lower program states are assigned to respective desired program states, with read currents that correspond approximately to respective determined error read current values, and are separated approximately by a respective target read current value associated with the respective desired program state.

A sampling switching circuit includes: an input node connected to receive an input voltage signal to be sampled; a sampling transistor including a gate terminal, a source terminal, and a drain terminal, the source terminal being connected to the input node; a capacitor; a current source configured to allow a defined current to flow through it; and a switching circuit system configured to alternate between a pre-charge configuration and an output configuration according to a clock signal. In the pre-charge configuration, the switching circuit system connects the capacitor to a current path between the current source and a first voltage reference node to create a potential difference across the capacitor that depends on the defined current. In the output configuration, the switching circuit system connects the capacitor between a second voltage reference node and the gate terminal of the sampling transistor such that the voltage level applied at the gate terminal of the sampling transistor depends on the defined current.