264 results about "Bit cell" patented technology

The invention relates to the technical field of integrated circuits, and discloses a parallel-serial conversion circuit. The parallel-serial conversion circuit comprises a parallel data storage unit, an odd-even data exchange unit, a shifting unit and a selection output unit, the parallel data storage unit is connected with a parallel data input end and a parallel clock signal end, and the odd-even data exchange unit is connected between the parallel data storage unit and the shifting unit. The data output module is used for directly outputting parallel data or performing odd-even data bit exchange on the parallel data according to a first selection control signal and then outputting the parallel data; the shifting unit is connected with the odd-even data exchange unit, the selection output unit and a serial clock signal end; and the selection output unit is connected with the shift unit, the serial clock signal input end and the serial data output end, and is used for sequentially and serially outputting each bit of data in the shift data along with the high and low levels of the serial clock signal. According to the technical scheme, the specific parallel-serial conversion mode can be dynamically configured, and the use flexibility of the I / O interface of the FPGA is improved.

A bit cell (100) is disclosed that includes a non-volatile memory element (110) and a transistor arrangement (120) configured to provide a write signal that switches a state of the memory element. A first terminal (111) of the memory element is connected to a bit line (BL), a second terminal (112) of the memory element is connected to a first common source / drain terminal (121) of the transistor arrangement, and a second common source / drain terminal (122) of the transistor arrangement is connected to a source line (SL). The transistor device includes a pair of stacked complementary transistors, where a gate (213) of an upper transistor is connected to a first word line (WLN), and where a gate (233) of a lower transistor is connected to a second word line (WLP). A memory device including an array of such bit cells, and a method for controlling bit cells are also disclosed.

An integrated circuit includes a substrate; a bit cell array including bit cells on the substrate; a frontside wiring layer above the substrate in a vertical direction with respect to a front side of the substrate, the frontside wiring layer including local word lines connected to the bit cells; a row decoder configured to provide word line signals for driving the bit cell array; a backside wiring layer on a backside of the substrate, the backside wiring layer including backside wiring lines configured to receive the word line signals from the row decoder; and a word line rebuffer configured to provide the word line signals received from the backside wiring lines to the local word lines.

The embodiment of the invention provides a display device and a driving method thereof. The display device comprises N rows of pixel units and N levels of gate driving units, wherein the ith level of gate driving unit is electrically connected with a gate line of the ith row of pixel units. The ith-level gate driving unit comprises a pull-up unit and a reset unit, the pull-up unit is electrically connected with a first node, a gate driving signal output end and a level transmission signal output end, the reset unit comprises a first reset subunit and a second reset subunit, the first reset subunit is electrically connected with a first reset control signal line, and the second reset subunit is electrically connected with a second reset control signal line. The second reset subunit is electrically connected with a second reset control signal line. The first reset subunit and the second reset subunit are electrically connected with the first node, the gate drive signal output end and the level transmission signal output end. According to the display device provided by the embodiment of the invention, the charge emptying capability of the gate driving unit on the key node is enhanced, the working time of the thin film transistor is shortened, and the reliability of the gate driving unit is improved.

The application discloses a sensitive amplifier and a storage chip. The sensitive amplifier comprises a first clamping unit, a second clamping unit, a first current unit and a feedback unit. The control end of the first clamping unit is coupled with a total bit line through the feedback unit, so that the potential change of the total bit line forms a closed-loop control. That is, when the potential of the total bit line rises, the current flowing through the first current unit and the feedback unit is reduced, and the current flowing through the second clamping unit is increased. The potential of the control end of the first clamping unit is reduced, the current flowing through the first clamping unit is also reduced, and the potential of the total bit line is reduced to a preset potential and is kept stable. Conversely, the potential of the total bit line is increased to a preset potential and is kept stable.

A circuit includes a memory array including memory bit cells arranged in rows and columns. A row includes differential reference bit cells and single-ended bit cells, and the reference bit cells include a first set configured to store a first binary value and a second set configured to store a second binary value different from the first binary value. The circuit also includes a control module configured to generate a first reference current and to select the given row for a read operation. The circuit additionally includes an input / output module configured to compare a sensed current of a respective single-ended bit cell of the single-ended bit cells for the read operation to a second reference current. The second reference current is based on the first reference current and respective currents of the first set of reference bit cells and the second set of reference bit cells.

The present disclosure provides a semiconductor structure comprising a substrate having a front side and a back side; an SRAM circuit having SRAM bit cells formed on a front side of the substrate, where each SRAM bit cell includes two inverters cross-coupled together, two write pass gates coupled to the two inverters, a read pull-down device coupled to the two inverters, and a read pass gate coupled to the read pull-down device, and wherein each SRAM bit cell is connected to the WBL, the WBLB, the RBL, the Vdd, and the Vss; a first subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the front side of the substrate to a first of the SRAM bit cells; a second subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the backside of the substrate to the first SRAM bit cell.

An SRAM architecture is disclosed that provides a process- and temperature-compensated word-line underdrive scheme enabling stable, low-voltage operation. Each row decoder generates an initial word-line signal, derives an inverse word-line signal, and drives the corresponding word line through driver circuitry including a word-line underdrive p-channel transistor. The transistor's gate is controlled by the inverse word-line signal and optionally receives a dynamically generated negative bias to reduce device size while maintaining performance. Control circuitry includes a word-line underdrive sink circuit having dummy memory cells that replicate bit-cell behavior to generate a compensated driver output signal tracking process and temperature variations. A negative bump generator produces a transient below-ground potential at the gate node to enhance underdrive efficiency. This improves bit-cell stability, dynamic noise-margin yield, and performance uniformity across process corners and temperature, while minimizing silicon area.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a logic block and a p-bit block. The logic block includes a plurality of plurality of logic elements. The p-bit block includes a transistor, a first bit cell with a magnetic structure and at least one second bit cell with a resistance structure. The first bit cell with the magnetic structure is connected to one end of the transistor. The at least one second bit cell with the resistance structure is connected to another end of the transistor.

To provide a low-power, high-density, 1T-1C (one transistor and one capacitor) memory bit-cell.SOLUTION: The capacitor has a pillar structure, which comprises ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.SELECTED DRAWING: Figure 1C

The invention discloses a method, system and medium for a voltage clamping unit in a chip circuit, and belongs to the technical field of chip circuit protection, and the method comprises the steps: obtaining a maximum allowable voltage deviation window and a maximum allowable voltage rise rate of a target input / output pin of a chip, and constructing a target clamping characteristic parameter set; selecting a clamp sub-model based on the parameter set; adjusting capacitance matching unit parameters according to the equivalent input capacitance of the target pin by combining a support vector regression algorithm with a genetic algorithm; connecting a clamping model and injecting a test voltage waveform, and extracting clamping response time and clamping voltage to construct feedback characteristics; a mathematical model between the clamping response time and the delay gate series is generated through a symbol regression algorithm, and a control delay unit structure is corrected; according to the method, closed-loop adaptive adjustment of clamping parameters is realized, the transient interference suppression capability and clamping precision of the chip under high-frequency and low-voltage conditions are improved, and the method has good reliability and expandability.

The invention discloses a gray scale voltage correction method based on a gamma curve, which is applied to a pixel driving circuit without a reset unit, and comprises the following steps: determining gray scale brightness corresponding to a target binding point gray scale of the pixel driving circuit; detecting the light emitting brightness of the pixel driving circuit, and recording a target write-in data voltage; constructing a gray scale voltage formula of the pixel based on the plurality of target write-in data voltages; and obtaining a plurality of gray-scale voltage values based on the gray-scale voltage formula and generating a corrected gray-scale voltage curve.

A method of manufacturing an information processing device and a mobile computer are disclosed, the method of manufacturing including storing an installation program in a first storage area of a solid state drive (SSD) of the information processing device, the installation program, when executed, causing the information processing device to install pre-load data, executing the installation program to at least partially install the pre-load data in a second storage area of the SSD, and after executing the installation program, moving a portion of the pre-load data stored in the second storage area to the first storage area of the SSD. The first storage area is configured to store single-bit cells in which one bit of data is stored in one memory cell, and the second storage area is configured to store multi-bit cells in which multiple bits of data are stored in one memory cell.

The invention discloses a PAM and PWM hybrid modulation pixel driving circuit and method, the circuit comprises a PAM module, a PWM module and a micro light emitting diode, the PAM module comprises a driving unit A, a compensation unit B, a compensation unit C, a data write-in unit D, a control unit E and a reset unit F, and the PWM module comprises a driving unit a, a compensation unit b, a compensation unit c, a data write-in unit d and a control unit e. According to the invention, PAM and PWM hybrid modulation of the pixel circuit is realized, threshold voltage compensation and power line voltage drop compensation are carried out on the circuit modulation module at the same time, the anti-interference capability of the circuit is improved, the brightness uniformity of a display screen is improved, and the display effect is enhanced.

A multilevel converter (1) comprises a plurality of bit cells (31-35) that output DC voltages different from one another. Each of the bit cells (31-35) includes switching elements (Q1-Q4) configured to charge or discharge a power storage element (C) by performing a switching operation in response to a control command from a control device (7). The control device (7) repeatedly outputs a plurality of switching patterns in which control commands for the bit cells (31-35) are arranged in time series. The switching patterns are temporally symmetrical for each cycle, and are determined such that the length of a charging period and the length of a discharging period for the power storage element (C) are equal.

The application relates to the field of integrated circuit technology and discloses a parallel-serial conversion circuit. The parallel-serial conversion circuit comprises a parallel data storage unit, a parity data exchange unit, a shift unit and a selection output unit. The parallel data storage unit is connected with a parallel data input end and a parallel clock signal end. The parity data exchange unit is connected between the parallel data storage unit and the shift unit and is used for directly outputting parallel data or outputting the parallel data after parity data bit exchange according to a first selection control signal. The shift unit is connected with the parity data exchange unit, the selection output unit and a serial clock signal end. The selection output unit is connected with the shift unit, a serial clock signal input end and a serial data output end and is used for sequentially and serially outputting each bit data in the shift data according to the high and low levels of the serial clock signal. The technical scheme can dynamically configure a specific parallel-serial conversion mode and improves the flexibility of I / O interface use of the FPGA.

A method includes forming a front-side pass-gate transistor over a front-side of a substrate, wherein the front-side pass-gate transistor is comprised in a memory bit-cell, and is of a first conductivity type; forming a back-side pull-down transistor over a back-side of the substrate, wherein the back-side pull-down transistor is comprised in the memory bit-cell, and is of a second conductivity type opposite to the first conductivity type, and the back-side pull-down transistor is an oxide semiconductor transistor.

Various implementations described herein are related to a read multiplexer circuit for a multiport register file, comprising: an input stage coupled to an array of storage nodes, each storage node coupled to drive an output of a respective bitcell; a read stage comprising control logic dividing the array of storage nodes into one or more sets and first circuitry that provides a first read word line to a first storage node of a first set for reading data from the first storage node and a second read word line to a second storage node of the first set for reading data from the second storage node; and a first latch stage comprising second circuitry that provides a third read word line to the first and second storage node of the first set to latch the read from one of the first and second storage nodes.

The array substrate row driving circuit provided in the application comprises a plurality of cascade gate driving modules, wherein the nth gate driving module comprises a pull-up control unit, a pull-up unit, a pull-down unit, a first pull-down maintaining unit, a second pull-down maintaining unit and a global reset unit, the global reset unit is electrically connected with a first node, a first low-frequency clock signal end, a second low-frequency clock signal end and a first reference signal end, the global reset unit is electrically connected with the first low-frequency clock signal end and the second low-frequency clock signal end instead of being electrically connected with a global reset signal end, so that the number of signal ends electrically connected with the array substrate row driving circuit is reduced, the number of GOA signal lines electrically connected with the signal ends is reduced, and the narrow frame of the display panel is facilitated.

A secure anti-fuse one-time programmable (OTP) bit cell is disclosed. In one aspect, the OTP bit cell includes: a P well including an N + region and a P + region; a first contact electrically coupled to the N + region of the P well; a second contact electrically coupled to the P + region of the P well; an insulating layer disposed over a portion of the N + region, a portion of the P well, and a portion of the P + region; a gate structure disposed over the insulating layer; and a third contact electrically coupled to the gate structure. In the unprogrammed mode, the insulating layer produces a high resistance between the third contact and the second contact, and in the programmed mode, a fracture in the insulating layer produces a low resistance between the third contact and the second contact.

The present disclosure relates to a power domain management circuit and a system on chip. The power domain management circuit includes: an enable unit, configured to generate an enable signal with a first preset level in a case of receiving an isolation set signal, or to generate an enable signal with a second preset level in a case of receiving a reset indication signal; and a clamping unit, electrically connected to the enable unit, and configured to clamp an initial signal transmitted from a first power domain to a second power domain to generate a target signal with a third preset level in a case of receiving the enable signal with the first preset level, or to skip clamping the initial signal to generate a target signal with a level that varies with a level of the initial signal in a case of receiving the enable signal with the second preset level.

An integrated circuit device includes a semiconductor substrate, a plurality of multi-bit cells over the semiconductor substrate, a first pad, and a second pad. Each of the multi-bit cells includes first and second bits. The first bit includes a first electrostatic discharge (ESD) protection circuit and a first strap region in the semiconductor substrate. The second bit includes a second ESD protection circuit and a second strap region in the semiconductor substrate. The first strap region of the first bit is symmetric to the second strap region of the second bit with respect to a border between the first bit and the second bit in a top view, and the first p-type strap region of the first bit and the second strap region of the second bit have a first conductivity type. The first and second pads are respectively connected to the first and second ESD protection circuits.

An apparatus includes an N-type bit-cell bundle with a first N-type bit-cell array, a first merge circuit, and a second N-type bit-cell array coupled to the first N-type bit-cell array via the first merge circuit. The apparatus includes a P-type bit-cell bundle coupled in a horizontal direction to the N-type bit-cell bundle via a spacer area. The P-type bit-cell bundle includes a first P-type bit-cell array, a second merge circuit, and a second P-type bit-cell array. The second P-type bit-cell array is coupled to the first P-type bit-cell array via the second merge circuit.

The invention discloses a grid control self-compensation field sequence display circuit. The grid control self-compensation field sequence display circuit comprises a self-compensation unit, a pre-writing unit, a display unit and a reset unit, the self-compensation unit comprises a first transistor, a third transistor, a fourth transistor and a fifth transistor; the grid electrode of the fourth transistor is coupled to a first reset signal line, the first source and drain electrode of the fourth transistor is coupled to the pre-writing unit, and the second source and drain electrode of the fourth transistor is coupled to the first source and drain electrode of the sixth transistor and the display unit; the grid electrode of the sixth transistor is coupled to the second source and drain electrode of the fifth transistor, and the second source and drain electrode of the sixth transistor is coupled to a global driving signal line; the reset unit is coupled with the display unit. The circuit has the beneficial effects that threshold voltage deviation caused by process deviation and long-term use can be eliminated by acquiring the threshold voltage of the sixth transistor in the circuit, so that uniform and consistent picture brightness is ensured, and the service life of a product is prolonged.

The invention relates to a memory array and a reference current circuit. A circuit (100) includes a memory array (110) including memory bit cells arranged in rows and columns. A row includes differential reference bit cells (114) and single-ended bit cells (112), and the reference bit cells (114) include a first set configured to store a first binary value and a second set configured to store a second binary value different from the first binary value. The circuit (100) also includes a control module (120) configured to generate a first reference current and select a given row for a read operation. The circuit (100) additionally includes an input / output module (130) configured to compare a sensed current of a respective one of the single-ended bit cells (112) for the read operation to a second reference current.

An embedded memory device includes a retention voltage supply circuit outputting a retention voltage in response to a retention activation signal, and a plurality of array voltage supply circuits outputting corresponding array voltages to corresponding bit cells. The plurality of array voltage supply circuits respectively include an array switch providing the retention voltage as a corresponding array voltage in response to the retention activation signal, a power switch providing a power supply voltage as the corresponding array voltage in response to a power gate activation signal, and an auxiliary circuit compensating the corresponding array voltage during a write operation or a read operation.

The application provides a token ring-based spike scanning arbitration circuit, which comprises a spike scanning circuit and a token ring circuit; the spike scanning circuit comprises a first complementing unit, a preprocessing unit composed of a subtraction unit and an inverter INV connected in sequence, and an AND gate AGND and an OR gate OR; and the token ring circuit comprises an edge detection unit, a token unit and a second complementing unit connected in sequence. The token ring circuit can use tokens to fairly distribute priorities among all request signals, the spike scanning circuit scans the request signals, and outputs corresponding response signals according to the priorities of the request signals, so that the speed of the arbitration circuit is improved, the fair arbitration in time and space is realized, and the imaging quality of a dynamic visual sensor is effectively improved.

A storage system and circuits therefor. A storage system includes a bitcell array comprising a plurality of storage cells arranged in one or more columns and one or more rows; a read bitline associated with a first column to access storage cells of the first column, wherein the read bitline has a first keeper circuit coupled thereto; and a tracker bitline associated with the read bitline, wherein the tracker bitline has a second keeper circuit coupled thereto, and wherein the tracker bitline is configured such that a behaviour thereof is to substantially match a behaviour of the read bitline.

A compensation resistor is gated by arranging a compensation circuit switch to be gated in synchronization with the reception of a bit cell, and corresponding resistance compensation is performed on the bit cell which is gated by a total resistance value of a pre-designed compensation resistor array structure, and compensation resistor traces are sequentially connected in series into two metal wires.