452 results about "Bit cell" patented technology

An example embodiment of the present invention provides a semiconductor device including: an encoder configured to receive a plurality of bit data by dividing the plurality of bit data into first group data and second group data, the plurality of bit data being divided into 2-bit units, to delay the second group data for a first period, and to output the first group data and the delayed second group data; and an output driver configured to output the first group data and the delayed second group data together to an external semiconductor device.

Inrush current in a memory such as SRAM cache may be managed by using one or more integrated delay elements such as inverters, RC delay lines, and the like to significantly slow down power down signal propagation between memory instances in a memory array. The delay in some examples may be between memory instances, while in other examples the delay is also introduced between bitcell arrays within a memory instance. By staggering the power up times of interconnected or chained memory instances, inrush current when powering the memory instances on or resuming from an inactive state may be reduced.

Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a TCAM array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, weights in a weight matrix may be programmed in SRAMs of a TCAM bit cell array. Each SRAM may operate as a multiplier that performs a multiplication between the stored weight to an input activation value applied at a search line in the TCAM bit cell array. The two SRAMs within a TCAM bit cell may operate independently to receive independently two input activation values on their respective select lines, and to perform a multiplication operation with the stored weight in each respective SRAM.

An integrated circuit includes first bit cells, second bit cells, and clock cells. Each of first bit cells is arranged in one of multiple first cell rows having a first row height. Each of the second bit cells is arranged in one of multiple second cells rows having a second row height different from the first row height. The second bit cells extend to pass the first bit cells in a first direction. The clock cells are arranged in peripheral regions of a multi-bit flip flop cell in the first cell rows. The first and second bit cells and the clock cells are included in the multi-bit flip flop cell.

A circuit includes a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit. The circuit includes a second plural number (S) of multiplexers operatively coupled to the scan chain, wherein the S is determined asNM,where the M represents a diagnostic resolution. The multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages.

The invention relates to hydraulic pump return plate machining equipment, and belongs to the technical field of machining. The equipment aims to solve the problems that in the prior art, a return plate is prone to deformation during machining, and grinding precision is insufficient. The equipment comprises a rack, a limiting unit, a lifting mechanism and a grinding mechanism. Wherein the limiting unit is matched with the limiting groove through a clamping assembly to limit horizontal and vertical movement of the blank piece; the grinding mechanism comprises a plurality of grinding execution units rotating synchronously, and precise machining of an inner cavity of the blank is achieved through a rotary grinding assembly. A positioning adjusting module of the clamping assembly is provided with an avoiding structure and can be matched with a to-be-machined hole site of the blank. The grinding execution unit adopts a reverse rotation design, so that the machining efficiency and precision are improved; in addition, the vertical movement of the grinding mechanism is accurately controlled through the lifting mechanism, and the equipment is suitable for machining blanks with different heights; the method has the advantages of high machining precision, wide application range, convenience in operation and the like.

A memory device is provided. The memory device includes a compute-in-memory (CIM) array, capacitor circuit pairs, a first switch circuit and an analog-to-digital converter. The CIM array includes bit cells arranged in columns, in which the CIM array generates, in response to an input vector and a stored vector in the bit cells, accumulation results. The capacitor circuit pairs receive the accumulation results through bit lines, in which portions, in one of the columns, of the bit cells and a corresponding one of capacitor circuit pairs are coupled to a corresponding bit line of the bit lines. The first switch circuit is coupled to the capacitor circuit pairs is switched to generate, based on the accumulation results, weight mean results in one capacitor circuit in each of the plurality of capacitor circuit pairs. The analog-to-digital converter generates, according to the plurality of weight mean results, a multiply-and-accumulate result.

An integrated circuit includes a one-time programmable (OTP) bit cell including a program transistor and a read transistor arranged on an active region extending on a front side of a substrate in a first direction, a first backside gate contact penetrating the substrate in a vertical direction and overlapped by the active region, a backside wiring layer arranged on a backside of the substrate and connected to a first gate of the program transistor via the first backside gate contact to transfer a program word line signal to the first gate, and a front side wiring layer arranged above the front side of the substrate and including a first front side wiring pattern connected to a second gate of the read transistor to transfer a read word line signal to the second gate.

A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.

A memory is provided that includes an analog gate voltage driver that drives the gate of a head switch transistor for a bitcell array with an analog gate voltage while the bitcell array operates in a light-sleep mode. The analog gate voltage switches the head switch transistor partially on so that the head switch transistor passes a reduced power supply voltage despite being powered by a memory power supply voltage that is greater than the reduced power supply voltage. The reduced power supply voltage has a sufficient magnitude so that the bitcell array retains its stored binary contents during the light-sleep mode.

The invention relates to a pixel driving circuit and a display panel, and relates to the technical field of display driving. The pixel driving circuit comprises a driving transistor, a write-in unit, a storage capacitor, a connecting unit, a reset unit and a light-emitting control unit. A first electrode of the driving transistor is connected with the connecting unit and the light-emitting control unit at a first node, a second electrode is connected with the writing unit and the light-emitting control unit at a second node, and a control electrode is connected with the connecting unit and the storage capacitor at a third node; the reset unit is connected with the storage capacitor and the anode of the light-emitting device; wherein the write-in unit is connected with the first driving unit; the connection unit and the reset unit are respectively connected with the second driving units of different levels; and the light-emitting control unit is connected with the third driving units of different levels. By resetting the second driving units of different levels and the third driving units of different levels, the total number of the required gate driving circuits is reduced, and the narrow frame design of the display panel can be realized.

The invention discloses a low-delay Montgomery modular multiplier. The modular multiplier comprises an iteration control unit, a parallel part and generation unit, a quotient operation unit of a multi-stage pipeline, an output shifting unit, a part and compression unit and a final reduction unit. According to the modular multiplier, an intermediate result of each round of iteration is expressed in a triple form, and the number of compression stages is reduced while long-bit-width addition is avoided. According to the method, shift operation is introduced, the quotient operation process is dispersed to a plurality of cycles for pipeline implementation, at the cost of introducing a plurality of additional cycles, the key path of each round of iteration is greatly shortened, the overall output delay of the modular multiplier is greatly reduced, the method is suitable for scenes with high-speed operation requirements, and the longer the modulus length is, the more obvious the acceleration effect is.

The invention relates to the technical field of integrated circuits, and discloses a parallel-serial conversion circuit. The parallel-serial conversion circuit comprises a parallel data storage unit, an odd-even data exchange unit, a shifting unit and a selection output unit, the parallel data storage unit is connected with a parallel data input end and a parallel clock signal end, and the odd-even data exchange unit is connected between the parallel data storage unit and the shifting unit. The data output module is used for directly outputting parallel data or performing odd-even data bit exchange on the parallel data according to a first selection control signal and then outputting the parallel data; the shifting unit is connected with the odd-even data exchange unit, the selection output unit and a serial clock signal end; and the selection output unit is connected with the shift unit, the serial clock signal input end and the serial data output end, and is used for sequentially and serially outputting each bit of data in the shift data along with the high and low levels of the serial clock signal. According to the technical scheme, the specific parallel-serial conversion mode can be dynamically configured, and the use flexibility of the I / O interface of the FPGA is improved.

A bit cell (100) is disclosed that includes a non-volatile memory element (110) and a transistor arrangement (120) configured to provide a write signal that switches a state of the memory element. A first terminal (111) of the memory element is connected to a bit line (BL), a second terminal (112) of the memory element is connected to a first common source / drain terminal (121) of the transistor arrangement, and a second common source / drain terminal (122) of the transistor arrangement is connected to a source line (SL). The transistor device includes a pair of stacked complementary transistors, where a gate (213) of an upper transistor is connected to a first word line (WLN), and where a gate (233) of a lower transistor is connected to a second word line (WLP). A memory device including an array of such bit cells, and a method for controlling bit cells are also disclosed.

An information processing apparatus includes: a solid state drive (SSD) configured with a multi-bit cell for storing multi-bit data in one memory cell and configured to include an electrically rewritable non-volatile storage unit; and a main control unit configured to execute processing based on data stored in the SSD. The SSD includes a storage control unit, which is a storage control unit configured to control access to the non-volatile storage unit, and configured to, when the multi-bit data is stored in the multi-bit cell, store the multi-bit data with a high-quality storage mode in which a variation width of a threshold voltage is narrower than in a normal storage mode when a number of rewrites executed in the multi-bit cell is equal to or greater than a threshold number of rewrites.

An integrated circuit includes a substrate; a bit cell array including bit cells on the substrate; a frontside wiring layer above the substrate in a vertical direction with respect to a front side of the substrate, the frontside wiring layer including local word lines connected to the bit cells; a row decoder configured to provide word line signals for driving the bit cell array; a backside wiring layer on a backside of the substrate, the backside wiring layer including backside wiring lines configured to receive the word line signals from the row decoder; and a word line rebuffer configured to provide the word line signals received from the backside wiring lines to the local word lines.

The embodiment of the invention provides a display device and a driving method thereof. The display device comprises N rows of pixel units and N levels of gate driving units, wherein the ith level of gate driving unit is electrically connected with a gate line of the ith row of pixel units. The ith-level gate driving unit comprises a pull-up unit and a reset unit, the pull-up unit is electrically connected with a first node, a gate driving signal output end and a level transmission signal output end, the reset unit comprises a first reset subunit and a second reset subunit, the first reset subunit is electrically connected with a first reset control signal line, and the second reset subunit is electrically connected with a second reset control signal line. The second reset subunit is electrically connected with a second reset control signal line. The first reset subunit and the second reset subunit are electrically connected with the first node, the gate drive signal output end and the level transmission signal output end. According to the display device provided by the embodiment of the invention, the charge emptying capability of the gate driving unit on the key node is enhanced, the working time of the thin film transistor is shortened, and the reliability of the gate driving unit is improved.

The application discloses a sensitive amplifier and a storage chip. The sensitive amplifier comprises a first clamping unit, a second clamping unit, a first current unit and a feedback unit. The control end of the first clamping unit is coupled with a total bit line through the feedback unit, so that the potential change of the total bit line forms a closed-loop control. That is, when the potential of the total bit line rises, the current flowing through the first current unit and the feedback unit is reduced, and the current flowing through the second clamping unit is increased. The potential of the control end of the first clamping unit is reduced, the current flowing through the first clamping unit is also reduced, and the potential of the total bit line is reduced to a preset potential and is kept stable. Conversely, the potential of the total bit line is increased to a preset potential and is kept stable.

A circuit includes a memory array including memory bit cells arranged in rows and columns. A row includes differential reference bit cells and single-ended bit cells, and the reference bit cells include a first set configured to store a first binary value and a second set configured to store a second binary value different from the first binary value. The circuit also includes a control module configured to generate a first reference current and to select the given row for a read operation. The circuit additionally includes an input / output module configured to compare a sensed current of a respective single-ended bit cell of the single-ended bit cells for the read operation to a second reference current. The second reference current is based on the first reference current and respective currents of the first set of reference bit cells and the second set of reference bit cells.

The invention provides a digital-to-analog converter device. A digital-to-analog converter apparatus includes: a set of components, each component included in the set of components including a plurality of unit cells, each unit cell being associated with a unit cell size representing a manufacturing specification of the unit cell; a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components; and an output electrode coupled to the plurality of switches, the converter device configured to output an output signal on the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different from a second unit cell size associated with a second unit cell included in the set of components.

Described herein is a read and write scheme to improve memory reliability. In at least one embodiment, one or more circuitries are provided to perform logic 0 write operation in a first phase and logic 1 write operation in a second phase for a plurality of bit-cells controlled by a word-line. In at least one embodiment, an individual bit-cell comprises a transistor having a gate terminal coupled to the word-line; and a capacitor including non-linear polar material, wherein the capacitor has a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein a source or drain terminal of the transistor is coupled to a bit-line.

The present disclosure provides a semiconductor structure comprising a substrate having a front side and a back side; an SRAM circuit having SRAM bit cells formed on a front side of the substrate, where each SRAM bit cell includes two inverters cross-coupled together, two write pass gates coupled to the two inverters, a read pull-down device coupled to the two inverters, and a read pass gate coupled to the read pull-down device, and wherein each SRAM bit cell is connected to the WBL, the WBLB, the RBL, the Vdd, and the Vss; a first subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the front side of the substrate to a first of the SRAM bit cells; a second subset of WBL, WBLB, RBL, Vdd, and Vss is connected from the backside of the substrate to the first SRAM bit cell.

A method includes causing a first information bit to be written into a first bit cell in a first plurality of bit cells as an original logic state of the first information bit. The method also includes causing a second information bit to be written into a second bit cell in a second plurality of bit cells as an original logic state of the second information bit. The method also includes causing a third information bit to be written into a third bit cell in a third plurality of bit cells as a logically complementary state of the first information bit.

An SRAM architecture is disclosed that provides a process- and temperature-compensated word-line underdrive scheme enabling stable, low-voltage operation. Each row decoder generates an initial word-line signal, derives an inverse word-line signal, and drives the corresponding word line through driver circuitry including a word-line underdrive p-channel transistor. The transistor's gate is controlled by the inverse word-line signal and optionally receives a dynamically generated negative bias to reduce device size while maintaining performance. Control circuitry includes a word-line underdrive sink circuit having dummy memory cells that replicate bit-cell behavior to generate a compensated driver output signal tracking process and temperature variations. A negative bump generator produces a transient below-ground potential at the gate node to enhance underdrive efficiency. This improves bit-cell stability, dynamic noise-margin yield, and performance uniformity across process corners and temperature, while minimizing silicon area.

Provided are an image sensor, and a method for operating same, the image sensor comprising a pixel array having a plurality of pixels, each pixel comprising: a SPAD for sensing photons and generating impulse signals; a counter for counting the number of pulse signals; a multiplexer for selecting, in accordance with a mode selection signal, one count bit cell among a plurality of count bit cells of the counter, and outputting an overflow signal based on the bit value of the selected count bit cell; and a front-end module for converting the impulse signals to pulse signals, and when the overflow signal is issued, converting global clock signals to pulse signals and transmitting to the counter. As such, light can be sensed with ultra-high precision at low power, and by varying the period to which extrapolation is applied, light can be sensed with adjustments to the level of precision.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a logic block and a p-bit block. The logic block includes a plurality of plurality of logic elements. The p-bit block includes a transistor, a first bit cell with a magnetic structure and at least one second bit cell with a resistance structure. The first bit cell with the magnetic structure is connected to one end of the transistor. The at least one second bit cell with the resistance structure is connected to another end of the transistor.

To provide a low-power, high-density, 1T-1C (one transistor and one capacitor) memory bit-cell.SOLUTION: The capacitor has a pillar structure, which comprises ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.SELECTED DRAWING: Figure 1C

The invention discloses a method, system and medium for a voltage clamping unit in a chip circuit, and belongs to the technical field of chip circuit protection, and the method comprises the steps: obtaining a maximum allowable voltage deviation window and a maximum allowable voltage rise rate of a target input / output pin of a chip, and constructing a target clamping characteristic parameter set; selecting a clamp sub-model based on the parameter set; adjusting capacitance matching unit parameters according to the equivalent input capacitance of the target pin by combining a support vector regression algorithm with a genetic algorithm; connecting a clamping model and injecting a test voltage waveform, and extracting clamping response time and clamping voltage to construct feedback characteristics; a mathematical model between the clamping response time and the delay gate series is generated through a symbol regression algorithm, and a control delay unit structure is corrected; according to the method, closed-loop adaptive adjustment of clamping parameters is realized, the transient interference suppression capability and clamping precision of the chip under high-frequency and low-voltage conditions are improved, and the method has good reliability and expandability.

The present disclosure relates to row-by-row tracking of reference generation for a memory device. The disclosure relates to a structure comprising a plurality of magnetic random access memory (MRAM) bit cells, the bit cells comprising a first circuit and a second circuit, the second circuit being connected to the same word line as the first circuit such that the second circuit is configured to be connected in parallel series to generate a reference resistance value for sensing.