572 results about "Bit cell" patented technology

An example embodiment of the present invention provides a semiconductor device including: an encoder configured to receive a plurality of bit data by dividing the plurality of bit data into first group data and second group data, the plurality of bit data being divided into 2-bit units, to delay the second group data for a first period, and to output the first group data and the delayed second group data; and an output driver configured to output the first group data and the delayed second group data together to an external semiconductor device.

Inrush current in a memory such as SRAM cache may be managed by using one or more integrated delay elements such as inverters, RC delay lines, and the like to significantly slow down power down signal propagation between memory instances in a memory array. The delay in some examples may be between memory instances, while in other examples the delay is also introduced between bitcell arrays within a memory instance. By staggering the power up times of interconnected or chained memory instances, inrush current when powering the memory instances on or resuming from an inactive state may be reduced.

Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a TCAM array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, weights in a weight matrix may be programmed in SRAMs of a TCAM bit cell array. Each SRAM may operate as a multiplier that performs a multiplication between the stored weight to an input activation value applied at a search line in the TCAM bit cell array. The two SRAMs within a TCAM bit cell may operate independently to receive independently two input activation values on their respective select lines, and to perform a multiplication operation with the stored weight in each respective SRAM.

An information processing apparatus includes: a solid state drive (SSD) configured with a multi-bit cell for storing multi-bit data in one memory cell and configured to include an electrically rewritable non-volatile storage unit; and a main control unit configured to execute processing based on data stored in the SSD. The SSD includes a storage control unit, which is a storage control unit configured to control access to the non-volatile storage unit, and configured to execute a storage process through which a variation width of a threshold voltage is changeable when the multi-bit data is stored in the multi-bit cell.

An integrated circuit includes first bit cells, second bit cells, and clock cells. Each of first bit cells is arranged in one of multiple first cell rows having a first row height. Each of the second bit cells is arranged in one of multiple second cells rows having a second row height different from the first row height. The second bit cells extend to pass the first bit cells in a first direction. The clock cells are arranged in peripheral regions of a multi-bit flip flop cell in the first cell rows. The first and second bit cells and the clock cells are included in the multi-bit flip flop cell.

A circuit includes a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit. The circuit includes a second plural number (S) of multiplexers operatively coupled to the scan chain, wherein the S is determined asNM,where the M represents a diagnostic resolution. The multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages.

A circuit includes a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit. The circuit includes a second plural number (S) of multiplexers operatively coupled to the scan chain, wherein the S is determined asNM,where the M represents a diagnostic resolution. The multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages.

A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.

The invention relates to hydraulic pump return plate machining equipment, and belongs to the technical field of machining. The equipment aims to solve the problems that in the prior art, a return plate is prone to deformation during machining, and grinding precision is insufficient. The equipment comprises a rack, a limiting unit, a lifting mechanism and a grinding mechanism. Wherein the limiting unit is matched with the limiting groove through a clamping assembly to limit horizontal and vertical movement of the blank piece; the grinding mechanism comprises a plurality of grinding execution units rotating synchronously, and precise machining of an inner cavity of the blank is achieved through a rotary grinding assembly. A positioning adjusting module of the clamping assembly is provided with an avoiding structure and can be matched with a to-be-machined hole site of the blank. The grinding execution unit adopts a reverse rotation design, so that the machining efficiency and precision are improved; in addition, the vertical movement of the grinding mechanism is accurately controlled through the lifting mechanism, and the equipment is suitable for machining blanks with different heights; the method has the advantages of high machining precision, wide application range, convenience in operation and the like.

An integrated circuit includes a first backside wiring layer arranged on a backside of a substrate, and an e-fuse bit cell. The e-fuse bit cell includes an e-fuse, a transistor arranged on a front side of the substrate, and a first backside contact passing through the substrate in a vertical direction and electrically connecting the e-fuse to the transistor. The e-fuse includes a first terminal electrically connected to a bit line, a second terminal electrically connected to the first backside contact, and a link between the first terminal and the second terminal, and the first terminal, the second terminal, and the link are included in the first backside wiring layer.

A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.

A memory device is provided. The memory device includes a compute-in-memory (CIM) array, capacitor circuit pairs, a first switch circuit and an analog-to-digital converter. The CIM array includes bit cells arranged in columns, in which the CIM array generates, in response to an input vector and a stored vector in the bit cells, accumulation results. The capacitor circuit pairs receive the accumulation results through bit lines, in which portions, in one of the columns, of the bit cells and a corresponding one of capacitor circuit pairs are coupled to a corresponding bit line of the bit lines. The first switch circuit is coupled to the capacitor circuit pairs is switched to generate, based on the accumulation results, weight mean results in one capacitor circuit in each of the plurality of capacitor circuit pairs. The analog-to-digital converter generates, according to the plurality of weight mean results, a multiply-and-accumulate result.

The invention relates to the field of electronic signal processing, in particular to the field of high-speed analog-to-digital converters, and discloses a high-speed ADC with error / edge detection and eye pattern monitoring functions. The ADC comprises a main channel and a reference channel, wherein the main channel comprises a source follower buffer and 16 time-interleaved 2-bit SAR ADC units; the reference channel comprises a source follower buffer with a small size and a plurality of SAR ADC units used for error detection, edge detection and eye pattern monitoring. The reference channel carries out real-time monitoring and dynamic calibration on the main channel according to a detection result, key performance indexes such as high-speed sampling rate, conversion precision and power consumption are effectively balanced, and an optimized ADC solution is provided for high-speed data link application.

An integrated circuit includes a one-time programmable (OTP) bit cell including a program transistor and a read transistor arranged on an active region extending on a front side of a substrate in a first direction, a first backside gate contact penetrating the substrate in a vertical direction and overlapped by the active region, a backside wiring layer arranged on a backside of the substrate and connected to a first gate of the program transistor via the first backside gate contact to transfer a program word line signal to the first gate, and a front side wiring layer arranged above the front side of the substrate and including a first front side wiring pattern connected to a second gate of the read transistor to transfer a read word line signal to the second gate.

A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.

A memory is provided that includes an analog gate voltage driver that drives the gate of a head switch transistor for a bitcell array with an analog gate voltage while the bitcell array operates in a light-sleep mode. The analog gate voltage switches the head switch transistor partially on so that the head switch transistor passes a reduced power supply voltage despite being powered by a memory power supply voltage that is greater than the reduced power supply voltage. The reduced power supply voltage has a sufficient magnitude so that the bitcell array retains its stored binary contents during the light-sleep mode.

The invention relates to a pixel driving circuit and a display panel, and relates to the technical field of display driving. The pixel driving circuit comprises a driving transistor, a write-in unit, a storage capacitor, a connecting unit, a reset unit and a light-emitting control unit. A first electrode of the driving transistor is connected with the connecting unit and the light-emitting control unit at a first node, a second electrode is connected with the writing unit and the light-emitting control unit at a second node, and a control electrode is connected with the connecting unit and the storage capacitor at a third node; the reset unit is connected with the storage capacitor and the anode of the light-emitting device; wherein the write-in unit is connected with the first driving unit; the connection unit and the reset unit are respectively connected with the second driving units of different levels; and the light-emitting control unit is connected with the third driving units of different levels. By resetting the second driving units of different levels and the third driving units of different levels, the total number of the required gate driving circuits is reduced, and the narrow frame design of the display panel can be realized.

The invention discloses a low-delay Montgomery modular multiplier. The modular multiplier comprises an iteration control unit, a parallel part and generation unit, a quotient operation unit of a multi-stage pipeline, an output shifting unit, a part and compression unit and a final reduction unit. According to the modular multiplier, an intermediate result of each round of iteration is expressed in a triple form, and the number of compression stages is reduced while long-bit-width addition is avoided. According to the method, shift operation is introduced, the quotient operation process is dispersed to a plurality of cycles for pipeline implementation, at the cost of introducing a plurality of additional cycles, the key path of each round of iteration is greatly shortened, the overall output delay of the modular multiplier is greatly reduced, the method is suitable for scenes with high-speed operation requirements, and the longer the modulus length is, the more obvious the acceleration effect is.

A memory device is provided, including at least one bit cell, a pair of transistors, and a voltage generation circuit. The voltage generation circuit is coupled to the negative voltage line and is configured to pull down a voltage of at least one of the pair of data lines to a negative voltage level through the negative voltage line. The voltage generation circuit includes a first capacitive unit, a second capacitive unit, and a switch circuit. The first capacitive unit includes a first capacitor. The second capacitive unit includes a second capacitor. The switch circuit is configured to connect the first capacitor, the second capacitor, or the combination thereof to the negative voltage line in response to a first kick signal and a second kick signal that are different from each other.

The invention relates to the technical field of integrated circuits, and discloses a parallel-serial conversion circuit. The parallel-serial conversion circuit comprises a parallel data storage unit, an odd-even data exchange unit, a shifting unit and a selection output unit, the parallel data storage unit is connected with a parallel data input end and a parallel clock signal end, and the odd-even data exchange unit is connected between the parallel data storage unit and the shifting unit. The data output module is used for directly outputting parallel data or performing odd-even data bit exchange on the parallel data according to a first selection control signal and then outputting the parallel data; the shifting unit is connected with the odd-even data exchange unit, the selection output unit and a serial clock signal end; and the selection output unit is connected with the shift unit, the serial clock signal input end and the serial data output end, and is used for sequentially and serially outputting each bit of data in the shift data along with the high and low levels of the serial clock signal. According to the technical scheme, the specific parallel-serial conversion mode can be dynamically configured, and the use flexibility of the I / O interface of the FPGA is improved.

A bit cell (100) is disclosed that includes a non-volatile memory element (110) and a transistor arrangement (120) configured to provide a write signal that switches a state of the memory element. A first terminal (111) of the memory element is connected to a bit line (BL), a second terminal (112) of the memory element is connected to a first common source / drain terminal (121) of the transistor arrangement, and a second common source / drain terminal (122) of the transistor arrangement is connected to a source line (SL). The transistor device includes a pair of stacked complementary transistors, where a gate (213) of an upper transistor is connected to a first word line (WLN), and where a gate (233) of a lower transistor is connected to a second word line (WLP). A memory device including an array of such bit cells, and a method for controlling bit cells are also disclosed.

A memory device including a substrate, a sense amplifier that includes first gate-all-around transistors that have first drain / source regions that extend into the substrate, and bit cells that include fuse memory elements and second gate-all-around transistors. Each of the bit cells includes a fuse memory element having a first terminal connected to an input of the sense amplifier and a second terminal connected to a second gate-all-around transistor that includes second drain / source regions and a bottom dielectric isolation layer under the second drain / source regions.

An information processing apparatus includes: a solid state drive (SSD) configured with a multi-bit cell for storing multi-bit data in one memory cell and configured to include an electrically rewritable non-volatile storage unit; and a main control unit configured to execute processing based on data stored in the SSD. The SSD includes a storage control unit, which is a storage control unit configured to control access to the non-volatile storage unit, and configured to, when the multi-bit data is stored in the multi-bit cell, store the multi-bit data with a high-quality storage mode in which a variation width of a threshold voltage is narrower than in a normal storage mode when a number of rewrites executed in the multi-bit cell is equal to or greater than a threshold number of rewrites.

An integrated circuit includes a substrate; a bit cell array including bit cells on the substrate; a frontside wiring layer above the substrate in a vertical direction with respect to a front side of the substrate, the frontside wiring layer including local word lines connected to the bit cells; a row decoder configured to provide word line signals for driving the bit cell array; a backside wiring layer on a backside of the substrate, the backside wiring layer including backside wiring lines configured to receive the word line signals from the row decoder; and a word line rebuffer configured to provide the word line signals received from the backside wiring lines to the local word lines.

The invention provides a data processing method of a magnetic random access memory. The data processing method comprises the following steps: acquiring to-be-written data and a write address of the to-be-written data in the magnetic random access memory; comparing the original data in the write address with the to-be-written data to obtain a comparison result; determining a bit cell of a to-be-changed numerical value based on a comparison result; dividing the to-be-written data into a plurality of first to-be-written data sets and a plurality of second to-be-written data sets; controlling the current direction of a first magnetic tunnel junction set corresponding to a bit unit to realize writing of data in at least one first to-be-written data set; reading data in the magnetic random access memory; and controlling the current direction of the second magnetic tunnel junction set corresponding to the bit unit to realize writing of data in the at least one second to-be-written data set. Therefore, the data reading efficiency of the magnetic random access memory can be improved.

Methods and systems which involve computer memories are disclosed herein. A disclosed multibit read only memory (ROM) includes a plurality of voltage generators for generating a plurality of voltages and a transistor having a first node and a second node. The transistor can be a field effect transistor (FET) and the first node can be a gate node and the second node can be a source or drain node. The ROM includes a connection from the first node to a first supply voltage node which is biased by one of the voltages in the plurality of voltages. The ROM includes a connection from the second node to a second supply voltage node which is biased by one of the voltages in the plurality of voltages. The value of a multibit ROM cell in the multibit ROM is stored as a resulting conductivity state of the transistor.

Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

The embodiment of the invention provides a display device and a driving method thereof. The display device comprises N rows of pixel units and N levels of gate driving units, wherein the ith level of gate driving unit is electrically connected with a gate line of the ith row of pixel units. The ith-level gate driving unit comprises a pull-up unit and a reset unit, the pull-up unit is electrically connected with a first node, a gate driving signal output end and a level transmission signal output end, the reset unit comprises a first reset subunit and a second reset subunit, the first reset subunit is electrically connected with a first reset control signal line, and the second reset subunit is electrically connected with a second reset control signal line. The second reset subunit is electrically connected with a second reset control signal line. The first reset subunit and the second reset subunit are electrically connected with the first node, the gate drive signal output end and the level transmission signal output end. According to the display device provided by the embodiment of the invention, the charge emptying capability of the gate driving unit on the key node is enhanced, the working time of the thin film transistor is shortened, and the reliability of the gate driving unit is improved.

A system and method for efficiently resetting data stored in a memory array is described. In various embodiments, an integrated circuit includes a memory for storing data and a processing unit for generating access requests for the data stored in the memory. When an access circuit of the memory array initiates a reset operation, it reduces a power supply voltage level used by memory bit cells in a column of the array to a value below the threshold voltage of the transistor. Thus, the p-type transistors of the bit cells do not contend with the write driver during a write operation. The access circuit provides reset data on the write bit lines and asserts each of the write word lines of the memory array. To complete the write operation, the access circuit returns the power supply voltage level from below the threshold voltage level to the operating voltage level.