1856 results about "Data bits" patented technology

Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.

Apparatuses, systems, and methods for separate write enable signals for granular single pass metadata access operations. During an example write operation a memory may receive data bits and at least one metadata bit. A set of bit lines in a first column plane is selected and a first write enable signal is provided which enables writing data to each of that set of bit lines. A second set of bit lines in a second column plane is selected and a second write enable signal is provided which enables writing the at least one metadata bit to a selected subset of the second set of bit lines.

The invention relates to the technical field of industrial robots, in particular to an industrial robot disordered grabbing system and method based on multi-modal sensing, and the system comprises a multi-modal sensing module, a pose estimation and correction module, a grabbing task planning module and a mechanical arm execution module. The multi-modal sensing module is used for acquiring RGB image data, depth image data, point cloud data and force / torque data in a working environment, and the pose estimation and correction module performs feature extraction and fusion on multi-modal data based on topology invariant mapping and performs adaptive pose estimation on a target object. The grabbing task planning module generates an optimal grabbing strategy based on deep reinforcement learning and outputs a grabbing control instruction, and the mechanical arm execution module receives the grabbing control instruction, controls a mechanical arm to execute a grabbing action and monitors a grabbing state through force / torque feedback. And the environmental adaptability and the perception robustness are improved.

The invention discloses a large language model acceleration system and method based on binary quantization, and the system comprises an extraction and quantization unit, a grouping packaging and splicing unit, an operation realization unit, and an inverse quantization and output unit, and comprises the specific steps: extracting parameters needing matrix / vector multiplication in a model; performing binary quantization processing on parameters of the model matrix / vector multiplication operation; splicing the grouped binary quantized parameters into single integer data bit by bit according to an order when matrix / vector multiplication is calculated by adopting a grouping and packaging algorithm; matrix / vector multiplication which is equivalent to original model reasoning and is friendly to hardware is executed; the result is converted back to the floating point data type through an inverse quantization algorithm, a final calculation result of the large language model in the matrix / vector multiplication operation is obtained, the final calculation result is transmitted into a subsequent network layer, and calculation acceleration for the matrix / vector multiplication operation in the large language model is completed. According to the method, the accuracy is ensured, and meanwhile, the speed is increased during large language model reasoning.

The invention discloses a data processing system and method, electronic equipment and a storage medium, and relates to the technical field of computers.Original input data are preprocessed into multiple sets of target input data through a data input module, and the multiple sets of target input data are input into multiple iterative calculation units to obtain data to be calculated and code identifiers; when the code identifier represents that the to-be-calculated data needs to be overturned in advance, the to-be-calculated data is overturned in advance to obtain the to-be-calculated inverted data, and a subsequent iterative calculation unit only needs to perform target calculation on the to-be-calculated inverted data to obtain a data processing result; that is, the iterative calculation unit can obtain the data processing result only by performing a small amount of data bit flipping on the to-be-calculated inverted data through the target calculation, the number of data bit flipping in the target calculation is reduced, the dynamic flipping power consumption is reduced, and compared with a power consumption reduction mode in the related technology, the efficiency is improved. High-difficulty chip rear end layout wiring is not needed, and the performance and the power consumption reduction effect of the chip can be ensured.

The present invention relates to a system for implementing large-scale FIFO data processing based on DDR, comprises ingress asynchronous clock domain FIFO; burst read and write data block chain table, for writing data block chaining table and reading data block chaining table by setting of data bit width and data block length; DDR4 AXI interface for interacting with the flow control state machine and the burst read and write chain table; egress asynchronous clock domain FIFO; flow control state machine, used for data flow control to monitor writes and reads of data streams to the ingress asynchronous clock domain FIFO, DDR4 AXI interface and egress asynchronous clock domain FIFO. The present invention also relates to a method for implementing DDR-based large-scale FIFO data processing using DDR. By adopting the system, method, device, processor and its computer-readable storage medium for implementing large-scale FIFO data processing based on DDR of the present invention, the time utilization rate is improved, the data acquisition efficiency is effectively improved, and the FIFO storage depth is increased to ensure continuous data acquisition for a longer period of time.

The invention relates to the technical field of slope disaster monitoring, particularly provides a slope landslide geological disaster monitoring method and system based on image intelligent identification, and solves the problems that image identification and hyperspectral analysis are depended, multi-modal data fusion is lacked, and the monitoring accuracy is high. The method comprises the following steps: acquiring multi-modal data through an unmanned aerial vehicle hyperspectral camera, a ground image sensor, a vibration sensor, a displacement sensor and a meteorological sensor; carrying out denoising, calibration and formatting processing on the acquired multi-modal data; extracting landslide related features from the image data, the hyperspectral data, the vibration data, the displacement data and the meteorological data; fusing the multi-modal data through an intelligent fusion algorithm to generate a landslide risk assessment result; and early warning information is generated according to a landslide risk assessment result, and an emergency response mechanism is triggered, so that the precision and efficiency of image recognition and hyperspectral data analysis are improved, and the real-time performance and response speed of the system are improved.

The embodiment of the invention provides a data tracking circuit, a data tracking processing method, a chip and electronic equipment, the data tracking circuit comprises a selection module and a packaging engine module, tracking source data is received and selected to be output as tracking data through the selection module, the packaging engine module packages the tracking data to generate corresponding data frames, and the corresponding data frames are stored in the storage module. The data frames comprise the identifiers used for identifying the types of the data frames, the larger the number of the data frames of the same type is, the shorter the data bit width of the identifiers of the data frames of the type is, compared with identifiers of fixed lengths, the lengths of most identifiers can be shortened, the data size of the data frames is reduced on the whole, and the data transmission efficiency is improved. And thus, the bandwidth required by the packaged data frame is also reduced.

Systems and methods include receiving data bits at an input pin of a semiconductor device from a host device. The received data is latched in latch circuitries of the semiconductor device that at least partially implements an equalizer to aid in interpreting the received data bits. A first latched bit latched from the first received bit of the received bits is transmitted from the latch circuitries to self-calibration circuitry. The first received bit is also latched in error evaluation circuitry as a second latched bit. The second latched bit is transmitted from the error evaluation circuitry to the self-calibration circuitry. The self-calibration circuitry determines settings for the equalizer without involving the host device in determining the settings after the host device sends the data bits.

A method and apparatus are provided for processing a GNSS signal received at a receiver. The method comprises mixing a local carrier signal with samples of the GNSS signal to generate carrier-free signal samples. It further comprises: correlating the carrier-free signal samples with a local spreading code to generate a complex-valued correlation result; and wiping off at least one of the data bits from the complex-valued correlation result, to produce a data-free complex-valued correlation result. A carrier phase of the local carrier signal is controlled based on a Doppler estimate for the GNSS signal, wherein the Doppler estimate is based at least in part on inertial measurements made at the receiver.

Certain aspects of the present disclosure generally relate to techniques for selecting a base graph to be used for wireless communications. Selection can be based on a variety of factors. A base graph can be used to derive a low-density parity-check (LDPC) code used for encoding a retransmission of an original transmission. An exemplary method generally includes selecting, based on a modulation and coding scheme (MCS) and a resource allocation (RA) for transmitting a codeword, a base graph (BG), from which to derive a low density parity check (LDPC) code for use in encoding data bits in the codeword (e.g., encoding data bits of a bitstream such that some redundant bits are included in the codeword), encoding the data bits to generate the codeword using the LDPC code derived from the selected BG, and transmitting the codeword using the MCS via resources of the RA.

The present invention discloses a method and device for transmitting network time synchronization messages applicable to any channel environment, including: classifying the data bits of the time synchronization messages to be transmitted to obtain public information bits and secret information bits, and performing Polar coding on the data of the time synchronization messages to obtain a first coding sequence; dividing all data subcarriers within the transmission bandwidth into sub-blocks according to the number of legitimate receivers, and dividing each sub-block to obtain clusters, performing IM modulation on each cluster to determine the active subcarrier indices of each cluster; interleaving the symbol vector obtained by modulating the first coding sequence based on the total frequency-domain channel matrix characteristics of a preset channel simulation system; modulating the interleaved symbol vector onto the active subcarriers selected for each sub-block to complete OFDM-IM modulation, and sending the modulated OFDM-IM signal to each legitimate receiver. The present invention solves the problems of poor security and limited application scenarios in the transmission of network time synchronization messages.

The invention relates to the technical field of large-scale data management, in particular to a data storage method and system based on a large model, and the method comprises the following steps: collecting multiple items of data in a large model data set, recording the occurrence frequency of each type of data, calculating the entropy value of each type of data, determining the volatility and diversity of the data, and generating an entropy value calculation result. According to the method, the data are sorted and stored in a classified mode according to the entropy values, so that the high-entropy-value data are located in a high-density storage area, the low-entropy-value data are stored in a low-density area, the utilization rate of the storage space is optimized, unnecessary storage cost is reduced, stratum superposition is simulated according to hierarchical storage of the data and sorting of time stamps, and the data storage efficiency is improved. The storage structure is optimized, rapid positioning and access of new data are also facilitated, adjustment of data compression and storage parameters simulates the geologic stratum compaction process, the storage capacity is effectively managed, the energy efficiency of a data center is enhanced, and the response capability to a complex data environment is enhanced.

The invention relates to the technical field of computer hardware and network communication, in particular to a high-speed I / O (input / output) virtualization server based on an FPGA (field programmable gate array) and a remote forwarding method.The high-speed I / O virtualization server comprises an FPGA chip, a network processing unit, an I / O protocol processing unit, a protocol conversion and scheduling unit, a time sequence and transaction management unit and a data buffering and flow control unit are integrated in the FPGA chip; the optical fiber Ethernet interface module comprises a physical layer interface and an MAC layer processing and network configuration interface; the local I / O interface module comprises a USB interface circuit, a serial port interface circuit, a PCIe interface circuit and an interface expansion connector; the power supply and monitoring module comprises a multi-path power supply management system, a state monitoring and diagnosis system and an LED indication system; according to the self-adaptive Baud rate detection circuit, the Baud rate can be accurately locked under the condition that data with less than two characters is received, the number of data bits, the type of a check bit and the length of a stop bit are automatically identified, and compared with a traditional microcontroller scheme, the self-adaptive Baud rate detection circuit has higher precision and higher detection speed.

An electronic device may include a reception circuit configured to generate a plurality of reception data bits based on a voltage level of an analog signal received through a link, and to generate a plurality of bit reliability values indicating probabilities of error occurrence of the plurality of reception data bits based on the voltage level of the analog signal, an alignment circuit configured to group the plurality of reception data bits into a plurality of error correction code (ECC) symbols, and to generate a plurality of symbol reliability values indicating probabilities of error occurrence of the plurality of ECC symbols based on the plurality of bit reliability values, and a decoding circuit configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.

The invention provides a downlink data transmission method, device and system for laser fiber power supply application, and the method comprises the steps: carrying out the differential coding of downlink data to be transmitted through a transmitting end, and obtaining a data bit sequence; mapping the data bit sequence into a modulation symbol sequence by adopting a single-carrier phase modulation mode; performing digital-to-analog conversion on the modulation symbol sequence to obtain an analog signal; and outputting downlink energy and downlink data through an energy optical fiber according to the analog signal. According to the invention, the signal frequency spectrum is moved to be far away from the direct current frequency through differential coding and single carrier phase modulation, so that the interference of direct current laser energy on signal detection is minimized, the signal-to-noise ratio is improved, the inter-symbol interference is reduced, and a receiving end is ensured to have enough signal-to-noise ratio to reliably detect data.

The invention discloses a robot track online compensation and precision control method and system based on multiple sensors, and belongs to the technical field of robot track control. The method comprises the following steps: acquiring target trajectory data and original data of each sensor, and performing time alignment on the original data of each sensor to generate a fusion data set comprising vibration acceleration data and pose data; performing time-frequency feature extraction based on the vibration acceleration data to obtain a dominant vibration frequency spectrum; constructing a mechanical transfer function model of the joint driving torque and the tail end vibration displacement; based on the mechanical transfer function model, constructing an adaptive notch filter to generate a feed-forward compensation sequence; according to the target trajectory data, the pose data and weight parameters, updated in real time, of the sensors, a trajectory fusion deviation value is obtained through calculation; and after the feedforward compensation sequence and the trajectory fusion deviation value are integrated, a joint driving current instruction is generated based on a fuzzy PID control algorithm. The robot trajectory control precision can be improved.

The invention provides an anti-interference serial port communication method and system for an industrial-grade wireless module, and the method comprises the steps: collecting interference data in the serial port communication of the industrial-grade wireless module in real time based on a multi-dimensional interference feature collection module, and forming a multi-scale interference feature vector; inputting the multi-scale interference feature vector into a Mamba communication state space model fused with a CRC (Cyclic Redundancy Check) mechanism, and predicting a potential interference mode through linear complexity time sequence modeling; based on an adaptive weight transmission optimization function, carrying out dynamic weighting adjustment on the transmission parameters in the potential interference mode; wherein the transmission parameters comprise a baud rate, a data bit length, a verification mode and a retransmission strategy. According to the invention, hardware cost does not need to be increased, and the cost of anti-interference serial port communication is reduced; meanwhile, based on an adaptive weight transmission optimization function, dynamic weighting adjustment is carried out on transmission parameters in a potential interference mode, and interference dynamic changes are tracked in real time to carry out anti-interference communication.

A method and apparatus are provided for processing a GNSS signal received at a receiver. The method comprises mixing a local carrier signal with samples of the GNSS signal to generate carrier-free signal samples. It further comprises: correlating the carrier-free signal samples with a local spreading code to generate a complex-valued correlation result; and wiping off at least one of the data bits from the complex-valued correlation result, to produce a data-free complex-valued correlation result. A carrier phase of the local carrier signal is controlled based on a Doppler estimate for the GNSS signal, wherein the Doppler estimate is based at least in part on inertial measurements made at the receiver.

The invention discloses a serial port communication transmission method and system with high baud rate tolerance. The method comprises the following steps: S1, monitoring a serial port communication line until a level change from logic '1' to logic '0' is detected, and detecting a start bit of a data frame through a triple acknowledgement mechanism; s2, after the transmission of the data bits and the optional parity check bits is completed, continuously monitoring the serial port communication line until the level change from the logic '0' to the logic '1' is detected, and confirming a stop bit for detecting a data frame through triple sampling; and S3, after the stop bit of the data frame is ended, returning to the step S1 to detect the start bit of the next frame of data. According to the invention, by adopting a triple acknowledgement mechanism and a triple sampling acknowledgement method, the start bit and the stop bit of the data frame can be accurately detected, accurate receiving of data can be kept even under the conditions of Baud rate change and noise interference, and an efficient and reliable serial port communication solution is provided for users.

The invention provides a model training method and device, equipment and a storage medium, and relates to the technical field of computers, in particular to the technical field of neural network models and model training. The specific implementation scheme is as follows: a calculation unit executes quantization matrix multiplication based on Hadamard pre-transformation on an activation tensor and a weight tensor of a target model stored in a memory so as to generate an output tensor of a linear layer based on a low-precision tensor with smaller data bit width; using the output tensor and a subsequent network layer of the target model to complete forward propagation so as to obtain a loss value; and according to the loss value, updating model parameters of the target model stored in a memory through a back propagation algorithm. By means of the technical scheme, on the premise that the model training precision is guaranteed, memory resource occupation and the calculation amount in the calculation process can be remarkably reduced, and the training cost is reduced.

An apparatus comprises a storage configured to store data items associated with error correction codes (ECCs); data retrieval circuitry responsive to a data retrieval request specifying a retrieval address to retrieve a retrieved data item and an associated ECC from a storage location corresponding to the retrieval address; and ECC decoding circuitry to generate a syndrome value by performing an ECC decoding operation on a decoding input value comprising data bits of the retrieved data item, code bits of the associated ECC, and address bits of the retrieval address, and to determine based on the syndrome value whether an error condition has occurred. Each bit of the syndrome value depends on a different combination of bits of the decoding input value. For each data bit of the decoding input value, an odd number of bits of the syndrome value depend on that data bit. For each address bit of the decoding input value, an even number of bits of the syndrome value depend on that address bit.

The invention provides a system memory management unit configuration method and device, electronic equipment and a computer readable storage medium, and the method comprises the steps: distributing corresponding external equipment for each virtual machine according to a preset configuration file, and storing the external equipment in a preset table recording the information of the external equipment; acquiring a numerical value of a first specified data bit of a table item corresponding to the distributed external equipment, before the virtual machine is started, setting the numerical value of the first specified data bit as a preset value, and after the virtual machine is started, adjusting the numerical value of the first specified data bit as a first numerical value, the method comprises the following steps: when a virtual machine accesses a memory through an input operation of an external device, obtaining a physical address of the input operation, obtaining a target memory address matched with the physical address of the input operation from a corresponding relationship between the physical address recorded in a page table corresponding to the virtual machine to which the external device belongs and the memory address, and according to the target memory address, storing the target memory address in the external device; and the memory is accessed by the input operation, so that the probability of unsafe memory access is reduced.

Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of memory blocks, each including a plurality of memory cells configured to store data, and a memory controller in communication with the memory device and configured to 1) determine a write mode of a memory block of the memory device to be either a first write mode in which one data bit is stored in a memory cell of a memory block or a second write mode in which a plurality of data bits is stored in a memory cell based on a temperature of the storage device and a number of read reclaim operations that have been performed in the memory block and 2) control the memory device to perform a write operation in the determined write mode.

A method of model training is disclosed. The method includes: obtaining a second embedding vector input to a decoder in a pre-trained language model, where the second embedding vector corresponds to a second data sequence. The second data sequence includes first sub-data, a masked to-be-predicted data unit, and second sub-data. The first sub-data is located before the masked to-be-predicted data unit in the second data sequence, and the second sub-data is located after the masked to-be-predicted data unit in the second data sequence. The method further includes: obtaining a hidden state based on a first embedding vector by using an encoder in the pre-trained language model (PLM); and predicting the masked to-be-predicted data unit based on the first sub-data, the second sub-data, and the hidden state by using the decoder in the PLM and an output layer of the decoder.

The embodiment of the invention provides a data processing method and a data processing device, relates to the technical field of chips, and solves the problem of low performance of a processor. According to the specific scheme, a processor core obtains input data of a target function through an input interface; the processor core determines polynomial coefficients corresponding to the input data based on the first index and the second index. And the processor core performs polynomial calculation based on the data bits and the polynomial coefficients to obtain output data of the target function, and outputs the output data of the target function through the output interface. The embodiment of the invention is used for the calculation process of the target function.

The invention provides a weight quantification method and device based on mixed segment coding and a server, and relates to the technical field of artificial intelligence, and the method comprises the steps: obtaining a to-be-processed floating point weight and an activation value; based on the Laplacian distribution of the floating point weights, carrying out hybrid segmented coding processing on the floating point weights to obtain a coding weight set in a quantization weight coding format; and determining a multiplication coefficient and a shift value of the coding weight based on the identification bit, and carrying out multiplication and addition calculation processing on the activation value and the weight information in the data bit based on the multiplication coefficient and the shift value to obtain an output activation value corresponding to the coding weight. According to the method, the quantization precision of the neural network can be remarkably improved, and the quantization error is reduced while the compression ratio is not changed.

Disclosed is a system that streams true three-dimensional (“3D”) image data over a data network in a manner that preserves the dimensionality and detail of a dynamic and changing 3D scene. The system generates the 3D image data to represent the 3D scene, and streams different set of the 3D image data that are within different viewing frustums requested by different devices. The system generates updates to the 3D image data based on changes occurring at different parts of the 3D scene. The system streams a first update to the first device in response to image data updated by the first update being within the first device's viewing frustum, and streams a second update to the second device in response to image data updated by the second update being within the second device's viewing frustum.

A decoding method, a data processing method, an information generation method, a mobile terminal, a control terminal, an electronic system, and a non-transitory computer-readable storage medium are provided. The decoding method includes: parsing combined data that is received, the combined data being data obtained by combining image data captured by a mobile terminal and mobile terminal information corresponding to the mobile terminal; and in response to obtaining, by the parsing, an extended data bit string corresponding to the mobile terminal information, parsing extended data encoding information corresponding to the mobile terminal information from the combined data, and decoding the extended data encoding information to obtain the mobile terminal information.

The embodiment of the invention provides an embedded AI power grid waveform dynamic bit width adaptive preprocessing method and system and a medium, and the method comprises the steps: obtaining the real-time sampling data of voltage and current, and analyzing the sampling precision of the real-time sampling data; setting a sampling precision threshold, and judging whether the sampling precision is greater than the sampling precision threshold; if the sampling precision is greater than the sampling precision threshold value, performing Q-format fixed-point number conversion on the real-time sampling data, and performing normalization processing on the real-time sampling data after the Q-format fixed-point number conversion; if the real-time sampling data is smaller than or equal to the real-time sampling data, converting the real-time sampling data into normalization by adopting an LUT table look-up method; normalized sampling data is input into a quantitative model, data bit width is output, a bit width adjustment strategy is generated based on a set bit width threshold value, the data bit width is dynamically adjusted, the data preprocessing efficiency is improved through Q format fixed-point and LUT lookup methods, memory occupation is reduced, and self-adaptive preprocessing can be conducted according to collected signals of different bit widths.