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1235 results about "Data bits" patented technology

Data bits. The number of bits used to represent one character of data. When transmitting ASCII text via modem, either seven or eight bits may be used.

Adaptive power control based on a rake receiver configuration in wideband CDMA cellular systems (WCDMA) and methods of operation

A WCDMA system includes a Base Station (BS) or forward transmitter and a pilot channel that transmits control signals between a Mobile Station (MS) and BS to reconfigure their transmitter/receiver according to the prediction of the channel power and channel power probability density function separated into three distinct equal probable regions. Data signals are encoded using a one-half Viterbi encoder and interleaved. The interleaved data bits are modulated using Quadrature Phase Shift Keying (QPSK) modulation. The QPSK data is multiplexed with the pilot channel and spread by an appropriate code in an OFDM transmitter modified by a long code. Output of the transmitter may be provided to two diverse antennas for reliable communications to the receiver. Data may be received at two diverse antennas. The outputs are provided to match filters coupled to a coherent rake receiver and a channel prediction system. The future attenuation of the channel coefficients and power are determined by the prediction system for several milliseconds. The power levels of each finger in the Rake receiver can be predicted and the strongest ones used in determining the optimum transmitter power or rate control for operating the system transmitters and receivers based on computing a long range power prediction of each finger of a rake receiver.

Scoreboarding for DRAM access within a multi-array DRAM device using simultaneous activate and read/write accesses

A method and apparatus for performing memory array/row scoreboarding in a dynamic access memory (DRAM) having dual bank access. The DRAM of the present invention allows dual simultaneous memory accesses into a memory divided into a plurality of arrays (e.g., 48 arrays). Each array of the DRAM contains a plurality of rows (e.g., 256). Each row of the DRAM contains storage for a certain amount of data bits (e.g., 1024). The DRAM in one configuration contains 1.5 Megabytes of memory. During a dual bank DRAM access, the system allows a first access for pre-opening a row (e.g., a page) of DRAM memory within a first array while simultaneously allowing a second access for reading/writing data to an opened row of another array aside from the first array. The present invention scoreboarding system tracks the rows that are currently open so that immediate read/write accesses can take place. Upon presentation of a row and array, the scoreboard determines if the presented row is currently open, and if so, generates a hit signal that allows an immediate read/write access to the presented row. If the presented row is not open, the present invention generates a miss signal so that the row can be immediately opened before access is allowed. The scoreboard contains a memory unit containing row information for each array in the DRAM. The scoreboard, in addition to other novel features, allows an efficient DRAM configuration allowing dual memory accesses per cycle.
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