1235 results about "Data bits" patented technology

Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2^M−1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.

A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.

A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

A WCDMA system includes a Base Station (BS) or forward transmitter and a pilot channel that transmits control signals between a Mobile Station (MS) and BS to reconfigure their transmitter/receiver according to the prediction of the channel power and channel power probability density function separated into three distinct equal probable regions. Data signals are encoded using a one-half Viterbi encoder and interleaved. The interleaved data bits are modulated using Quadrature Phase Shift Keying (QPSK) modulation. The QPSK data is multiplexed with the pilot channel and spread by an appropriate code in an OFDM transmitter modified by a long code. Output of the transmitter may be provided to two diverse antennas for reliable communications to the receiver. Data may be received at two diverse antennas. The outputs are provided to match filters coupled to a coherent rake receiver and a channel prediction system. The future attenuation of the channel coefficients and power are determined by the prediction system for several milliseconds. The power levels of each finger in the Rake receiver can be predicted and the strongest ones used in determining the optimum transmitter power or rate control for operating the system transmitters and receivers based on computing a long range power prediction of each finger of a rake receiver.

A memory module for attachment to a computer system having a memory bus and a method of using the memory module for error correction by scrubbing soft errors on-board the module is provided. The module includes a printed circuit card with memory storage chips on the card to store data bits and associated ECC check bits. Tabs are provided on the circuit card to couple the card to the memory bus of the computer system. Logic circuitry selectively operatively connects and disconnects the memory chip and the memory bus. A signal processor is connected in circuit relationship with the memory chips. The logic circuitry selectively permits the signal processor to read the stored data bits and associated check bits from the memory chips, recalculate the check bits from the read stored data bits, compare the recalculated check bits with the stored check bits, correct all at least one bit errors in the store data bits and stored associated check bits and re-store the correct data bits and associated check bits in the memory chips. When the memory chips and the memory bus are disconnected, single bit soft errors occurring during storage of the data bits and check bits are corrected periodically before the data is read from the memory chips to the data bus on a read operation.

A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.

The present invention relates to methods, apparatuses, and systems for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits processing the outer encoded bits using an interleaver and a logical unit to produce intermediate bits, wherein the logical unit receives a first number of input bits and produces a second number of corresponding output bits, the second number being less than the first number, and wherein the logical unit takes each of the first number of input bits into account in producing the second number of output bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, wherein the inner convolutional code is characterized by at least two states, and combining the data bits and the inner encoded bits to produce encoded outputs.

A forward link device of a multicarrier CDMA communication system with an overlay scheme in which a multicarrier system and an IS-95 system share same frequency bands. In the forward link device, four encoders encode input data of corresponding rates with a 1/3 coding rate, respectively. A first repeater repeats two times full rate symbols output from the first encoder, and second to fourth repeaters repeat symbols output from the second to fourth encoders, respectively, according to a predetermined number of times, to match the number of corresponding output symbols to the number of full rate symbols. First to fourth interleavers interleave the symbols output from the first to fourth repeaters, respectively, to uniformly distribute the symbols of the same data bit to the carriers.

A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.

A method and apparatus for transmitting uplink acknowledge information (ACK) in a communication system using an orthogonal frequency division multiple access (OFDMA) scheme. The method includes receiving a data bit for the uplink ACK; outputting codewords corresponding to the data bit; performing quadrature phase shift keying (QPSK) modulation on symbols for ACK vector indexes corresponding to the codewords for the received data bit; performing inverse fast Fourier transform (IFFT) on a transmission signal having subcarrier clusters to which the modulated transmission symbols are allocated; and transmitting the IFFT-processed transmission signal.

In transmitter apparatus for a digital television (DTV) broadcasting system, internet-protocol (IP) packets of digital television information are subjected to multilevel concatenated Bose-Chaudhuri-Hocquenghem (BCH) coding and low-density parity-check convolutional coding (LDPCCC) before being bit-interleaved and mapped to quadrature-amplitude-modulation (QAM) constellations. The QAM constellations are used in coded orthogonal frequency-division modulation (COFDM) of plural carrier waves up-converted to a radio-frequency broadcast television channel. In receiver apparatus for the DTV broadcasting system the results of de-mapping QAM constellations recovered from demodulating the COFDM carrier waves are de-interleaved, and the constituent LDPCCC codewords are decoded to recover constituent BCH codewords of the multilevel BCH coding. The constituent BCH codewords are decoded to correct remnant bit errors in them. Then, IP packets of digital television information are reconstituted from the systematic data bits in those BCH codewords.

A method for improving a cooperation between a packetized data bit-rate adaptation and a data packet re-transmission transmits data packets from a server to a client with a first bit-rate; stores transmitted data packets in a server buffer; stores transmitted data packets in a client buffer; signals impairment information related to an impairment of transmitted data packets during transmitting to the server, wherein the signaled impairment information is analyzed by the server to decide if a re-transmission of data packets stored in the server buffer is required; and signals client buffer information related to a state of the client buffer to the server, wherein the client buffer information is analyzed by the server to decide if a re-transmission of data packets is required.

Systems, methods, and devices for managing endian-ness are disclosed. In one embodiment, a device is configured to selectively operate in one of a big-endian operating mode or a little-endian operating mode. The device may include a register in which the current endian mode of the device is indicated in at least two different bit positions within the register. The at least two different bit positions may be chosen such that a data bit in one of the bit positions would be read by a system if the device and system operate in the same endian mode, while a data bit in another of the chosen bit positions would be read by the system if the device and system are operating in different endian modes from one another. In some embodiments, the endian mode of the device may be controlled by a hardware input or a software input.

A disk drive includes a sampled servo controller for periodically adjusting a control effort signal during a track-following operation based on embedded distributed position information and repeatable runout (RRO) cancellation values for reducing effects of RRO in the distributed position information during track following. A magnetic disk in the disk drive stores RRO information relating to predetermined RRO cancellation values for a data storage track. The RRO information for the data storage track includes at least one first data structure having a first predetermined number of data bits for representing an initial RRO cancellation value, and includes at least one second data structure having a second predetermined number of data bits associated with a respective subsequent RRO cancellation value. The first predetermined number of data bits is greater than the second predetermined number of data bits.

A payment card comprises a plastic card with a magnetic stripe for user account data. Internal to the plastic card, and behind the magnetic stripe, a number of fixed-position magnetic write heads allow the user account data to be automatically modified. For example, a data field that counts the number of times the card has been scanned is incremented. A payment processing center keeps track of this usage-counter data field, and will not authorize transaction requests that come out of sequence. For example, as can occur from a magnetic clone of a card that has been skimmed and tried later. A card-swipe detector embedded in the plastic card detects each use in a scanner, and it signals an internal microcomputer which changes data bits sent to the write heads. Once scanned, the payment card can also disable any reading of the user account data for a short fixed period of time.

A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. In another aspect, a system differentiates between data bits based on their estimated reliability, giving more emphasis to decoding reliable bits than unreliable bits using any of a variety of techniques. By differentiating between god and bad bits and de-emphasizing or ignoring unreliable bits, the system can provide a significant reduction in uncorrectable errors and packet loss.

A data processing device transmits the data bits on the predetermined quantity carrying wave signal of the OFDM sign. The data processing device comprises a parity interweaver for operating the pairs of LDPC coding data. The data bits are obtained by the parity matrix LDPC detecting with the LDPC code. The parity matrix has a ladder-type structure interweaving the LDPC code data to the different parity bit position. The mapping unit maps the parity interweaving bit to the data signs corresponding to the modulating signs of the solution. The sign interweaver reads the quantity signs to the sign interweaving store, carrying out the data sig of the sign interweaving store reading the order with different reading; the order address set is confirmed. The address set is generated by the address generator.

A bit patterned magnetic recording medium for use in HAMR, which is optimized for optical coupling efficiencies and improved magnetic read-back coupling. The medium comprises bit-patterned magnetic recording elements, each corresponding to a magnetic data bit, and each comprising a cluster of discrete and separated magnetic grains. The desired packing fraction may be obtained by defining the number of grains within a bit, while bit-patterning provides efficient optical transmission. The grains have an effective packing fraction that enhances magnetic read-back signals, and the bits are distributed in a pattern having a packing fraction that enhances the optical coupling efficiency. The bits and/or the grains may be substantially thermally and optically isolated.

The present invention relates to a merging network for multiple data streams comprising a pipelined butterfly network. The pipelined butterfly network comprises an input network for receiving a plurality of data streams of mutually constant widths, each data stream having logically related data bits carried on contiguous signal lines, a butterfly network containing suitably interconnected register and multiplexer means for rearranging the received data streams into a time-multiplexed constant-width output data stream, the output data stream having a width equal to or greater than the sum of the widths of the input data streams, and an output network for providing the output data stream interleaved to an output bus.

Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices in combination with a stored record of known flaws, errors, or questionable data bits of a read memory row or block to allow for more efficient processing and correction of these errors. An embodiment of the present invention utilizes an erasure pointer that can store the location of N bad or questionable bits in the memory segment that is currently being read, where for each bit stored by the erasure pointer the embodiment also contains 2^N ECC generators to allow the read data to be quickly checked with the know bad bits in each possible state. This allows the read data to then be easily corrected on the fly before it is transferred by selecting the bad bit state indicated by the ECC generator detecting an uncorrupted read.

A Global Navigation Satellite System (GNSS) receiver and associated method capable of tracking weak GNSS signals from a plurality of GNSS satellites. In a preferred embodiment, code and carrier tracking loops are initially closed around the code phase, carrier frequency, and data bit edge estimates handed over from an acquisition mode. In subsequent tracking, early, prompt, and late copies of the code replica are correlated with the incoming signal. The prompt correlations are coherently integrated over an extended updating interval for data bit edge and sign estimation as well as for carrier phase and frequency error discrimination whereas the early and late correlations are used for code error discrimination. Code delay and carrier phase and frequency errors are used to update the code and carrier tracking loop filters. Together with data bits, they form observables of a GNSS signal's time and frequency parameters for timing and position fixing.

Data input and output circuits that support multi data rate and a number of timing schemes. In one design, a data output circuit includes an input multiplexer, data latches, an output multiplexer, and at least one output driver. The input multiplexer receives a set of data bits in a first order (e.g., odd and even) and provides the data bits in a second order (e.g., first and second). The data latches can latch the data bits with (1) a latch signal to satisfy memory access timing requirements and (2) a data write clock signal to satisfy output timing requirements. The output multiplexer multiplexes the latched data bits to provide time multiplexed data bits. The output driver(s) provide signal drive for the time multiplexed data bits. Clock signals with various timing characteristics can be used to allow the data output circuit to satisfy various timing requirements.

Methods of operating nonvolatile memory devices include testing a plurality of strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other ones of the plurality of strings. An identity of the at least one weak string may be stored as weak column information. This weak column information may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on a first plurality of bits of data read from the plurality of strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the first plurality of bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the first plurality of data bits.

The invention discloses a speed matching method of the limited-length circular cache of a low-density parity-check code. The method includes the following steps of conducting a structured low-density parity-check code encoding on the data bit of an inputted information block, and determining the size of the one-dimensional limited-length circular cache according to the encoding result; selecting a redundant version value from a plurality of preset redundant version values according to the retransmission times of the mixed retransmission request, and determining the initial position of the data bit of the formed mixed retransmission request data packet read from the one-dimensional limited-length circular cache according to the selected redundant version value; and reading the mixed automatic retransmission request data packet composed of specific-length data from the initial position in order, and sending the mixed automatic retransmission request data packet out. The respective corresponding initial positions of the multiple preset redundant version values are evenly or almost evenly distributed on the one-dimensional limited-length circular cache.

In a method for a variable-length communications system including encoding a message and decoding a data bit stream, the message includes a plurality of message blocks. A message block of the message is encoded by generating a parity check bit stream, flipping the parity check bit stream, and appending the flipped parity check bit stream to the end of the message block. When a data bit stream is received, a guessed message block and a guessed flipped parity check bit stream are extracted based on a guessed message block length. A parity check bit stream is generated for the guessed message block and then flipped. If the flipped parity check bit stream is the same as the guessed flipped parity check bit stream, the message block has been identified. Otherwise, the guessed message block length is increased by 1 and the above step is repeated.

Disclosed are an apparatus and a method for transmitting uplink control information in an OFDMA communication system. The method, in which the uplink control information is transmitted using an ACK channel in the OFDMA communication system, includes the steps of receiving data bits of the uplink control information, outputting transmit symbols of sub-carriers by performing orthogonal modulation with respect to symbols for codewords of the received data bits, and inverse fast fourier transforming and transmitting a transmit signal including bundles of sub-carriers allocated the modulated transmit symbols.

A data communication interface for transferring at least one data bit to a host processor. The interface includes a one-wire data line, and a slave processor connected to the data line and including a pull-down circuit for varying voltage on the data line. The slave processor is passive and incapable of sampling data from the data line. The slave processor is programmed to vary voltage on the data line when the data line is energized, to signal at least one data bit.

A method and apparatus for performing memory array/row scoreboarding in a dynamic access memory (DRAM) having dual bank access. The DRAM of the present invention allows dual simultaneous memory accesses into a memory divided into a plurality of arrays (e.g., 48 arrays). Each array of the DRAM contains a plurality of rows (e.g., 256). Each row of the DRAM contains storage for a certain amount of data bits (e.g., 1024). The DRAM in one configuration contains 1.5 Megabytes of memory. During a dual bank DRAM access, the system allows a first access for pre-opening a row (e.g., a page) of DRAM memory within a first array while simultaneously allowing a second access for reading/writing data to an opened row of another array aside from the first array. The present invention scoreboarding system tracks the rows that are currently open so that immediate read/write accesses can take place. Upon presentation of a row and array, the scoreboard determines if the presented row is currently open, and if so, generates a hit signal that allows an immediate read/write access to the presented row. If the presented row is not open, the present invention generates a miss signal so that the row can be immediately opened before access is allowed. The scoreboard contains a memory unit containing row information for each array in the DRAM. The scoreboard, in addition to other novel features, allows an efficient DRAM configuration allowing dual memory accesses per cycle.

A method and system sense the logic state of an unknown initial data bit stored in a selected resistive memory cell. According to one method, a first count representing the logic state of the unknown initial data bit stored in the selected memory cell is generated. A second count is then generated, and represents a data bit having a first known logic state stored in the selected memory cell. A third count is then generated, and represents a data bit having a second known logic state stored in the selected memory cell. The logic state of the initial unknown data bit stored in the selected memory cell is then determined from the first, second, and third counts.

A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hubs each include a transmit interface having a data organization system that organizes a command header and data for each of a plurality of memory transactions into lane groups each of which contain a predetermined number of lanes. Each of the lanes contains either parallel command header bits or parallel data bits. The lane groups are then converted to a serial stream of lanes and transmitted from the memory hubs through a high-speed bus. The lane groups are organized so that they are always filled with lanes containing either a command header or data. As a result, the high-speed bus is never idle during transmission of memory transactions from the memory hub thereby maximizing the memory bandwidth of the memory system.