3380 results about "Data bits" patented technology

Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2^M−1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.

A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.

A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

A WCDMA system includes a Base Station (BS) or forward transmitter and a pilot channel that transmits control signals between a Mobile Station (MS) and BS to reconfigure their transmitter/receiver according to the prediction of the channel power and channel power probability density function separated into three distinct equal probable regions. Data signals are encoded using a one-half Viterbi encoder and interleaved. The interleaved data bits are modulated using Quadrature Phase Shift Keying (QPSK) modulation. The QPSK data is multiplexed with the pilot channel and spread by an appropriate code in an OFDM transmitter modified by a long code. Output of the transmitter may be provided to two diverse antennas for reliable communications to the receiver. Data may be received at two diverse antennas. The outputs are provided to match filters coupled to a coherent rake receiver and a channel prediction system. The future attenuation of the channel coefficients and power are determined by the prediction system for several milliseconds. The power levels of each finger in the Rake receiver can be predicted and the strongest ones used in determining the optimum transmitter power or rate control for operating the system transmitters and receivers based on computing a long range power prediction of each finger of a rake receiver.

Techniques for improved timing control of memory devices are disclosed. In one embodiment, the techniques may be realized as a memory controller to communicate with a memory device via a communications link. The memory controller may comprise a memory interface to exchange data with the memory device via a set of N conductors according to at least one clock, the data being encoded such that each M bits of data are represented by at least one symbol and each symbol is associated with a combination of signal levels on a group of n conductors, wherein M<N and n is equal to at least one and at most N. The memory may also comprise clock control logic to receive timing calibration information from the memory device and to output a signal to adjust a phase of the at least one clock based on the timing calibration information.

A memory module for attachment to a computer system having a memory bus and a method of using the memory module for error correction by scrubbing soft errors on-board the module is provided. The module includes a printed circuit card with memory storage chips on the card to store data bits and associated ECC check bits. Tabs are provided on the circuit card to couple the card to the memory bus of the computer system. Logic circuitry selectively operatively connects and disconnects the memory chip and the memory bus. A signal processor is connected in circuit relationship with the memory chips. The logic circuitry selectively permits the signal processor to read the stored data bits and associated check bits from the memory chips, recalculate the check bits from the read stored data bits, compare the recalculated check bits with the stored check bits, correct all at least one bit errors in the store data bits and stored associated check bits and re-store the correct data bits and associated check bits in the memory chips. When the memory chips and the memory bus are disconnected, single bit soft errors occurring during storage of the data bits and check bits are corrected periodically before the data is read from the memory chips to the data bus on a read operation.

A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.

The present invention relates to methods, apparatuses, and systems for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits processing the outer encoded bits using an interleaver and a logical unit to produce intermediate bits, wherein the logical unit receives a first number of input bits and produces a second number of corresponding output bits, the second number being less than the first number, and wherein the logical unit takes each of the first number of input bits into account in producing the second number of output bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, wherein the inner convolutional code is characterized by at least two states, and combining the data bits and the inner encoded bits to produce encoded outputs.

A forward link device of a multicarrier CDMA communication system with an overlay scheme in which a multicarrier system and an IS-95 system share same frequency bands. In the forward link device, four encoders encode input data of corresponding rates with a 1/3 coding rate, respectively. A first repeater repeats two times full rate symbols output from the first encoder, and second to fourth repeaters repeat symbols output from the second to fourth encoders, respectively, according to a predetermined number of times, to match the number of corresponding output symbols to the number of full rate symbols. First to fourth interleavers interleave the symbols output from the first to fourth repeaters, respectively, to uniformly distribute the symbols of the same data bit to the carriers.

A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.

A method and apparatus for transmitting uplink acknowledge information (ACK) in a communication system using an orthogonal frequency division multiple access (OFDMA) scheme. The method includes receiving a data bit for the uplink ACK; outputting codewords corresponding to the data bit; performing quadrature phase shift keying (QPSK) modulation on symbols for ACK vector indexes corresponding to the codewords for the received data bit; performing inverse fast Fourier transform (IFFT) on a transmission signal having subcarrier clusters to which the modulated transmission symbols are allocated; and transmitting the IFFT-processed transmission signal.

In transmitter apparatus for a digital television (DTV) broadcasting system, internet-protocol (IP) packets of digital television information are subjected to multilevel concatenated Bose-Chaudhuri-Hocquenghem (BCH) coding and low-density parity-check convolutional coding (LDPCCC) before being bit-interleaved and mapped to quadrature-amplitude-modulation (QAM) constellations. The QAM constellations are used in coded orthogonal frequency-division modulation (COFDM) of plural carrier waves up-converted to a radio-frequency broadcast television channel. In receiver apparatus for the DTV broadcasting system the results of de-mapping QAM constellations recovered from demodulating the COFDM carrier waves are de-interleaved, and the constituent LDPCCC codewords are decoded to recover constituent BCH codewords of the multilevel BCH coding. The constituent BCH codewords are decoded to correct remnant bit errors in them. Then, IP packets of digital television information are reconstituted from the systematic data bits in those BCH codewords.

An orthogonal frequency division multiplexing (OFDM) transmitter method, consistent with certain embodiments of the present invention arranges OFDM data symbols representing data bits for transmission in a packet. A prescribed pattern of OFDM data symbols are removed (212) and replaced (216) with pilot symbols. The packet is then transmitted (220) to an OFDM receiver that receives the packet (224) and determines a channel correction factor from the pilot pattern. The receiver then estimates a plurality of channel correction factors, one for each of the plurality of OFDM symbols representing data (228) and uses these correction factors to correct the OFDM symbols representing data (232). Arbitrary data are then inserted in place of the pilot symbols (236). The OFDM symbols representing data along with the arbitrary data are then decoded using an error correction decoder that corrects the errors induced by substitution of the pilot symbols for data symbols (240).

A method for improving a cooperation between a packetized data bit-rate adaptation and a data packet re-transmission transmits data packets from a server to a client with a first bit-rate; stores transmitted data packets in a server buffer; stores transmitted data packets in a client buffer; signals impairment information related to an impairment of transmitted data packets during transmitting to the server, wherein the signaled impairment information is analyzed by the server to decide if a re-transmission of data packets stored in the server buffer is required; and signals client buffer information related to a state of the client buffer to the server, wherein the client buffer information is analyzed by the server to decide if a re-transmission of data packets is required.

Systems, methods, and devices for managing endian-ness are disclosed. In one embodiment, a device is configured to selectively operate in one of a big-endian operating mode or a little-endian operating mode. The device may include a register in which the current endian mode of the device is indicated in at least two different bit positions within the register. The at least two different bit positions may be chosen such that a data bit in one of the bit positions would be read by a system if the device and system operate in the same endian mode, while a data bit in another of the chosen bit positions would be read by the system if the device and system are operating in different endian modes from one another. In some embodiments, the endian mode of the device may be controlled by a hardware input or a software input.

A disk drive includes a sampled servo controller for periodically adjusting a control effort signal during a track-following operation based on embedded distributed position information and repeatable runout (RRO) cancellation values for reducing effects of RRO in the distributed position information during track following. A magnetic disk in the disk drive stores RRO information relating to predetermined RRO cancellation values for a data storage track. The RRO information for the data storage track includes at least one first data structure having a first predetermined number of data bits for representing an initial RRO cancellation value, and includes at least one second data structure having a second predetermined number of data bits associated with a respective subsequent RRO cancellation value. The first predetermined number of data bits is greater than the second predetermined number of data bits.

A payment card comprises a plastic card with a magnetic stripe for user account data. Internal to the plastic card, and behind the magnetic stripe, a number of fixed-position magnetic write heads allow the user account data to be automatically modified. For example, a data field that counts the number of times the card has been scanned is incremented. A payment processing center keeps track of this usage-counter data field, and will not authorize transaction requests that come out of sequence. For example, as can occur from a magnetic clone of a card that has been skimmed and tried later. A card-swipe detector embedded in the plastic card detects each use in a scanner, and it signals an internal microcomputer which changes data bits sent to the write heads. Once scanned, the payment card can also disable any reading of the user account data for a short fixed period of time.

A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. In another aspect, a system differentiates between data bits based on their estimated reliability, giving more emphasis to decoding reliable bits than unreliable bits using any of a variety of techniques. By differentiating between god and bad bits and de-emphasizing or ignoring unreliable bits, the system can provide a significant reduction in uncorrectable errors and packet loss.