659 results about "Data bits" patented technology

The embodiment of the invention provides a data tracking circuit, a data tracking processing method, a chip and electronic equipment, the data tracking circuit comprises a selection module and a packaging engine module, tracking source data is received and selected to be output as tracking data through the selection module, the packaging engine module packages the tracking data to generate corresponding data frames, and the corresponding data frames are stored in the storage module. The data frames comprise the identifiers used for identifying the types of the data frames, the larger the number of the data frames of the same type is, the shorter the data bit width of the identifiers of the data frames of the type is, compared with identifiers of fixed lengths, the lengths of most identifiers can be shortened, the data size of the data frames is reduced on the whole, and the data transmission efficiency is improved. And thus, the bandwidth required by the packaged data frame is also reduced.

The invention relates to the technical field of computer hardware and network communication, in particular to a high-speed I / O (input / output) virtualization server based on an FPGA (field programmable gate array) and a remote forwarding method.The high-speed I / O virtualization server comprises an FPGA chip, a network processing unit, an I / O protocol processing unit, a protocol conversion and scheduling unit, a time sequence and transaction management unit and a data buffering and flow control unit are integrated in the FPGA chip; the optical fiber Ethernet interface module comprises a physical layer interface and an MAC layer processing and network configuration interface; the local I / O interface module comprises a USB interface circuit, a serial port interface circuit, a PCIe interface circuit and an interface expansion connector; the power supply and monitoring module comprises a multi-path power supply management system, a state monitoring and diagnosis system and an LED indication system; according to the self-adaptive Baud rate detection circuit, the Baud rate can be accurately locked under the condition that data with less than two characters is received, the number of data bits, the type of a check bit and the length of a stop bit are automatically identified, and compared with a traditional microcontroller scheme, the self-adaptive Baud rate detection circuit has higher precision and higher detection speed.

The invention discloses a robot track online compensation and precision control method and system based on multiple sensors, and belongs to the technical field of robot track control. The method comprises the following steps: acquiring target trajectory data and original data of each sensor, and performing time alignment on the original data of each sensor to generate a fusion data set comprising vibration acceleration data and pose data; performing time-frequency feature extraction based on the vibration acceleration data to obtain a dominant vibration frequency spectrum; constructing a mechanical transfer function model of the joint driving torque and the tail end vibration displacement; based on the mechanical transfer function model, constructing an adaptive notch filter to generate a feed-forward compensation sequence; according to the target trajectory data, the pose data and weight parameters, updated in real time, of the sensors, a trajectory fusion deviation value is obtained through calculation; and after the feedforward compensation sequence and the trajectory fusion deviation value are integrated, a joint driving current instruction is generated based on a fuzzy PID control algorithm. The robot trajectory control precision can be improved.

The invention provides an isomorphic sensor dexterous hand-tactile glove system and a data acquisition method, and belongs to the technical field of tactile sensing, the system comprises a tactile data acquisition module which comprises a glove main body and a fixed flange arranged on the glove main body, a tactile sensor array is arranged on the palm side of the fixed flange and used for collecting tactile data of interaction between the glove body and an object; the visual perception module comprises an infrared camera array and an RGB (Red, Green and Blue) camera array, and is used for tracking marking balls arranged on the fixed flanges so as to solve pose data of the fixed flanges and collecting RGB images of interaction between the glove main body and an object; and the multi-modal data processing module is used for receiving the tactile data, the pose data and the RGB image, realizing space-time alignment of the data and generating a standardized data set. The system is simple in structure, rapid in deployment and high in acquisition safety, and can be suitable for tactile big data acquisition under multi-scene and multi-task conditions.

The invention discloses a garbage collection optimization method and device, equipment and a medium. The invention relates to the technical field of solid state disks, which comprises the following steps that: a global invalid data bit chart is established in a host memory, each table item in the global invalid data bit chart corresponds to a physical block, and a bitmap bit in each table item corresponds to a physical page in the physical block; bit values corresponding to the bitmap bits comprise a first bit value and a second bit value; responding to a data updating event through an access acceleration engine so as to dynamically update the bit value of the corresponding physical page in the global invalid data bit graph; and when garbage collection is triggered, screening the physical page of which the bit value is the second bit value in a to-be-collected source physical block according to the global invalid data bit chart and the access acceleration engine to perform validity verification and data migration, and skipping the physical page of which the bit value is the first bit value. According to the invention, the garbage recycling efficiency is improved.

A transmitter system comprises a mapper configured to map data bits and power information to multiple subcarriers, producing mapped information. A first-level modulator converts this mapped information into subcarrier specifications, each defined by a complex number indicating amplitude and phase. The system includes multiple data stream / power channel digital paths, each with a frequency selector that processes a portion of the subcarrier specifications. An orthogonal subcarrier generator translates these specifications from frequency to time domain, generating baseband real and imaginary signals. A second-level modulator processes these signals with intermediate-frequency sine and cosine waves to produce IF I and IF Q signals. A beamformer modifies the phase and / or amplitude of these signals across multiple antenna channels, creating directed signals. Finally, a combiner adds output signals from each data stream / power channel digital path, directing them to corresponding antenna channel modules, facilitating efficient transmission across multiple channels.

The embodiment of the invention provides a single-bus communication method and device, a chip and a medium, and the method comprises the steps: enabling a host to enter an initialization mode after the host confirms that an internal power supply and a clock of a slave are stable; the host sends a wake-up code to the slave within a set time to wake up the slave, and releases the bus to enter a normal communication mode; the host sends a communication signal to the slave through the improved communication frame; after the host receives a response signal of the slave, the host releases the bus, the bus is pulled to a high level from an external pull-up resistor, and the transmission is ended; wherein the format of the improved communication frame comprises ten codes, one code corresponds to one bit, and the ten codes sequentially comprise one start bit, six address bits, one read-write control bit, one data bit and one response bit. A wake-up code is set before communication between the host and the slave, so that the slave is prevented from being mistakenly waken up. According to the communication mode, the coding mode is simplified, the chip area is reduced, and the transmission speed of the chip is also improved.

The invention provides a 200GE service data transmission method based on 224G high-speed SerDes, a chip and a communication system, and the method comprises the steps that a PCS sending module carries out PCS sending processing on obtained upstream data to obtain first PCS data; the PCS sending module sends first PCS data to the PMA sending module through the rate increasing module according to the first PCS clock rate and the first PCS data bit width; the rate increasing module determines first clock information according to the first PMA data bit width, the first PMA clock rate, the first PCS clock rate, the first PCS data bit width and the set bandwidth so as to increase the first PCS clock rate; the PCS sending module sends first PCS data according to the first PMA data bit width and the improved first PCS clock rate; the PMA sending module processes the first PCS data and sends the first serial data. The method can be applied to the fields of internet access and related services, the alignment mark insertion process is avoided so as to improve the sending rate of the PCS layer, and the PMA state frame is introduced so as to accelerate link convergence and improve link stability.

The invention relates to the technical field of power transmission line state monitoring, and particularly provides a power transmission line dynamic dance positioning detection method and system, and the method comprises the following steps: collecting Beidou positioning data, pose data and environment parameter data of a power transmission line in real time; correcting the Beidou positioning data according to the coordinate error component and the pose data of the base station, and filtering a multipath effect deviation signal to obtain absolute coordinate data; calculating galloping parameter data of the power transmission line according to the absolute coordinate data; and dynamically fusing the galloping parameter data and the environment parameter data to obtain comprehensive detection data. The problems of large dancing posture detection error and high time delay of the power transmission line in the prior art are solved.

The invention provides an SLAM (Simultaneous Localization and Mapping) optimization method and equipment based on point cloud registration and adaptive resolution, and a medium, and relates to the technical field of AGV (Automatic Guided Vehicle) positioning and mapping, and the method comprises the following steps: (1) inputting and preprocessing sensor data; (2) front-end scanning and matching: based on the preprocessed data, carrying out point cloud registration through a GICP algorithm, updating the pose of the current frame and constructing a local subgraph; (3) global SLAM: receiving sensor data, poses and subgraph data from the front-end scanning and matching step, and carrying out loopback detection and global optimization; wherein a self-adaptive resolution switching strategy based on environment complexity is adopted in the loopback detection process; according to the GICP algorithm, the surface of the point cloud is modeled as Gaussian distribution, local features are described through a covariance matrix, and a target error function constructed based on the mahalanobis distance is optimized to estimate pose transformation. According to the method, the local matching precision and robustness are improved by replacing ICP with GICP, and the global calculation efficiency is adjusted and optimized in combination with the dynamic resolution.

The invention discloses an ALU operation fusion processing module and method suitable for a neural network, and the module comprises a control unit which is used for receiving and decoding a machine instruction, managing the execution processes of internal and external circulation and microinstruction circulation, and generating a control signal of each stage of a microinstruction assembly line; the microinstruction buffer area is used for storing a microinstruction sequence pre-generated by the neural network compiler; the register file is used for storing source operands and results of ALU operation; each entry of the register file is composed of a valid bit, a tag bit and a data bit; the ALU computing core adopts an SIMD (Single Instruction Multiple Data) architecture and comprises a plurality of paths of parallel arithmetic logic function units; the Load / Store unit is used for processing data exchange between a register file and a local buffer area; and the data selection interface is used for selecting a data source or a target buffer area according to the storage tag field of the microinstruction. According to the method, the high efficiency and the flexibility of the ALU in the neural network hardware accelerator can be effectively considered.

There is provided a storage device which includes a plurality of nonvolatile memory devices, and a memory controller connected in common to the plurality of nonvolatile memory devices through first signal lines and connected in common to the plurality of nonvolatile memory devices through second signal lines. Each of the plurality of nonvolatile memory devices receives a command and an address through the first signal lines and communicates data bits with the memory controller through the second signal lines. While the command and the address are not received through the first signal lines, the plurality of nonvolatile memory devices exchange information through the first signal lines without control of the memory controller.

In a data storage device with a multi-level-cell memory, bits of data are stored in different levels of each of the memory cells. In some situations, a quantized version of the stored data (e.g., the most-significant bits) may be requested. Responding to such a request can involve reading all levels of the memory cells to retrieve a full version of the data and then selectively providing only the quantized version. To improve performance, the data is stored in the memory in an interleaved manner in which the quantized version of the data is stored in the same level(s) instead of being spread across all levels of the memory cells. That way, when the quantized version of the data is later requested, only the relevant level(s) are sensed, thereby avoiding the time and resources needed to read memory level(s) that do not store the quantized data.

The invention provides a temporary check block repairing method and system based on erasure codes in distributed block storage, and the method comprises the steps that a distributed block storage system detects that a check block fails to be written in, and a metadata service creates a temporary check block according to an erasure code mode; the temporary check block records an operation log and executes data writing, and replays IO operation according to a data version number; repairing the inconsistency of the data blocks by using the operation log of the temporary check block; and quickly recovering the check block data through the data bitmap of the temporary check block. According to the rapid recovery processing method for the temporary check block, the check block data can be directly recovered without a coding mode, the internal IO is reduced, and the recovery speed of the erasure code check block is increased.

The invention relates to the technical field of computers, and discloses a topological structure generation method, a communication method, equipment, a chip and a program product. The topological structure parameters comprise a plurality of master port identifiers, a plurality of slave port identifiers, a mapping relationship between a plurality of master ports and a plurality of slave ports and first data bit widths of the plurality of master ports and the plurality of slave ports, and the mapping relationship comprises that at least two master ports in the plurality of master ports correspond to the same slave port in the plurality of slave ports, and / or at least two slave ports in the plurality of slave ports correspond to the same slave port in the plurality of slave ports. At least two slave ports in the plurality of slave ports correspond to the same master port in the plurality of master ports; determining communication parameters based on the topological structure parameters, wherein the communication parameters comprise the number of arbiters and arbitration parameters; and generating a topological structure file based on the communication parameters, the plurality of master ports and the plurality of slave ports, the topological structure file comprising connection lines among the plurality of master ports, the plurality of slave ports and the at least one arbiter. A user does not need to manually configure an arbiter and calculate, and the labor cost is saved.

A wireless communication system for enhanced reliability of wireless communication and reducing peak power in wireless data transmission across different waveforms comprising transmitter modules coupled to waveform modulators including waveform two-dimensional resource or data grids representative of a signal processing domain for transmitting data bit bearing symbols across varied waveforms under controlled sparsely / partially loading of fewer modulated data symbols of the available grid points of a larger two-dimensional resource or data grid for transmission as spaced fewer data symbols with loading zero symbols at remaining empty grid points. The modulated data symbols under controlled sparsely / partially loading including said fewer modulated data symbols being allocated in the resource or data grid and distanced there between based on a factor for partial loading and full number of symbols accommodable in the resource or data grid to reduce cross interference amongst symbols and minimize error rate.

A pixel circuit can include an internal compensation unit having a driving transistor and a capacitor having a first terminal connected to a gate electrode of the driving transistor. Data lines are connected to a first electrode of the driving transistor and a second terminal of the capacitor, respectively, so that a light-emitting element emits light with a grayscale corresponding to a difference between data voltages charged in the capacitor. Accordingly, the number of bits of data output from channels of a data driving circuit can be reduced.

The invention provides a detection process processing system and method for a package substrate production line, and relates to the technical field of package substrate manufacturing and processing. The system comprises a plurality of detection devices, a control unit, an EAP system and an MES system, and each detection device is configured to perform defect detection and output detection data containing defect Mapping and defect coordinates; the detection data output by the detection equipment located at the tail end integrates the defect Mapping and the defect coordinates respectively acquired by all the detection equipment; the control unit is configured to generate a trigger instruction after determining that the plurality of detection devices complete detection. On the basis, defect detection is carried out on the packaging substrate in sequence through the multiple detection devices, the integrated defect Mapping and defect coordinates are finally output to achieve one-time waste marking, and the problem that an existing packaging substrate waste marking method has multiple limitations is solved.

The invention discloses a tunnel adaptive support system and a support parameter dynamic optimization method thereof, and the method comprises the steps: firstly, obtaining the deformation data and displacement data of surrounding rock and the pressure in a bag of a bag type support unit in real time, and forming a corresponding monitoring data time sequence; and then, inputting the monitoring data time sequence into a deformation prediction model which is learned through a global deformation rule in advance, and predicting the deformation of the surrounding rock in the future in advance through the deformation prediction model. And finally, the predicted deformation amount and the current deformation amount of the surrounding rock, the prestress of the SMA anchor rods and the pressure in the bag of the bag type supporting unit serve as state spaces, the bag body pressure of the bag type supporting unit and the current of the SMA anchor rods are dynamically regulated and controlled through a PPO reinforcement learning algorithm, phase change of the SMA anchor rods is triggered to compensate for creep displacement of the surrounding rock, and convergence deformation of the surrounding rock is effectively restrained. Therefore, 'monitoring-prediction-regulation 'closed-loop management of the support system is realized, and the defects of lagging response and poor generalization of a traditional method are overcome.

The invention relates to the technical field of integrated circuits, and discloses a parallel-serial conversion circuit. The parallel-serial conversion circuit comprises a parallel data storage unit, an odd-even data exchange unit, a shifting unit and a selection output unit, the parallel data storage unit is connected with a parallel data input end and a parallel clock signal end, and the odd-even data exchange unit is connected between the parallel data storage unit and the shifting unit. The data output module is used for directly outputting parallel data or performing odd-even data bit exchange on the parallel data according to a first selection control signal and then outputting the parallel data; the shifting unit is connected with the odd-even data exchange unit, the selection output unit and a serial clock signal end; and the selection output unit is connected with the shift unit, the serial clock signal input end and the serial data output end, and is used for sequentially and serially outputting each bit of data in the shift data along with the high and low levels of the serial clock signal. According to the technical scheme, the specific parallel-serial conversion mode can be dynamically configured, and the use flexibility of the I / O interface of the FPGA is improved.

This specification relates to file format-based transparent encryption tailored for big data. In some aspects, a method includes receiving a write request including a table with one or more columns to be stored in a storage device; compressing table data in a unit of block, wherein each column includes a number of blocks; generating a column key for each column and a block key for each block including sensitive information; encrypting (i) each block including sensitive information with a corresponding block key and (ii) rest of blocks in each column with a corresponding column key; generating wrapped keys for the column keys and block keys and storing the wrapped keys into a key file; and storing the encrypted blocks of each column into a data file in a data folder of the storage device.

A memory circuit comprises: a first memory cell configured to store a first data bit; a second memory cell configured to store a second data bit; a sampling amplifier coupled to the first and second memory cells, respectively, via a data bit line and a reference bit line; a first switch; and a second switch. The first switch is selectively coupled between the data bit line and a first input node of the sampling amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sampling amplifier.

A method for performing Tile to Raster (T2R) conversion includes: receiving tile input data including a stream of a plurality of tiles each having a tile height, a tile input width, a macroblock width (MBW), and data bits; segmenting the tile input data based on a total number of virtual square tiles; segmenting a Tile Buffer (TB) into one or more of the virtual square tiles based on the received tile input data; and performing a raster-scanning operation on each of the segmented tile input data and the segmented TB based on the total number of virtual square tiles to generate raster data.

A three-dimensional memory array comprising a plurality of NAND strings. Each NAND string is configured to store a storage data having multiple bits and receive a searching input having multiple bits. Each bit of the storage data and the searching input is of a bit value “0”, a bit value “1”, a wildcard bit or an invalid bit. At least one bit of the storage data is configured as data bit(s), at least bit of the searching input is configured as search bit(s). All of the data bit(s) and the search bit(s) are of bit value “0” or bit value “1”. When the position of the data bit(s) in the storage data overlaps with the position of the search bit(s) in the searching input, the NAND string that stores the storage data is turned off; otherwise, the NAND string that stores the storage data generates an output current.

The invention relates to a message verification method and device and a vehicle, relates to the technical field of hardware-in-the-loop testing, and aims to solve the problem of difference between original data of a bottom layer of a controller and data processed by an application layer. The method comprises the following steps: acquiring message description information corresponding to a target message sent by a controller in a hardware-in-the-loop test process of the controller; determining whether the message description information comprises target information or not; wherein the target information is used for indicating the data bit without the signal value in the target message. And under the condition that the message description information does not comprise the target information, generating the target information. And updating the target information to the message description information. And the updated message description information is utilized to perform message verification on the target message, so that the problem of data difference between a bottom layer and an application layer can be solved, and the efficiency and reliability of system development are improved.

The invention belongs to the technical field of integrated circuits, and particularly relates to a burning circuit with a configurable port mapping function and a burning method thereof. Comprising a mapen signal generating circuit which is used for detecting and counting rising edges of clock signals CLKPmap input by a clock mapping IO port, when a counting value reaches a preset fixed threshold value, data signals DATAPmap input by a data mapping IO port serve as to-be-matched data, the to-be-matched data are compared with reference data bit by bit, and when the counting value reaches the preset fixed threshold value, the to-be-matched data are obtained; a comparison result signal mapen is output to enable the port configuration circuit; the port configuration circuit is used for selecting a mapping pair port or a default pair port as a burning port under the enabling of the comparison result signal mapen; according to the method, the default port and the mapping port are selected, so that the layout flexibility of the PCB is improved, the wiring complexity is reduced, and meanwhile, the adaptability of a packaging form is improved.

A semiconductor device includes a scan data output and a scan chain having length n. Scan data bits appear sequentially at the scan data output responsive to a scan clock when the device is in a scan mode. Initial masking circuitry is operable to obscure, responsive to the device transitioning from a non-scan mode to the scan mode, a first n bits of the scan data appearing at the scan data output and not to obscure n+1st and subsequent bits of the scan data appearing at the scan data output. Infinite masking circuitry is operable to obscure, responsive to an infinite masking trigger, all scan data bits appearing at the scan data output until a reset of the device occurs. Monitoring and security enforcement circuitry is operable to detect a configuration change and to generate the infinite masking trigger if the detected change corresponds to a potential security risk.

A neural network device, a computing system, and a method of processing a feature map are provided. The neural network device includes at least one processor configured to implement: an arithmetic circuit configured to generate third data including a plurality of pixels based on a neural network performing an arithmetic operation on first data and second data; and a compressor configured to generate compressed data by compressing the third data, wherein the compressor is further configured to generate bitmap data as the compressed data based on a quadtree structure, the bitmap data including position information of non-zero pixels having non-zero data values among the plurality of pixels.

The invention relates to a vehicle driving coverage mileage calculation method, device, equipment and medium, the vehicle driving coverage mileage calculation method comprises the following steps: obtaining target road network data of at least a part of roads located in a target geographic area, the target road network data comprising a plurality of road section data, and the plurality of road sections form at least a part of roads; determining a first geographic position of a target vehicle running in the target geographic area when a preset vehicle event occurs; determining first road section data matched with the first geographic position in the target road network data; screening second road section data which are located on the same road as the first road section data and are communicated with the first road section data from the target road network data; and calculating the total mileage covered by the first road section data and the second road section data to obtain the driving coverage mileage of the target vehicle. According to the method provided by the invention, the driving coverage mileage of the vehicle can be accurately, quickly and lightly calculated.

A memory system includes a non-volatile memory having a plurality of blocks, and a memory controller. The memory controller is configured to set one of writing modes including a first mode of writing a single bit of data per memory cell and a second mode of writing multi bits of data per memory cell as a data writing mode for each of one or more blocks, upon receiving information indicating a size of write data to be written into the non-volatile memory from a host device, determine whether the size exceeds a size of a first free space of the non-volatile memory usable for data writing in the first writing mode, and upon determining that the size of the write data exceeds the size of the first free space, write at least a part of the write data into the non-volatile memory in the second writing mode.