41results about "Data representation error detection/correction" patented technology

The invention relates to the technical field of computers, and discloses an information source coding matrix data processing method based on a modified conjugate gradient algorithm. According to the method, sparsity constraint and a fixed-point quantization mechanism are fused in iterative optimization, and a sparse fixed-point coding matrix meeting hardware deployment requirements is directly generated through gradient shielding, correction conjugate parameter calculation and Armijo criterion line search and synchronous execution of hard threshold sparseness and fixed-point quantization after each update. According to the method, the sparsity constraint and the fixed-point quantization mechanism are embedded in the iteration process of the modified conjugate gradient algorithm, so that end-to-end alignment of coding matrix optimization and hardware deployment requirements is realized.

An ECC engine of a semiconductor memory device includes an ECC encoder and an ECC decoder. The ECC encoder generates parity data based on main data based on a primitive polynomial and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page based on an address to generate a syndrome and corrects at least one error bit in the read codeword based on the syndrome by respectively applying different syndromes to a single bit error in the read codeword, adjacent bit errors and non-adjacent bit errors occurring in non-adjacent two memory cells in the target page. The ECC decoder generates the different syndromes based on a parity check matrix generated as a function of the primitive polynomial. The primitive polynomial has an alpha matrix as a solution belonging to a Galois field.

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

The present application provides a communication method and device. The method comprises: a first device performs channel encoding processing on a first data packet on the basis of first context information, to obtain an encoded first data packet, wherein the first context information is associated with first data having a first fault tolerance capability, the first context information is used for indicating the temporal and / or spatial correlation between two frames, the first fault tolerance capability indicates support for obtaining a frame to which the first data belongs on the basis of a preset number of data packets, the first data comprises N data packets, the first data packet is any one of the N data packets, and N is a positive integer; and the first device sends the encoded first data packet to a second device. According to the method, the encoding efficiency can be effectively improved, and the reliability of data transmission and the performance (or efficiency) of data transmission can be improved.

This invention relates to the field of computer technology and discloses a method for processing source coding matrix data based on a modified conjugate gradient algorithm. This method integrates sparsity constraints and fixed-point quantization mechanisms in iterative optimization. Through gradient masking, modified conjugate parameter calculation, and Armijo criterion line search, and by synchronously performing hard-threshold sparsification and fixed-point quantization after each update, it directly generates a sparse fixed-point coding matrix that meets hardware deployment requirements. This invention achieves end-to-end alignment between coding matrix optimization and hardware deployment requirements by embedding sparsity constraints and fixed-point quantization mechanisms within the iterative process of the modified conjugate gradient algorithm.

The present disclosure relates to a channel coding method and device, electronic equipment, storage medium and computer program product, the method comprising: at a data sending end, encoding a first k-ary remainder vector based on a target RRNS encoder to obtain a first n-ary remainder vector; transmitting the first n-ary remainder vector from the data sending end to a data receiving end using a target channel; at the data receiving end, obtaining a second n-ary remainder vector from the target channel, and decoding the second n-ary remainder vector based on a target RRNS decoder to obtain a third n-ary remainder vector, the target RRNS decoder comprising at least one target RRNS encoder, and the third n-ary remainder vector being obtained after error correction of the second n-ary remainder vector. The embodiments of the present disclosure are effectively applicable to high-performance low-latency data transmission scenarios, and the decoding process can reuse the encoder logic, thereby increasing the hardware circuit reusability and expandability.

A memory device includes at least three digital storage circuits arranged in parallel, the digital storage circuits each configured to store state data representing a bit of data in a first or second state; a data input configured to receive input data, the input data representing a bit of data in the first or second state; a voter having a voter output, the voter configured to generate output data at the voter output, the output data representing which of the first and second state are in a majority among the state data stored in each of the digital storage circuits; and a multiplexer operatively coupled to the data input, the voter output, and an input of each of the digital storage circuits, the multiplexer configured to output, to each of the digital storage circuits, one of the input data and the output data based on a functional enable signal.

The application discloses a kind of quantum torus code decoder and method, using the self-attention U-net quantum error correction decoder obtained by training to decode torus code.SU‑NetQD is composed of two parts of low-level decoder and high-level decoder.The low-level decoder uses the extracted error syndrome as input and predicts recovery chain operation, and the high-level decoder uses the recovery chain predicted by the low-level decoder and the original error syndrome as input and predicts the logical error introduced by the low-level decoder.The decoder decodes successfully when and only when the recovery chain predicted by the low-level decoder can completely eliminate the error syndrome, and the logical error predicted by the high-level decoder conforms to the combined effect of the recovery chain and the original error.The application can efficiently and quickly implement the denoising function for torus code under complex noise, maintain the original information of quantum bits without interference, and perform better than the traditional MWPM decoder in various situations.

A two-dimensional square constraint encoding and decoding method and device, relating to the fields of data storage and data communication. The encoding method comprises: caching a one-dimensional data stream, and dividing the one-dimensional data stream into several sets of one-dimensional 2-bit data; according to an encoding table, encoding each set of 2-bit data into a 3∗2 two-dimensional codeword in sequence by an encoder, and then cascading all the two-dimensional codewords into a two-dimensional constraint array in a specified order; the decoding method comprises: reading the two-dimensional constraint array by a decoder, and dividing the two-dimensional constraint array into several 3∗2 two-dimensional codewords; decoding each two-dimensional codeword into the one-dimensional 2-bit data in sequence through a decoding table, and then successively assembling the generated one-dimensional 2-bit data into the one-dimensional data stream and outputting. The two-dimensional square constraint in the present invention means that in a binary data array composed of data "0" and "1", along four directions of a horizontal direction, a vertical direction, a northeast direction and a southeast direction, the two data "1" cannot be directly adjacent to each other.

An ECC engine of a semiconductor memory device includes an ECC encoder and an ECC decoder. The ECC encoder generates parity data based on main data based on a primitive polynomial and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page based on an address to generate a syndrome and corrects at least one error bit in the read codeword based on the syndrome by respectively applying different syndromes to a single bit error in the read codeword, adjacent bit errors and non-adjacent bit errors occurring in non-adjacent two memory cells in the target page. The ECC decoder generates the different syndromes based on a parity check matrix generated as a function of the primitive polynomial. The primitive polynomial has an alpha matrix as a solution belonging to a Galois field.

Provided are a communication method and device, the method comprising: a first device performing channel coding processing on a first data packet based on first context information to obtain a coded first data packet; wherein the first context information is associated with first data with a first fault-tolerant capability, the first context information is used for indicating the relevance of time and / or space between two frames, the first fault-tolerant capability indicates that the frame to which the first data belongs is supported to be obtained based on a preset number of data packets, and the first data comprises N data packets, the first data packet is any one of the N data packets, and N is a positive integer; and the first device sends the encoded first data packet to the second device. Through the method, the coding efficiency can be effectively improved, and the data transmission reliability and the data transmission performance (or efficiency) can be improved.

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

The present application provides a kind of error detection and correction device, including decision feedback equalizer (DFE), decision circuit, error detection circuit and error correction circuit.DFE equalizes data signal to generate first equalization signal.Decision circuit performs hard decision to first equalization signal to generate symbol decision signal.Error detection circuit performs forward error detection at the symbol position of the continuous symbol included in symbol decision signal to detect the first position of suspected error affecting at least one symbol in symbol decision signal.Error correction circuit performs error correction to symbol decision signal in response to the first position of suspected error detected by error detection circuit.Accordingly, the present application also provides a kind of error detection and correction method.

For example, an approach is proposed for processing a data word in which a data word is received in which a first syndrome of a first code is determined, wherein the first syndrome has components, and in which, if the syndrome of the first code detects an error, a second syndrome of a second code is determined, wherein the second syndrome includes the components of the first syndrome.

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

A method for decoding includes, in a decoder 20 of an error correction code (ECC), receiving, in a buffer 24, a codeword 50 of the ECC containing a plurality of symbols, the codeword being misaligned with one or both boundaries of the buffer. In the buffer, one or more bits that do not belong to the codeword are zeroed. One or more syndromes are computed for the codeword across both the codeword and the zeroed bits. Based on the calculated syndromes, locations of one or more erroneous symbols are identified in the codeword, and the erroneous symbols are corrected in the identified locations to restore an erroneous version of the codeword. The method further includes compensating for misalignment between the codeword and the buffer during calculation of the syndrome or during identification of the location of the erroneous symbol.

The disclosed systems and methods for transmission and reception comprising: i) receiving a plurality of data bits; ii) generating FEC-based encoded data bits in accordance with a zipper code framework incorporating component non-binary codes, wherein the zipper code framework including a buffer having a virtual buffer and a real buffer; iii) storing codewords associated with the FEC-based encoded bits in rows of the real buffer; iv) mapping a given codeword in a given row of the real buffer to different rows of the virtual buffer; v) receiving an analog signal transmitted by a transmitter; vi) processing the received analog signal and generating received forward error correction (FEC) -based encoded bits in accordance with a zipper code framework that incorporates component non-binary codes; and vii) decoding the received FEC-based encoded bits in accordance with a non-binary decoding technique and generating information bits.

The invention provides a pre-coding method with soft output. The pre-coding method comprises the following steps: step 1, establishing an inter-symbol interference (ISI) channel model and a Thomlinson-Harat Hammer pre-coding (THP) algorithm; step 2, establishing a soft output Viterbi SOVA equalization algorithm; and step 3, establishing an equalization scheme of combining THP precoding with soft output with an SOVA algorithm. The problem that an existing precoding scheme cannot be adapted to a forward error correction code FEC soft decision decoding scene is solved. Compared with the existing scheme, the scheme can significantly improve the balance performance of the system and the error correction performance of the forward error correction code after FEC decoding under the condition of only increasing a small amount of calculation complexity.

In one aspect, a method comprises: receiving a data transmission containing at least one orthogonal frequency division multiplexing (OFDM) packet from a second wireless device in a first wireless device; processing the at least one orthogonal frequency division multiplexing (OFDM) packet to recover data and provide the data to a host processor of the first wireless device; encoding at least one decoded symbol of the at least one orthogonal frequency division multiplexing (OFDM) packet with forward error correction encoding in the first wireless device; processing the encoded at least one decoded symbol to recover at least one corresponding transmitted symbol of the at least one OFDM packet; and determining a distance estimate between the first wireless device and the second wireless device, at least partially based on the corresponding transmitted symbol.

A computer-implemented method (100) for error correction encoding of source data transmitted in a communication network, where the transmitted data comprises tri-state qubits. The method comprises determining (101) a maximum number of transmission errors to be corrected in each codeword. The method further comprises creating (102) a strictly layered asymmetric graph of the words constituting the potential codeword, where nodes of the graph represent the words, and if the first word can become the second word by a transmission error, the first word is connected to the second word by a directed edge towards the second word. The method comprises selecting (103) a codeword from a lowest non-empty layer of the graph and adding (103a) the selected codeword to a codeword list. The method finally comprises encoding (104) the source data using the selected codeword from the list of codewords and initiating (105) a transmission of the encoded data.

An encoder, a decoder, and a method for encoding first data are shown, in which the channel encoding of the first data is parameterized by a secret key.

The invention belongs to the technical field of signal fitting processing, and discloses a forward error correction coding circuit and an FPGA chip. The forward error correction coding circuit comprises a first storage module and a second storage module which write data to be coded according to a first clock frequency and read the data to be coded according to a second clock frequency; the first coding module is used for receiving the data to be coded according to a second clock frequency, coding the data into first coded data and outputting the first coded data according to the second clock frequency; the second coding module is used for receiving the data to be coded according to a second clock frequency, coding the data into second coded data and outputting the second coded data according to the second clock frequency; the third storage module is used for writing the first coded data according to the second clock frequency and reading the first coded data according to the first clock frequency; and the fourth storage module is used for writing the second coded data according to the second clock frequency and reading the second coded data according to the first clock frequency. According to the invention, the bottleneck problem of a single coding module is solved, the coding efficiency is improved, and the high-speed FEC coding requirement is met.

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

The disclosed systems and methods for transmission and reception comprising: i) receiving a plurality of data bits; ii) generating FEC-based encoded data bits in accordance with a zipper code framework incorporating component non-binary codes, wherein the zipper code framework including a buffer having a virtual buffer and a real buffer; iii) storing codewords associated with the FEC-based encoded bits in rows of the real buffer; iv) mapping a given codeword in a given row of the real buffer to different rows of the virtual buffer; v) receiving an analog signal transmitted by a transmitter; vi) processing the received analog signal and generating received forward error correction (FEC) -based encoded bits in accordance with a zipper code framework that incorporates component non-binary codes; and vii) decoding the received FEC-based encoded bits in accordance with a non-binary decoding technique and generating information bits.

A computer-implemented method (100) for error correcting encoding of source data for transmission in a communications network, wherein the transmission data comprises qutrits. The method comprises determining (101) a maximum number of transmission errors to correct in each codeword. The method further comprises creating (102) a strictly layered, asymmetric graph of words constituting potential codewords wherein the nodes of the graph represent words and a first word is connected to a second word with a directed edge towards the second word iff the first word can turn into the second word by one transmission error. The method comprises selecting (103) a codeword from the lowest non-empty layer of the graph and adding (103a) the selected codeword to a list of codewords. The method finally comprises encoding (104) the source data using the selected codewords from the list of codewords and initiating (105) a transmission of the encoded data.

The disclosed communication system includes a Dynamic Multiple Input / Multiple Output Transmission System (DMTS) module, and an adaptive forward error correction (FEC) module. The FEC module includes a transmission module for receiving first packets and commands from the DMTS module, generating a parity check for n number of the first packets, and retransmitting the first packets with the parity check to a channel manager in a transmission direction. The FEC module also includes a receive module for receiving second packets from the channel manager in a receive direction. The DMTS controls when a parity check is sent for a given flow. The parity check may be sent across multiple channels, and the FEC module can be enabled or disabled for each traffic flow.

A storage device, including a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array including a plurality of word-lines stacked on a substrate, a plurality of memory cells provided in a plurality of channel holes, and a word-line cut region dividing the plurality of word-lines into a plurality of memory blocks. The storage controller groups a plurality of target memory cells into outer cells and inner cells. The storage controller includes an error correction code (ECC) decoder configured to perform an ECC decoding operation by obtaining outer cell bits and inner cell bits during a read operation on the plurality of target memory cells, and applying different log likelihood ratio (LLR) values to the outer cell bits and the inner cell bits.

The invention relates to a redundant remainder system (RRNS) channel encoder, an RRNS channel decoder, an RRNS channel encoding method, an RRNS channel decoding method, electronic equipment and a storage medium. A mode set corresponding to the RRNS channel encoder comprises k information modes and n-k redundant modes; the RRNS channel encoder comprises: an input module receiving a first k-element remainder vector comprising k information remainder components; the modular operation modules from the first level to the (k-1) th level determine k weights based on the k information remainder components and the k information moduli; the kth-level modular operation module determines n-k check remainder components based on the k information moduli, the k weights and the n-k redundancy moduli; the output module determines and sends a first n-element remainder vector to the target channel according to the k information remainder components and the n-k check remainder components. According to the embodiment of the invention, the implementation complexity of the digital circuit of the RRNS channel encoder can be reduced.

A method for operating a quantum error correction (QEC) code on a quantum computing system (QCS) is disclosed. The QCS includes a set of qubits and a set of couplers. An indication of a set of dropouts is received. Each dropout corresponds to a qubit that is non-functional or a coupler that is non-functional. The dropouts define a set of non-functional qubits, a set of functional qubits, a set of non-functional couplers, and a set of functional couplers. The QEC code is generated based on a set of heuristics, the set of functional qubits, and the set of functional couplers. The QEC code operates on the functional qubits. Each functional coupler provides a coupling between a pair of functional qubits. A quantum algorithm is executed that includes employing the QEC code to protect a set of logical qubits formed by the first subset of functional qubits from logical errors.