365 results about "Viterbi decoder" patented technology

A receiver system that receives signals and has a demapper device that is responsive to an equalizer output and generates a demapper output including one or more bit metrics. The receiver system also generates equalizer output, and the demapper uses distance measure to calculate bit metrics. The receiver system uses demapper output to generate a processed output. The receiver system further includes a convolutional decoder which is responsive to the processed output, and subsequently generates a decoded bit sequence, as well as uses the processed output to generate one or more path metrics. The convolutional decoder uses bit metrics and path metrics to the decode processed output, to generate a decoded bit sequence. The receiver system uses the distance measure to reduce the size of the bit metrics and the size of the path metrics to improve the performance of said convolutional decoder.

An enhanced VSB receiver includes a tuner which tunes an RF signal and converts it into an IF signal, an IF mixer which converts the IF signal into a baseband signal, and a demodulator which demodulates the baseband signal signal into a VSB signal. The enhanced VSB receiver further includes a map recovery unit which recovers VSB map information of the VSB signal, an enhanced equalizer for compensating channel distortion of the VSB signal and outputting an equalized symbol, and an enhanced Viterbit decoder for estimating whether polarity inversion occurred during a symbol period of the equalized symbol and Viterbi-decoding the equalized symbol based on the polarity estimation.

There is provided an apparatus and method for initializing a tap coefficient of an adaptive equalizer constituting a read path for a storage medium, where the apparatus includes an FIR filter, a Viterbi decoder, a level error detector, and a tap coefficient updater, the FIR filter receives a first signal stream and outputs the first signal stream in the form of a second signal stream, the Viterbi decoder corrects a bit error of the second signal stream, the level error detector detects a level error between the second signal stream and a third signal stream that is an ideal output signal corresponding to the second signal stream, the tap coefficient updater selects a tap coefficient minimizing the level error and provides the selected tap coefficient as a tap coefficient of the FIR filter, the tap coefficient minimizing the level error is determined as an initial value in a system initialization mode, and the determined initial value is used as an initial value of the tap coefficient of the FIR filter in a normal operation mode.

A multi-path equalization system for orthogonal frequency division multiplexing communication (OFDM) system includes a first estimator for estimating the channel characteristic using pilot signal. A divider is coupled to the estimator for dividing each sub-carrier with the channel characteristic to get the equalization to the data signal. A de-mapper uses the phase and amplitude correction of the channel estimate to recover the data signals. An improved channel estimation is provided by a repeat channel estimation feedback loop that includes the de-mapper a multiplier, an inverse fast Fourier transform (IFFT), a low pass filter and a fast Fourier transform (FFT). The improved channel estimation is obtained by multiplying at the multiplier the conjugate of the de-mapped data to the input sub-carriers and applying inverse FFT, low pass filtering and FFT to get the new channel estimate. Each sub-carrier is divided with new channel characteristic to get new equalization to the data signal. The channel estimation is repeated until there is convergence. The output is provided after the de-mapper. In the case of channel decoding to improve performance a Viterbi decoder and convolutional encoder is coupled in loop between the de-mapper and the multiplier.

A method of evaluating the quality of a read signal from the viewpoint of the detection margin of a Viterbi decoder in the PRML method in which a target signal level varies depending on the read signal, and an optical disc apparatus implementing the method. A method of evaluating the quality of a signal pattern comprising a combination of minimum run lengths from the viewpoint of edge shift, and an optical disc apparatus implementing the method. From the target signal level that varies depending on the read signal, a target signal is generated based on a decoding result, and an error target signal is generated in which the decoding result is edge-shifted. The signal quality is evaluated by calculating a Euclidean distance between these signals and the read signal. A virtual state that is not included in the Viterbi decoder and that is less than the minimum run length is defined, and a target signal level for the virtual state is generated using a target signal level table inside the Viterbi decoder, based on the concept of convolution. In this way, the signal quality can be evaluated by the same method as mentioned above even in cases where the pattern of a combination of the minimum run lengths has edge-shifted.

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Different sets symbols are precluded at prescribed times in time-dependent trellis coding. This increases the distances between different individual symbols as well as the distances between trellis codes, which increases the robustness of data transmission. The symbols that are precluded in this time-dependent trellis coding are determined in advance according to a prescribed pattern, which pattern does not depend on the history of previous symbols. The Viterbi decoder used for trellis decoding in a receiver can be designed to take advantage of knowledge concerning which different sets of symbols are precluded at prescribed times.

A decoding method for use in a communications system employing a communication channel in which a message is convolutionally encoded by a base station encoder and transmitted to a remote terminal during a time slot allocated to at least that remote terminal. The encoder is not completely reset immediately prior to the allocated time slot such the encoder state is unknown at the onset thereof. The decoding method includes assigning a most likelihood probability for an initial encoder state as being one of a number of predetermined encoder states; and, convolutionally decoding ensuing bits of the message based on the assumption of the initial encoder state as one of the predetermined states. The method affords low error rate decoding, and allows for improved power conservation by a mobile station, since the mobile station need not awaken significantly prior to its allocated time slot. Preferably, a Viterbi decoder is used to perform the convolutional decoding. The method has particular utility when used for decoding page messages indicative of call notifications in a paging channel of a code division multiple access (CDMA) wireless telecommunications system.

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Encoded symbols of a concatenated convolutional-encoded and block encoded signal are presented to a conventional first stage of a concatenated decoder, comprising in sequence a soft metric generator, a Viterbi decoder, a first de-interleaver and a first block decoder such as a Reed-Solomon decoder. The encoded symbols are also presented to a delay chain to produce progressively delayed encoded symbols. Where an output block of the conventional decoder is indicated as being a valid codeword by the first block decoder, the bytes in this block are marked as being correct. These bytes that are known to be correct are then used after interleaving and serialisation as known bits input to a second stage of the decoder process operating on the delayed encoded symbols and incorporating a modified soft metric generator constrained by the known bits. This process can be extended to further iterations as required. A modified Viterbi decoder, which is also constrained by the known bits, may also be used in the second and subsequent iterative stages.

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

A high-speed mixed analog/digital PRML data detection and clock recovery apparatus and method. The high-speed mixed analog/digital PRML data detection and clock recovery apparatus includes a variable gain amplifier, an analog equalizer, an analog-to-digital (A/D) converter, a DC offset remover, a level error detector, a Viterbi decoder, and an adaptive digital controller. The adaptive digital controller separately stores the level error values by predetermined frequencies, calculates predetermined coefficient values by each frequency component based on the level error values, and D/A-converts and applies the calculated predetermined coefficient values to the variable gain amplifier and the analog equalizer.

A DVB-T receiver includes a channel equalizer, a metric assignment and demapping circuit, a Viterbi decoder and an outer Reed-Solomon decoder. The metric assignment and demapping circuit includes a soft-decision quantising arrangement which provides confidence values for the Viterbi decoder. The quantising arrangement receives a control input from channel state indication (CSI) measurement circuitry.

A further channel state indication is obtained on a symbol-by-symbol basis. This is compared an average obtained over a few symbols, to detect impulsive interference, and applied as part of the control for the soft-decision quantiser.

A signal derived from the further channel state indication is also applied to the erasures input of the Reed-Solomon decoder.

Aspects of a method and system for redundancy-based decoding of video content in a wireless system are provided. A wireless receiver may determine whether a received multimedia data stream comprises video content and may select a redundancy-based decoder when video content is detected. The wireless receiver may be a WLAN receiver or a cellular receiver. Video content may be indicated by at least one flag in a preamble or a reserved field of the received multimedia data. The redundancy-based decoder may be a Viterbi decoder. The wireless receiver may enable a standard Viterbi decoder to decode portions of the multimedia data that do not comprise video content. The wireless receiver may generate at least one signal to select the redundancy-based decoder or the standard Viterbi decoder.

A broadcast and receiver system for performing content from combined A/53 and A/153 standard transmissions enabling simultaneous reception of both signal types with one device. A combination HDTV/Mobile DTV chip can be used that does not alter the legacy HDTV forward error correction (FEC) decoder and Mobile DTV standard transmissions may include extra training signals aiding the demodulation of legacy HDTV reception. Two separate Trellis decoders can be used: one for A/53 legacy HDTV decoding and the other for A/153 Mobile DTV decoding that uses a Hard Input Hard Output (HIHO) type of architecture. Separate Viterbi decoders are allocated for each block of data with a block Viterbi rotator to parse out/collect results of each Viterbi decoder. Each block has its convolutional encoder reset at the beginning. The second Trellis decoder operates serially so as not to disturb the A/53 HDTV data but could also be operated in parallel.

A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and path differences and communicate the identified path decisions and the identified path differences to a next ACS stage coupled thereto. The decoder also includes a Traceback unit for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory. The path differences associated with the ACS stage and the next ACS stage provide a reliability estimation of the correctness of the path decisions.

A quadrature amplitude modulation trellis coded modulation (QAM-TCM) decoding apparatus and the related method that receives and decodes a QAM signal. The QAM-TCM decoding apparatus includes an in-phase least significant bit (LSB) decoding path, which includes a in-phase Viterbi decoder for executing a decoding procedure on at least one LSB corresponding to an in-phase component of the QAM signal, a quadrature-phase LSB decoding path, which includes a quadrature-phase Viterbi decoder for executing a decoding procedure on at least one LSB corresponding to a quadrature-phase component of the QAM signal, and a most significant bit (MSB) decoding path for executing a decoding procedure on MSB portions corresponding to the in-phase or the quadrature-phase of the QAM signal. In doing so, the apparatus and method reduces the complexity of the decoding calculation.

The invention relates to an error correcting decoder apparatus (100) and method. The decoder apparatus (100) comprises a likelihood estimator (101) which generates a sequence of bit value likelihood estimates, such as log likelihood ratios, for multi bit symbols of a data sequence. The decoder apparatus (100) further comprises a decoder element (103), such as a Maximum A Priori (MAP) or appropriate Soft Output Viterbi decoder. The decoder element (103) generates a decoded data sequence in response to the bit value likelihood estimates. The decoder apparatus (100) also comprises a weighted processor (105) which generates a weighted compensation data sequence from the decoded data sequence. The weighted compensation data is used to modify the sequence of bit value likelihood estimates. The decoding is subsequently repeated using the improved bit value likelihood estimates whereby improved decoding performance is achieved. The invention may be applied to a two decoder element decoding apparatus (300) and may specifically be applied to turbo decoders.

A Viterbi decoder includes an ACS unit that performs state metric updates for every symbol cycle. State metric updates involve adding the state metrics corresponding to a likely input symbol to the respective branch matrix, comparing the results of the additions to determine which is smaller, and selecting the smaller result for the next state metric. The ACS unit includes two parallel adders followed by a parallel comparator that generates a multiplexer-select signal. The outputs of the parallel adders are input into a multiplexer and the multiplexer-select signal is input into the multiplexer for a decision.