2910 results about "Multiplexer" patented technology

The invention requests to protect a multifunctional FFT (Fast Fourier Transform) hardware acceleration architecture capable of configuring software in real time, which comprises a first sample sequence rearrangement module, a first calculation unit, a second sample sequence rearrangement module, a second calculation unit, a third sample sequence rearrangement module, a butterfly operation circuit, a multiplexer and a dual-port RAM (Random Access Memory) which are sequentially connected end to end, in order to solve the technical problems that in an existing FFT hardware architecture, the operation length is fixed, the function is single, the fftshift function is lacked, and software dynamic configuration cannot be achieved, through software and hardware collaborative design, FFT hardware has operation flexibility, functional diversity and frequency spectrum processing capacity; the method can be widely applied to various digital signal processing scenes such as communication, images, radars and audios.

The invention belongs to the technical field of storage and calculation integration, and particularly relates to a low-bit-width and high-energy-efficiency floating point storage and calculation integrated circuit based on a partial pre-alignment framework. The circuit comprises a memory array, a pre-calculation unit, an adder tree, a configurable arithmetic unit and a normalization unit, and supports mixed precision operation of FP8MACFP4 and FP8MACFP8. The method is characterized in that a partial pre-alignment strategy dominated by an activation value is adopted, the maximum index of the activation value is dynamically counted, the mantissa of the maximum index is aligned, and multiple partial pre-alignment intermediate results are pre-calculated and latched for reuse; in combination with a customized lookup table and a multiplexer, a pre-calculation result is directly selected to replace real-time multiplication and displacement; and through the reconfigurable hardware, the FP8MACFP8 high-precision operation is realized by utilizing the FP8MACFP4 unit combination. According to the method, complete online floating point multiplication and addition operation is realized, and excellent energy efficiency ratio and operation speed are obtained while high precision is kept.

Aspects of this disclosure relate to a bulk acoustic wave resonator and an integrated capacitor. In certain embodiments, the integrated capacitor can be a metal-insulator-metal capacitor in parallel with the bulk acoustic wave resonator. The metal-insulator-metal capacitor can include a portion of a first electrode and a portion of a second electrode of the bulk acoustic wave resonator. At least part of the metal-insulator-metal capacitor is positioned laterally relative to an acoustic reflector of the bulk acoustic wave resonator. Other embodiments of capacitors integrated with a bulk acoustic wave resonator are disclosed. Related filters, multiplexers, radio frequency modules, radio frequency systems, wireless communication devices, and methods are disclosed.

The global event monitoring unit (100) comprises, characterized in that, an accumulator module (110) which comprises at least one mode to receive an input signal for at least one event, a logger module (120) to measure time interval for said at least one event, and a handler module (132) to enable generation of interrupts for the at least events logged by the logger module (120). The handler module (132) is shown within the logger module (120) but the same is possible to be separate. The at least one mode comprises a Port signal Block (102), internal signal Multiplexer (Mux) block (104), a Module Special Function Register (SFR) block (106) and a host (Central Processing Unit (CPU)) (108). The timing measurement between global events is performed precisely along with optimization of the system response time using the measurement results and the system performance evaluation becomes easy and effective.

A filter multiplexer for variable bandwidth annealing selection is described. The filter multiplexer has multiple pathways, where each pathway comprises a switch and a filter. Each filter has a different cutoff frequency from the other filters. Switches may be cryogenic switches. Each pathway may be communicatively coupled to an external annealing line. Upon receiving a problem, an annealing bandwidth can be selected, set or configured via the multiplexer to operate a quantum processor with a desired annealing schedule. The multiplexer may be used for calibration of a quantum processor by performing a calibration with a large annealing bandwidth, then calibrating the quantum processor by iterating through all available annealing bandwidths from the multiplexer.

A stream of photons from an optical source at a source wavelength are converted into entangled photon pairs via a spontaneous parametric down-conversion process. This produces time-synchronized signal and idler photon pairs which share a nominal wavelength, twice the source wavelength, a common polarization. The signal and idler individually have wavelengths that are equally offset above and below their nominal wavelength. The photons segregated into two paths based on wavelength via a wavelength division multiplexer. A phase modulator in the signal path alters the phase of the signal photon, while the idler photon's phase remains unchanged. By applying a modulation signal to the phase modulator, a quantum message is encoded on the photon pair. A multi-channel wavelength division multiplexer may be used to support multiple channels, each carrying signal-idler pairs conveying a quantum encoded message.

An electronic device of the disclosure includes a plurality of electronic units. Each of the plurality of electronic units includes a pixel circuit and a plurality of tunable circuits. The plurality of tunable circuits is coupled to the pixel circuit. The pixel circuit includes at least one scan transistor, a plurality of de-multiplexer transistors, and a plurality of storage capacitors. The plurality of de-multiplexer transistors is coupled to the at least one scan transistor. The plurality of storage capacitors is coupled to a data line through the at least one scan transistor and the plurality of de-multiplexer transistors.

Disclosed is a display panel in which a ratio of a plurality of areas capable of independently controlling a viewing angle in a display area may be adjusted. The display panel includes pixel blocks including subpixels and multiplexer circuits disposed in a bezel area and individually connected to the pixel blocks. The multiplexer circuits supplies first and second mode control signals to any one of the pixel blocks. The subpixels include a first light-emitting element connected to a driving transistor through a first mode control transistor controlled by the first mode control signal, a second light-emitting element connected to the driving transistor through a second mode control transistor controlled by the second mode control signal, a first lens area disposed on the first light-emitting element, and a second lens area disposed on the second light-emitting element.

The invention provides a communication device, a communication method, a communication system, electronic equipment and a storage medium, which are applied to the technical field of communication and are used for solving the problem that the coverage range and the antenna gain of an existing intelligent antenna cannot meet the use requirements of different use environments. The communication device comprises a multiplexer and a plurality of antenna structures. The multiplexer comprises a common end and a plurality of selection ends. The common end of the multiplexer is coupled with one radio frequency channel, and the common end is used for being switched and conducted with different selection ends in the plurality of selection ends to form a plurality of paths. The multiple antenna structures comprise phased-array antennas, the multiple selection ends comprise first selection ends, and the phased-array antennas are coupled with the first selection ends. The plurality of antenna structures further comprise an omnidirectional antenna, the plurality of selection ends further comprise a second selection end, the omnidirectional antenna is coupled with the second selection end, and / or the plurality of antenna structures further comprise a directional antenna, the plurality of selection ends further comprise a third selection end, and the directional antenna is coupled with the third selection end.

A frontend circuit includes a wide-band filter, a transmit filter, and switches. The wide-band filter passes both the receive frequency band of a first communication frequency band and that of a second communication frequency band which is close to or overlaps that of the first communication frequency band. The transmit filter passes the transmit frequency band of the first or second communication frequency band. The switches are capable of simultaneously bringing, into conduction, at least two of multiple filters including the wide-band filter and the transmit filter. In carrier aggregation using the receive frequency bands of the first and second communication frequency bands, the switches simultaneously bring the wide-band filter and the transmit filter into conduction. Thus, in carrier aggregation using signals of multiple communication frequencies simultaneously in communication, attenuation of signals due to signal leakage in two receive frequency bands, which are close to each other, is suppressed.

The invention discloses a high-tolerance synchronous dual-band pulse laser, and relates to the field of lasers, and the laser comprises a first resonant cavity and a second resonant cavity; the first resonant cavity comprises a first pumping source and an optical annular cavity formed by sequentially connecting a first wavelength division multiplexer, a first thulium-doped optical fiber, a first optical coupler, a first isolator, a second wavelength division multiplexer, a high-nonlinearity saturable absorber, a third wavelength division multiplexer and a first polarization controller; the second resonant cavity comprises a second pumping source and an optical annular cavity which is formed by sequentially connecting a fifth wavelength division multiplexer, a second erbium-doped fiber, a second optical coupler, a second wavelength division multiplexer, a high-nonlinearity saturable absorber, a third wavelength division multiplexer, an electric control adjustable delay line, a fourth wavelength division multiplexer, a second polarization controller and a second isolator, and the fifth wavelength division multiplexer, the second erbium-doped fiber, the second optical coupler, the high-nonlinearity saturable absorber, the third wavelength division multiplexer, the electric control adjustable delay line, the fourth wavelength division multiplexer, the second polarization controller and the second isolator; and the first optical coupler and the second optical coupler respectively output synchronization pulses in the wave bands of 2 microns and 1.5 microns. The device is compact in structure, low in manufacturing cost, convenient to operate and capable of covering the mid-infrared band of 2 microns.

A TE based on polymer optical waveguide 10 ‑TE 00 / TE 20 ‑TE 10 This compact mode converter belongs to the field of photonic integration technology. It consists of a substrate, a lower cladding, a core waveguide, and an upper cladding. The core waveguide is covered by the upper cladding. The lower and upper claddings are EpoClad, and the core waveguide is EpoCore, with the same height. It is constructed by sequentially connecting an input straight waveguide, a first intermediate asymmetric tapered waveguide, a second intermediate asymmetric tapered waveguide, a third intermediate asymmetric tapered waveguide, a fourth intermediate asymmetric tapered waveguide, a fifth intermediate asymmetric tapered waveguide, an output symmetric tapered waveguide, and an output straight waveguide. When passing through the intermediate asymmetric tapered waveguide, different mode components propagate with different effective lengths, causing different phase changes, ultimately resulting in the target mode. This increases channel transmission capacity and can be used in mode add / drop multiplexers (MADMs) and high-order mode filters.

The invention discloses an anti-radiation hardening digital controlled oscillator, a clock data recovery circuit and equipment, and the digital controlled oscillator is characterized in that an anti-radiation hardening circuit unit is connected between a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO), and comprises a voltage copying unit and a multiplexer; the voltage copying unit is used for copying a control voltage signal output by the digital-to-analog converter DAC, generating a copying voltage signal, sending the copying voltage signal to the multiplexer, and switching the output of the multiplexer from the control voltage signal to the copying voltage signal when the digital-to-analog converter DAC is subjected to single-particle bombardment. The DCO type clock data recovery circuit aims at solving the problem that a traditional DCO type clock data recovery circuit is prone to being affected by single particles when running in a radiation environment, single particle function interruption is generated, and consequently a space task fails, and the radiation hardening capacity of the DCO type clock data recovery circuit running in the radiation environment is improved.

The invention provides a UCIe standard protocol layer data transmission circuit, a related method and a chip, and the circuit comprises a slicing circuit which is configured to segment a data packet from a service port; sending the slice frame and slice description information associated with the slice frame to a framing device; the framing device is configured to fill a flow control unit Flit with the slice frames from the slice devices and slice description information associated with the slice frames, and send the Flit to the deframing device; the frame deframer is configured to determine slice frames belonging to the same service port from the Flit, and send the slice frames and slice description information associated with the slice frames to a packing circuit corresponding to the service port; and the packing circuit is configured to splice the data slices belonging to the same data packet in the slice frame based on the slice description information and output the data packet. The technical problem that extra delay is introduced due to beat insertion due to the fact that large multiplexers need to be introduced in existing protocol layer data transmission of the UCIe standard is solved.

Devices, systems, and methods for sharing an image sensor data stream with an active alignment subsystem are provided. An example device includes an image sensor coupled to a first processor. The first processor is coupled to a multiplexer and the image sensor. The first processor is configured to receive an image stream from the image sensor, transmit the image stream to a second processor via the multiplexer operating in a first state, and transmit the image stream to at least one test port of the data capture device via the multiplexer operating in a second state. The multiplexer is configured to connect the second processor to the first processor when operating in the first state, and connect the at least one test port to the first processor when operating in the second state. Responsive to receiving an enable signal, the multiplexer operates in the second state, else the first state.

The invention discloses a scanning high-resolution double-optical-comb spectrum system based on Raman gain modulation. The method is suitable for real-time spectrum detection with a wide spectrum range and high spectral resolution. The system comprises a single-frequency laser and driver, an optical coupler, a mode-locked laser, a rare earth doped amplifier, a wavelength division multiplexer, a Raman gain fiber, a sample to be tested, a photoelectric detector, a data processor and a wavemeter. The single-frequency laser couples part of light to the wavemeter, and the remaining light is divided into two paths to be coupled with the two amplified mode-locked lasers to enter the Raman gain optical fiber for Raman gain modulation and is converted into high-mutual-dryness double optical combs. The double combs pass through a to-be-measured sample in a combined manner, and interference signals are measured by the photoelectric detector and received by the data processor. And meanwhile, the processor sends a tuning signal to the single-frequency laser driver, so that the double combs scan in a wide spectrum range to obtain high-resolution spectrum information. Electrical feedback locking is not needed, and high-precision spectrum acquisition with megahertz resolution in a terahertz range can be completed within a few minutes.

The invention relates to the technical field of optical fiber transmission, and discloses a bidirectional optical fiber transmission system. Comprising a first wavelength division multiplexing / demultiplexing device, a second wavelength division multiplexing / demultiplexing device, a first power amplifier, a second power amplifier, a first preamplifier, a second preamplifier, a first optical fiber switching module, a second optical fiber switching module, a first filter, a second filter, a third filter and a fourth filter. The first optical fiber switching module and the second optical fiber switching module are provided with a first optical fiber or a second optical fiber for transmitting optical signals; according to the technical scheme, automatic switching to the standby optical fiber link is supported when the single optical fiber link fails or the performance is reduced, shunting and combining of wave band signals are achieved through the filter, and the stability and the anti-interference capability of transmission signals are ensured.

The invention discloses a multi-channel high-speed low-power-consumption successive approximation analog-to-digital converter, system and method, and relates to the technical field of analog integrated circuit design, the analog-to-digital converter comprises an M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer and a digital error correction circuit, an M-bit non-binary digital code is obtained through quantization of the auxiliary ADC, and the N-bit non-binary digital code is obtained through quantization of the N-bit main ADCs. A group of N-M-bit non-binary digital codes are obtained through quantization of multiple paths of main ADCs respectively, then combination and binary conversion are carried out on M-bit non-binary digital codes and each group of N-M-bit non-binary digital codes through a digital error correction circuit, n groups of binary digital codes are obtained and output, and multi-channel sampling, quantization, conversion and output are achieved. The device has the characteristics of low power consumption, high conversion speed and high precision, and the conversion speed and precision can be improved while the characteristic of low power consumption is maintained.

Aspects of this disclosure relate to bulk acoustic wave devices that include a first electrode, a second electrode, and a piezoelectric layer having a recess outside of the active region of the bulk acoustic wave device. The first electrode and the second electrode overlap and are on opposing sides of the piezoelectric layer throughout the active region. Related acoustic wave filters, multiplexers, radio frequency modules, radio frequency systems, wireless communication devices, methods of manufacture, and methods of filtering are disclosed.

The invention discloses a memory pooling system, a control method thereof, a power-on method, a power-on device and electronic equipment, and relates to the technical field of computers, through a multiplexer dynamic selection mechanism of a memory expansion unit, a first management link of a controller module for managing a memory buffer or a second management link of the controller module for managing a memory card is constructed, and the memory expansion unit is used for storing the memory. An external device to be expanded does not need to participate in memory device management, under the condition that the number of physical pins is limited, large-capacity memory expansion can be achieved only by connecting a memory buffer and a memory card, a memory board forms a pooling resource pool for capacity expansion by configuring the memory card, meanwhile, a multiplexer efficiently multiplexes a limited signal channel of the switching module, and the expansion efficiency is improved. The controller module can intelligently switch management paths according to instruction attributes, and finally the to-be-expanded device breaks through the limitation of physical pins and synchronously obtains the large-capacity and high-bandwidth memory expansion capacity.

The present invention describes an artificial intelligence (AI) enabled electroencephalography (EEG) system that integrates Pathway Hierarchical Adaptive Referencing (PHAR) for localized signal detection, large language models (LLMs) for automated EEG reporting, and Internet of Medical Things (IoMT) connectivity for adaptive neuromodulation control. The system can also deliver transcranial electrical stimulation (tES) pulses and function as an electrical impedance tomography (EIT) system. PHAR employs a multi-layered multiplexer hierarchy and adaptive referencing topologies to optimize EEG signal acquisition and spatial resolution. LLM integration enables automated generation of human-readable EEG reports. IoMT connectivity allows closed-loop neuromodulation, where real-time EEG analysis guides the adjustment of stimulation parameters. The system can deliver tES pulses and perform EIT expands its functionality, allowing for targeted neuromodulation and impedance-based brain imaging. This integrated system revolutionizes EEG-based diagnostics, treatment, and research in neurology and neuroscience, offering a comprehensive and versatile tool for understanding and modulating brain function.

An optical switch comprising: a set of first input ports. each first input port configured to transport an optical signal having at least one component frequency channel: a set of first output ports. each first output port configured to transport an optical signal having at least one component frequency channel: a first programmable deflection plane configured to deflect beams incident on it to form a first deflected array of beams: a second programmable deflection plane configured to deflect beams incident on it to form a second deflected array of beams: a first demultiplexer configured to separate light from the set of first input ports into its component frequency channels to form the beams incident on the first programmable deflection plane: a first multiplexer configured to combine the second deflected array of beams from the second programmable deflection plane into combined signals incident on the set of first output ports: and a beam steering optical element group configured to transfer the first deflected array of beams from the first programmable deflection plane to the beams incident on the second programmable deflection plane. The incidence normal of the first programmable

The invention relates to the technical field of electronic circuits, in particular to a filter circuit, a voltage filter control circuit, a chip and electronic equipment. The filter circuit comprises a counter, a first data selector, a digital operation circuit and a register, the counter is used for receiving the counting enable signal, outputting a counting mark value to the first data selector, determining a corresponding current logic operation mode according to the current counting mark value, and performing logic operation on the intermediate input parameter according to the current logic operation mode to obtain a first voltage error value after filtering processing; by adopting the filter circuit provided by the invention, required logical operation can be completed by virtue of the first data selector and the digital operation circuit, so that the first voltage error value is output, and the filtered voltage signal is adjusted according to the first voltage error value, so that the set frequency component in the output voltage signal is filtered out; in this way, complex filter coefficients do not need to be configured, a processor with higher computing power does not need to be used, and hardware cost is saved.

Apparatus, systems, and methods for systems and methods for data signal multiplexing may be provided. According to an aspect a method for data signal multiplexing may be provided. The method includes interleaving, by a first 4-to-1 (4:1) multiplexer (MUX), a first set of four analog signals received from a first group of 4 Digital-to-Analog Converters (DACs) to generate a first interleaved analog output. The method may further include interleaving, by a second 4:1 MUX, a second set of four analog signals received from a second group of 4 DACs to generate a second interleaved analog output. Each of the first and the second interleaved analog output may be based on a first 8-unit interval (UI) window including four consecutive 2 UI windows. The method may further include interleaving, by a 2:1 MUX, the first interleaved analog output and the second interleaved analog output to generate a combined interleaved analog output.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

The invention belongs to the technical field of electronic circuits, and particularly relates to an oscillator circuit for a PWM controller. Comprising an oscillator module which comprises a feedback loop and a current detection circuit; the hiccup module is used for gating and outputting an input signal by a data selector according to the level of the input PWM logic control signal so as to control the on-off of a transmission gate, establishing a charging and discharging process and providing a delay starting function for the oscillator module; and the jittering frequency module outputs current sources Iref0 of different sizes by performing combined gating on a current source I'ref and current sources I1-I4, outputs four paths of current sources Iref1-Iref4 of different sizes through a current mirror array mirror image, and provides charging and discharging current for the oscillator module and the hiccup module. By dynamically adjusting the PWM frequency, the switching frequency is matched with the load requirement, the invalid switching frequency is reduced, and the power consumption is greatly reduced.

To provide an acoustic wave device suppressing an area, where an acoustic wave element can be formed, from becoming smaller.SOLUTION: An acoustic wave device 100 includes: a support substrate 10; a piezoelectric layer 11 provided on the support substrate 10; an acoustic wave element 20 provided on the piezoelectric layer 11; a frame body 30 provided, on the support substrate 10, to surround the acoustic wave element 20 as viewed from the top of the piezoelectric layer 11; a lid 40 provided on the frame body 30 while sandwiching a gap 15 together with the support substrate 10, and sealing the acoustic wave element 20 in the gap 15; and a columnar body 50 which is provided between a lower surface 41 of the lid 40 and an upper surface 17 of the piezoelectric layer 11 within the gap 15 and in which a space 16 that is a gap between the lower surface 41 of the lid 40 and the columnar body is formed.SELECTED DRAWING: Figure 1

The invention discloses a data sorting device and method, a chip, electronic equipment and a storage medium, and the device comprises a controller which is used for obtaining a plurality of first data groups; a parity sorting network for sorting the first data set into a second data set; the data selector is used for acquiring a target data group; the controller is used for comparing the target data set with the ith second data set at an interval of N bits to obtain an (i-1) th third data set; when the TopN is sorted, the double-adjustment merging network is used for sorting the (i-1) th third data group into the (i-1) th fourth data group; when i is equal to the number of the plurality of first data groups, taking the (i-1) th fourth data group as a TopN sorting result; and during full sorting, the double-adjustment merging network is used for carrying out iterative merging on the sorted fourth data group to obtain a full sorting result. The method can be compatible with TopN and a dual-tone full-sorting algorithm, and saves computing resources.

According to the distributed fiber grating sensor provided by the invention, the optical pulse and the broadband laser are emitted in a time-sharing manner through the integrated composite light source module, and the cooperative monitoring of Raman scattering temperature measurement and Bragg grating stress measurement is realized on the same sensing optical fiber in combination with the optical path design of the wavelength division multiplexer and the optical circulator. According to the scheme, the high-temperature adaptability of the Raman scattering effect, namely a stable linear relation between molecular vibration frequency shift and temperature, is utilized, signals and stress are completely decoupled, the problem of cross sensitivity of a traditional single sensor is avoided, and independent measurement can be achieved without temperature compensation; meanwhile, a distributed measurement mode enables the sensor to still perform high-precision synchronous monitoring on temperature and stress in a high-temperature environment of 600-900 DEG C, so that the measurement process in an industrial complex scene is simplified, and the system reliability is improved.

A multiplexer includes first and second filters, a resin layer, and an electrically conductive layer. A pass band of the first filter is different from a pass band of the second filter. The first filter is in contact with an electrically conductive layer, and the second filter is not in contact with the electrically conductive layer. The second filter has a greater thermal resistance value than the first filter, and lowers the pass band in response to a temperature rise. A region of the piezoelectric substrate closer to the first filter is a first region, and a region of the piezoelectric substrate farther from the first filter is a second region. Areas in the first and second regions where an acoustic wave resonator included in a parallel-arm circuit is provided are first and second areas. The second area is greater than the first area.