5069 results about "Multiplexer" patented technology

Aspects of this disclosure relate to a bulk acoustic wave device that includes a multi-layer raised frame structure. The multi-layer raised frame structure includes a first raised frame layer positioned between a first electrode and a second electrode of the bulk acoustic wave device. The first raised frame layer has a lower acoustic impedance than the first electrode. The first raised frame layer and the second raised frame layer overlap in an active region of the bulk acoustic wave device. Related filters, multiplexers, packaged modules, wireless communication devices, and methods are disclosed.

The invention discloses a transmitter equalization driving circuit and a method for processing a signal to be transmitted. The circuit comprises a serialization and retiming module used for generating multiple paths of parallel data based on a signal to be transmitted; the data selector module is connected with the serialization and retiming module and used for receiving the clock signal corresponding to each path of parallel data and generating process data including front tap data, main tap data, first rear tap data and second rear tap data based on the parallel data and the clock signal; the pulse generation module is connected with the data selector module and is used for receiving the process data to generate a front tap equalization pulse and a first rear tap equalization pulse; and the hybrid equalization driving module is connected with the pulse generation module and the data selector module, and is used for receiving the front tap data, the front tap equalization pulse, the main tap data, the first rear tap equalization pulse and the second rear tap data to generate an output signal of the signal to be transmitted. The circuit can improve the signal quality of the output signal.

The invention relates to an all-fiber sub-hundred femtosecond laser based on an SESAM. The all-fiber sub-hundred femtosecond laser comprises the SESAM, a wavelength division multiplexer, a pumping source, a pumping protector, a gain fiber, a chirp fiber bragg grating, an isolator, a reflector, a compression unit and an autocorrelator. According to the invention, the chirp fiber bragg grating with the dispersion amount of 0.115 ps / nm is adopted to compensate positive dispersion in the cavity, so that mode-locked pulse with the spectral width of 23nm is realized. A transmission-type diffraction grating pair is adopted, the pulse width is compressed to 88fs, and the maximum spectral width 27nm is obtained under the dispersion of 0.00087 ps2 in a near-zero cavity. The condition that the optimal spectral bandwidth of the optimal seed source pulse based on the optical fiber chirped pulse amplification laser should be larger than 15 nm is met, and the compression pulse distortion of the amplifier is reduced. By adopting the linear cavity, the SESAM is adhered to the surface of the single-mode optical fiber patch cord for starting mode locking, so that an all-optical-fiber structure of the system is realized, and the single-mode optical fiber patch cord is suitable for industrial integrated application.

The invention discloses a multi-sideband chirp modulation DAS system and a working method thereof, and relates to the technical field of distributed sound wave sensing. The DAS system comprises a narrow linewidth laser, an optical fiber coupler, a phase modulator, an electro-optical modulator, an erbium-doped optical fiber amplifier, an optical fiber circulator, a dense wavelength division multiplexer, a photoelectric balance detector, a data acquisition card, an arbitrary waveform generator, a direct current source and the like. The phase modulator is used for modulating constant-amplitude multi-frequency continuous light, the frequency number of light waves is related to the harmonic number of a microwave modulation signal, the frequency interval is determined by the fundamental frequency of the microwave modulation signal, the continuous light frequency can be flexibly modulated by adjusting the microwave modulation signal, and the modulation bandwidth is large; detected beat frequency signals are compressed into single-frequency signals through pulses, phase information of the single-frequency signals is demodulated, vibration signals along the sensing optical fiber can be detected, the spatial resolution of the system depends on the chirp frequency sweeping range, and the spatial resolution is high.

An application specific integrated circuit (ASIC) for computing a convolutional neural network (CNN) has a first input bus that receives a stream of ordered values from an array, each location in the array having one or more channels, and a plurality of kernel processing blocks that receive inputs through a configurable multiplexer. The arrangement and connection of the kernel processing blocks and the bus enable the ASIC to operate as a pipeline system and transmit the output stream in a manner synchronized with the input stream.

A system and method for in-memory image processing. In some embodiments, a system includes a memory, a first neuron processing circuit, and a second neuron processing circuit. The first neuron processing circuit may be connected to a first plurality of bit lines of the memory, and the second neuron processing circuit may be connected to a second plurality of bit lines of the memory. The first neuron processing circuit may include a plurality of configurable processing circuits, each of the configurable processing circuits including: an artificial neuron for calculating the sign of a weighted sum of a plurality of single-bit digital input signals at respective inputs of the artificial neuron, and a plurality of multiplexers, each having an output connected to a respective input of the inputs of the artificial neuron.

The invention relates to a firmware upgrading method, a computer program product, equipment and a storage medium. The method comprises the steps that in response to a received first firmware upgrading signal, the state of a first link is obtained, and the first link conducts a main control chip and an external chip of the main control chip; if the first link is in the idle state, locking the first link, and returning a second firmware upgrading signal to the substrate management controller; in response to a second firmware upgrading signal received by the substrate management controller, the substrate management controller controls the main control chip to send a first control signal to the multiplexer so as to control the multiplexer to be switched to a second link, and the substrate management controller and an external chip of the main control chip are conducted through the second link; and the substrate management controller obtains a configuration file in the plug-in chip through the second link to carry out firmware upgrading, wherein the configuration file comprises a burning code. By adopting the method, the reliability of firmware upgrading can be improved.

A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.

The invention discloses a number-theory transformation structure of concurrency constant geometry, which uses two polynomial storage blocks to store polynomials, namely a left storage block MembL and a right storage block MembR, each of the left storage block MembL and the right storage block MembR consists of four 1024 * 24 single-port SRAMs (Static Random Access Memory), and n is an integer multiple greater than or equal to 16; and parallel computing of the two butterfly arithmetic units is realized through the four multiplexers, and position transformation of input and output data of the BFU is controlled. To be compatible with multiple algorithms, there is a need for an additional number-theoretical transform constant memory to store a pre-computed twiddle factor to provide a required twiddle factor access bandwidth. According to the method, data independence between polynomial storage blocks is utilized, a modular arithmetic unit of a two-concurrence BFU is designed, and the polynomial multiplication performance is improved by more than one time under the condition that the area increase is limited.

The invention relates to an optical fiber communication sensing integrated architecture and a working method thereof. Comprising a sensing system laser, a coupler, a polarization beam splitter, a semiconductor optical amplifier, a polarization multiplexing communication transmitting system, a polarization wavelength two-dimensional demultiplexer, namely a WDM-PM device, a coarse wavelength division multiplexer MMI-WDM, a single-mode fiber, a polarization multiplexing communication receiving system, a polarization diversity double-balanced photoelectric detector PBPD, and an ROTDR and phi OTDR data processing unit. According to the invention, not only can high-capacity and long-distance communication under fusion of polarization multiplexing and wavelength division multiplexing be realized, but also sensing and communication can be fused through a wavelength division multiplexing system, the quality of sensing signals is improved through polarization diversity reception on the basis, and mutual promotion of communication and sensing is realized.

Techniques for fully homomorphic encryption are described. In some examples, a register file to store polynomials is coupled to a butterfly compute path. The butterfly compute path includes a multiplier coupled to a first input and a second input to multiply the first and second input to, when enabled, generate a multiplication output, a first multiplexer coupled to an output of the multiplier and to the first input to output a selection between the output of the multiplier and the first input, an adder to add, when enabled, a third input to the selected output of the first multiplexer, a subtractor to subtract, when enabled, an output of the multiplier from the third input, and a second multiplexer coupled to an output of the multiplier and to the first input to, when enabled, output a selection between the output of the multiplier and the subtractor.

The invention relates to the technical field of filters, in particular to a dual-mode resonator and a dual-mode filter. The dual-mode resonator comprises a metal cavity and a medium resonance body; the number of the metal cavities is two, and the two metal cavities are arranged on the two opposite sides of the medium resonance body respectively. The opening end of the metal cavity faces one end of the dielectric resonator; a conducting ring is arranged between the metal cavity and the dielectric resonant body, and the metal cavity and the conducting ring form a resonant cavity. The dual-mode filter comprises a first resonator and a second resonator; the first resonator is a dual-mode resonator; the first resonator and the second resonator are connected in series through a coupling structure. The conducting rings and the metal cavities are arranged on the two opposite sides of the dielectric resonance body, the conducting rings and the metal cavities form the resonance cavities, and the dual-mode resonance effect is achieved. The overall size is small, the space utilization rate is high, and production is easy.

An optical module includes a base, a first cover, a circuit board, a light emitting assembly and a light receiving assembly. Part of the circuit board is arranged on a surface of the base, and part thereof arranged outside the base. The light emitting assembly includes a plurality of light-emitting chips disposed on the base and an optical multiplexer disposed on the first cover and located in a laser exit direction of the plurality of light-emitting chips. The light receiving assembly includes an optical demultiplexer disposed on the first cover, a plurality of light-receiving chips disposed on the circuit board and are located in a laser exit direction of the optical demultiplexer, a reflection prism disposed at a side of the plurality of light-receiving chips away from the circuit board, and an optical receiving case covering the plurality of light-receiving chips and the reflection prism.

The invention requests to protect a multifunctional FFT (Fast Fourier Transform) hardware acceleration architecture capable of configuring software in real time, which comprises a first sample sequence rearrangement module, a first calculation unit, a second sample sequence rearrangement module, a second calculation unit, a third sample sequence rearrangement module, a butterfly operation circuit, a multiplexer and a dual-port RAM (Random Access Memory) which are sequentially connected end to end, in order to solve the technical problems that in an existing FFT hardware architecture, the operation length is fixed, the function is single, the fftshift function is lacked, and software dynamic configuration cannot be achieved, through software and hardware collaborative design, FFT hardware has operation flexibility, functional diversity and frequency spectrum processing capacity; the method can be widely applied to various digital signal processing scenes such as communication, images, radars and audios.

Aspects of this disclosure relate to acoustic wave filter. The acoustic wave filter can include different types of acoustic wave resonators. The acoustic wave filter can include shunt acoustic wave resonator that has lower second harmonic distortion than other acoustic wave resonators of the acoustic wave filter. In certain embodiments, the shunt acoustic wave resonator can be a surface acoustic wave resonator. Related multiplexers, radio frequency modules, wireless communication devices, and methods are also disclosed.

The invention provides a multiplexer and a detector. The multiplexer comprises a dielectric substrate, a connecting structure and a plurality of band-pass filters with different working frequencies. A conductive film layer is arranged on the plane of one side of the dielectric substrate and comprises a signal line and a grounding plate located on the side edge of the signal line. The connecting structure is arranged on the conductive film layer and comprises a main branch and a plurality of branches, and the main branch is connected with the branches and serves as an input port of the multiplexer. And the plurality of band-pass filters with different working frequencies are connected with the signal line and the grounding plate. Each band-pass filter comprises a first port and a second port, the first port is connected with the corresponding branch, and the second port serves as an output port of the multiplexer. The signal line, the grounding plate, the connecting structure and the band-pass filter can be located on the same side plane of the dielectric substrate, metal loss and radiation loss are reduced, and integration with other components of the detector is facilitated.

The invention belongs to the technical field of storage and calculation integration, and particularly relates to a low-bit-width and high-energy-efficiency floating point storage and calculation integrated circuit based on a partial pre-alignment framework. The circuit comprises a memory array, a pre-calculation unit, an adder tree, a configurable arithmetic unit and a normalization unit, and supports mixed precision operation of FP8MACFP4 and FP8MACFP8. The method is characterized in that a partial pre-alignment strategy dominated by an activation value is adopted, the maximum index of the activation value is dynamically counted, the mantissa of the maximum index is aligned, and multiple partial pre-alignment intermediate results are pre-calculated and latched for reuse; in combination with a customized lookup table and a multiplexer, a pre-calculation result is directly selected to replace real-time multiplication and displacement; and through the reconfigurable hardware, the FP8MACFP8 high-precision operation is realized by utilizing the FP8MACFP4 unit combination. According to the method, complete online floating point multiplication and addition operation is realized, and excellent energy efficiency ratio and operation speed are obtained while high precision is kept.

Aspects of this disclosure relate to a bulk acoustic wave resonator and an integrated capacitor. In certain embodiments, the integrated capacitor can be a metal-insulator-metal capacitor in parallel with the bulk acoustic wave resonator. The metal-insulator-metal capacitor can include a portion of a first electrode and a portion of a second electrode of the bulk acoustic wave resonator. At least part of the metal-insulator-metal capacitor is positioned laterally relative to an acoustic reflector of the bulk acoustic wave resonator. Other embodiments of capacitors integrated with a bulk acoustic wave resonator are disclosed. Related filters, multiplexers, radio frequency modules, radio frequency systems, wireless communication devices, and methods are disclosed.

The present application relates to the technical field of integrated circuits and relates to a matrix operation apparatus based on a flexible RRAM memory-computing array, and solves the problem in the prior art of the inability to reduce the area of the memory-computing array without affecting the precision. The apparatus comprises: the flexible RRAM memory-computing array for outputting cumulative currents of columns of memory-computing units to a multiplexer (MUX) on the basis of multiple rows of inputs; the MUX for selecting the cumulative current of one column of memory-computing units from among the columns of memory-computing units and sending said cumulative current to an analog-to-digital converter (ADC); the ADC for converting the received cumulative current into a digital signal and sending said digital signal to a subtractor; a popcount module for receiving the multiple rows of inputs, obtaining the number of 1 in the multiple rows of inputs, and outputting the number of 1 to a multiplier; the multiplier for multiplying the number of 1 by a fixed value β and sending a product result to the subtractor; and the subtractor for subtracting the product result from the digital signal to obtain a multiply-accumulate result of the matrix. The present application realizes high-precision memory-computing based on a small-area memory-computing array, further enhances energy efficiency, and can be applied to flexible computing chips to create electronic skin.

An acoustic wave device includes a first substrate, an acoustic wave element provided on a first surface of the piezoelectric layer, a second substrate, a first metal layer provided on the first surface and conductively connected to the acoustic wave element, a second metal layer provided on a second surface of the second substrate, a third metal layer that connects the first metal layer to the second metal layer, is thicker than the first metal layer and the second metal layer, and contains copper or silver, and a first conductive layer that covers a side surface of the third metal layer, and a third surface of the first metal layer in a region surrounding another region where the third metal layer is bonded to the first metal layer, is thinner than the third metal layer, and contains a component other than copper, silver, and tin as a main component.

The global event monitoring unit (100) comprises, characterized in that, an accumulator module (110) which comprises at least one mode to receive an input signal for at least one event, a logger module (120) to measure time interval for said at least one event, and a handler module (132) to enable generation of interrupts for the at least events logged by the logger module (120). The handler module (132) is shown within the logger module (120) but the same is possible to be separate. The at least one mode comprises a Port signal Block (102), internal signal Multiplexer (Mux) block (104), a Module Special Function Register (SFR) block (106) and a host (Central Processing Unit (CPU)) (108). The timing measurement between global events is performed precisely along with optimization of the system response time using the measurement results and the system performance evaluation becomes easy and effective.

The invention provides a stimulated Brillouin spectrum analysis device and method.The device comprises an optical circulator, a stimulated Brillouin medium, a probe light source, a double-sideband IQ modulator, an optical isolator, a dense wavelength division multiplexer, an up-down frequency conversion detector and a data acquisition board card, and light to be detected is injected into the stimulated Brillouin medium through the optical circulator; probe light enters a stimulated Brillouin medium after being modulated by a double-sideband IQ modulator, the modulated probe light and to-be-detected light generate characteristic frequency signals distributed on the two sides of the probe light frequency based on the stimulated Brillouin effect, stimulated Brillouin complex gain is calculated by demodulating light signals collected by an up-down frequency conversion detector, and the stimulated Brillouin complex gain is obtained. And the to-be-measured light information is obtained through inversion. By means of the scheme, high-resolution spectral analysis without scanning can be achieved, dependence on Brillouin frequency deviation in the optical fiber is eliminated, and the real-time performance of stimulated Brillouin spectral analysis is improved.

A PCIe clock detection circuit includes a clock detector, a clock receiver, a counter coupled to the clock receiver, a multiplexer coupled to the counter, and an AND gate coupled to the clock detector and the multiplexer. The clock detector is used to detect amplitude of a clock signal and generate a clock detection signal accordingly. The clock receiver is used to generate a reference clock signal according to the clock signal. The counter is used to generate a counter signal according to the reference clock signal. The multiplexer is used to generate a MUX output signal according to the counter signal and a reference signal. The AND gate is used to generate a clock detection output signal according to the clock detection signal and the MUX output signal.

A filter device includes a filter circuit including first and second terminals and series arm resonators along a series arm connecting the first terminal and the second terminal, and an additional circuit connected in parallel at least some of the series arm resonators. The additional circuit includes first, second, and third interdigital transducer electrodes. The first interdigital transducer electrode is connected to a first node at one end portion of a series arm resonator having a lowest anti-resonant frequency of the series arm resonators, the second interdigital transducer electrode is connected to a second node having a potential different from a potential of the first node, the third interdigital transducer electrode is connected to a third node having a potential different from the potentials of the first and second nodes, and the first and second nodes are closer to the first terminal than the third node.

The invention provides a core particle and a test method thereof, and the core particle comprises a home terminal generator which is used for generating and sending a test code to a sending channel for transmission; wherein one test code is transmitted through one sending channel, and the number of the test codes is the same as that of the sending channels; the home terminal multiplexer is used for receiving the detection code through the receiving channel; wherein one detection code is received through one receiving channel, and the number of the detection codes is consistent with the number of the receiving channels; and the home terminal checker is used for generating a corresponding check code according to the received detection code and checking the corresponding detection code through the check code, if the check is successful, the transmission channel corresponding to the detection code is unobstructed, otherwise, the transmission channel corresponding to the detection code is transmission fault. According to the core particle and the test method thereof provided by the invention, the requirements of a serial transmission test of a single channel and a parallel transmission test of a plurality of transmission channels can be met.

The present invention relates to an ultra-wideband (UWB) radar sensor chip system architecture. The chip system architecture at least comprises N receiving channels and N transmitting channels, wherein N is a positive integer greater than 1, the N receiving channels form receiving links by means of connecting to a receiver multiplexer, the N transmitting channels form transmitting links by means of connecting to a transmitter multiplexer, and the receiving links and the transmitting links jointly form N groups of transceiving systems. The chip system architecture further comprises a serial peripheral interface, and is adjacent to an external main control chip by means of the serial peripheral interface, so as to drive, by means of a control command, the N groups of transceiving systems to operate on the basis of time division or to operate independently. The present invention introduces the concepts of time division multiplexing and multi-channel synthesis into a radar system, and provides a universal UWB radar sensor chip system architecture with a high integration level, a high performance and a low cost, thereby effectively solving the problems of a radar chip in terms of the sensitivity and transmitting power, improving the detection precision and increasing the detection distance.

A filter multiplexer for variable bandwidth annealing selection is described. The filter multiplexer has multiple pathways, where each pathway comprises a switch and a filter. Each filter has a different cutoff frequency from the other filters. Switches may be cryogenic switches. Each pathway may be communicatively coupled to an external annealing line. Upon receiving a problem, an annealing bandwidth can be selected, set or configured via the multiplexer to operate a quantum processor with a desired annealing schedule. The multiplexer may be used for calibration of a quantum processor by performing a calibration with a large annealing bandwidth, then calibrating the quantum processor by iterating through all available annealing bandwidths from the multiplexer.

Various techniques are provided to implement look-up table (LUT) circuits. In one example, a LUT circuit includes a first LUT configured to selectively receive a first input signal and each input signal of a set of input signals and determine a first output signal based on the first input signal and / or an input signal(s) of the set. The LUT circuit also includes a second LUT configured to selectively receive a second input signal and each input signal of the set and determine a second output signal based on the second input signal and / or an input signal(s) of the set. The LUT circuit also includes a multiplexer configured to selectively receive the first and second output signals and a third input signal, and selectively provide, based on the third input signal, the first or second output signal as an output of the LUT circuit. Related systems and methods are also provided.

An optical transmission system (300) includes a reconfigurable optical add-drop multiplexer (ROADM) device (200) that transmits and receives an optical signal via an optical transmission line (10, 20), and a communication device (400) connected to the ROADM device (200) via the optical transmission line (10, 20). The ROADM device (200) includes an SFP for OSC (250) that converts an electrical signal and an optical signal to each other, and transmits and receives the optical signal via the optical transmission line (10, 20). The communication device (400) includes a response unit (420) that returns back to the ROADM device (200) the optical signal transmitted from the ROADM device (200).

The invention discloses a communication optical cable line fault rapid positioning system, which comprises optical time domain reflectometers and a remote monitoring center, and is characterized in that two optical time domain reflectometers with different optical pulse wavelengths are respectively connected to two ends of a communication optical cable line through wavelength division multiplexers on corresponding sides; the optical time domain reflectometer analyzes a reflected light signal received by the optical time domain reflectometer through a built-in intelligent algorithm, quickly calculates the position of a fault point and judges the type of the fault; the intelligent algorithm comprises a loss positioning algorithm, a reflection peak identification algorithm and a microbend loss analysis algorithm; the loss positioning algorithm is used for detecting the position of a fault point and distinguishing an optical fiber breakpoint and a loss type fault; the reflection peak recognition algorithm is used for detecting a fault point position; the microbend loss analysis algorithm is used for detecting and distinguishing microbend loss and other types of loss; the system has the advantages of being stable in detection system, good in detection effect, rapid in fault positioning and more accurate in detection result, and automatic detection, remote detection and remote monitoring and management of optical cable faults can be conveniently achieved.