6658results about "CAD circuit design" patented technology

The invention relates to the field of chip verification, and provides a chip verification method, device and equipment, a medium and a chip. The method comprises the following steps: establishing a dynamic simulation verification environment of a to-be-verified design, and generating a plurality of test scenes and corresponding test excitation according to a design specification definition; sending the test excitation to a driver through a sequencer, converting the test excitation into a signal conforming to a to-be-verified design interface protocol by the driver, and transmitting the signal to the to-be-verified design; the monitor collects an input signal and an output signal of a to-be-verified design in real time, converts the input signal and the output signal into transactions, and transmits the transactions to the scoreboard; comparing the reference model with an output signal of the to-be-verified design to generate a dynamic simulation verification result; according to the dynamic simulation result, the state space is reduced, state space traversal is carried out on a design part which is not covered by dynamic simulation in the design to be verified, and a formal verification analysis result is generated; and evaluating the to-be-verified design according to the formal verification analysis result.

In some embodiments, a configured artificial intelligence system includes a plurality of intelligence models; a scoring system configured to generate know-your-model scores that quantify suitability for specific tasks of each model; a model execution system configured to provide standardized execution environment for the plurality of intelligence models; a training and reinforcement system configured to monitor outcomes relating to decisions or predictions made by the plurality of intelligence models and use outcome data as feedback to reinforce model performance; and a governance and analysis system configured to ensure model operations comply with governance standards. The intelligence controller may be configured to receive task requests, analyze task complexity, decompose tasks into manageable subtasks, and dynamically select appropriate models from the plurality of intelligence models to execute each subtask based on model suitability and performance characteristics.

Systems and methods for training a machine learning model for defect detection include obtaining training data including an inspection image of a fabricated integrated circuit (IC) and design layout data of the IC, and training a machine learning model using the training data. The machine learning model includes a first autoencoder and a second autoencoder. The first autoencoder includes a first encoder and a first decoder. The second autoencoder includes a second encoder and a second decoder. The second decoder is configured to obtain a first code outputted by the first encoder. The first decoder is configured to obtain a second code outputted by the second encoder.

Disclosed in the present invention is a non-autoregressive Transformer-based modeling method for a 4-level pulse amplitude modulation high-speed transmitter. The method involves establishing a deep learning model having an encoder-decoder architecture to predict the behavior of a 4-level pulse amplitude modulation transmitter. An encoder processes unordered non-sequential inputs, including an input signal parameter and link parameters, to generate a context vector and then transmit same to a decoder. The decoder uses both the context vector generated by the encoder and a transmitter output signal sequence to generate a categorical probability distribution for each point in the sequence one by one. The model is trained using a random masking strategy, and inference is performed by means of non-autoregressive decoding and filtering, so that the model can perform parallel prediction on an output sequence, and perform a filtering process to predict an output signal. Compared to traditional simulation methods, the present invention achieves a significant acceleration effect, particularly when processing multi-link systems.

Embodiments of the present disclosure include a software solution for generating a connectivity file that forms the connections between signals in a design under test (DUT) and signals in a verification IP (VIP) interface. The connecting signals from the DUT may form a DUT interface and the DUT interface may follow a protocol. The software solution may utilize a generative AI-based tool to identify example connections that also follow the protocol. These example connections may be included in a query to a large language model (LLM) for purposes of improving the results generated by the LLM.

The invention discloses a circuit netlist generation method supporting deep learning model multi-stage reasoning, and belongs to the technical field of electronic circuit design and automation, and the method comprises the steps: obtaining a circuit diagram image through optical scanning, carrying out the preprocessing of the image, carrying out the recognition of a component through a deep learning model YOLOv5, and determining the boundary frame coordinates and class information. And further performing port fine identification on the component, and determining the position and the direction of the port. And eliminating character interference by using an optical character recognition technology, performing wire recognition, including Hough straight line detection and jumper processing, and determining starting point and ending point coordinates of the wire. And matching the identification results of the components, the ports and the wires, constructing a topological structure of a circuit diagram, finally generating a circuit netlist, and performing error elimination and JSON format output. According to the method, automatic netlist generation of the analog circuit diagram can be realized, the analog circuit diagram file is converted into the netlist file with device function annotations, and the efficiency and quality of circuit design and simulation are improved.

The invention relates to the technical field of ultra-low power consumption microcontrollers, and discloses an ultra-low power consumption microcontroller architecture design method and system, and the method comprises the steps: constructing a heterogeneous dual-core processor comprising a high-performance core and a low-power consumption core, and dividing the heterogeneous dual-core processor into a plurality of independent power domains; constructing a sub-threshold voltage operation system on a plurality of independent power supply domains, and configuring a multi-layer storage structure in the heterogeneous dual-core processor; recording task characteristic data by using a multi-level storage structure, executing task dynamic allocation between dual cores, and creating a dynamic task allocation mechanism; and performing static analysis and function block division on the application code based on a dynamic task allocation mechanism to obtain a plurality of function code blocks, and performing storage hierarchy and processor core allocation on the plurality of function code blocks to obtain a function code allocation result. According to the method, the dynamic migration of the workload and the optimal resource allocation are realized, and the energy consumption of the microcontroller in various working scenes is reduced.

The embodiment of the invention provides a chip design system and method based on multiple agents. The system comprises a plurality of agents, and the following steps are cooperatively executed through the plurality of agents: receiving a design request of a user, and executing the whole chip design processing flow based on chip design demand information included in the design request so as to generate a chip design file (including chip layout information) for subsequent actual chip manufacturing. Visibly, according to the scheme, the intelligent agent based on LLM is applied to chip design full-process exploration, manual participation can be reduced, and the chip design efficiency can be improved.

The invention relates to a modeling and optimizing method for inter-layer signal crosstalk of a PCB (Printed Circuit Board). Frequency response data of all dielectric layers of the PCB under different temperature and humidity conditions are collected, and a mapping model with the temperature gradient and the humidity diffusion gradient as input and the dielectric constant as output is established. And calculating the dynamic distribution of mutual capacitance and mutual inductance under the environment change by combining the spatial layout parameters of the differential signal pair, and constructing a crosstalk sensitivity evaluation model with coupled frequency, environment and layout. And high-risk areas with crosstalk sensitivity caused by environment change are identified, and the crosstalk change rate of each area is quantified. For a sensitive area, a temperature and humidity compensation medium structure is introduced to stabilize local dielectric characteristics and reduce the influence of the environment on crosstalk. And according to the compensated medium distribution, adjusting a differential signal wiring path and impedance matching by adopting an optimization method with the aim of minimizing the crosstalk change rate, and generating a wiring layout with environmental robustness. According to the invention, the signal integrity and the transmission reliability of the multi-layer PCB in a temperature and humidity changing environment can be effectively improved.

The invention relates to the technical field of electronic circuits, in particular to a construction method and system of a high-speed differential signal transmission model. The method comprises the following steps: acquiring design data of the printed circuit board, and extracting differential signal line data; constructing a high-speed differential signal transmission model according to the differential signal line data; performing signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data; identifying a crosstalk source position based on the high-speed differential signal transmission data to obtain a crosstalk source coordinate; detecting via hole dislocation based on the crosstalk source coordinates to obtain via hole dislocation data, and evaluating a heat accumulation degree based on the via hole dislocation data; identifying an electrical fault area of the circuit board based on the heat accumulation degree; and extracting stack structure information according to the printed circuit board design data. Based on the electronic circuit technology, the precision and reliability of the high-speed differential signal transmission model are improved, and the signal transmission quality and the electrical fault detection rate are remarkably improved.

The invention relates to the technical field of PCB detection, and provides a PCB life analysis method based on reliability analysis and related equipment. The method comprises the following steps: performing multi-physics field coupling modeling on a to-be-detected circuit board to obtain a multi-field coupling data set, performing space-time alignment processing on a collected multi-source sensor data set to obtain a fusion monitoring data set, and performing feature extraction according to the multi-field coupling data set and the fusion monitoring data set to obtain a failure sensitive feature matrix; therefore, a dynamic neural network is used for modeling the failure sensitive feature matrix to obtain corresponding life prediction probability distribution data, and the life prediction probability distribution data is adjusted through actual measurement failure data calibration to obtain an accurate life prediction model. And finally monitoring the circuit board to be detected in real time through the life prediction model to obtain real-time life evaluation data. According to the invention, through fusion of multi-physics field coupling and real-time monitoring data, the service life performance of the target in a complex environment can be evaluated more accurately.

The invention belongs to the technical field of connectors and discloses a design method for a low-loss cable connector without resonance points, comprising: designing a spiral gradient groove structure on the surface of an inner conductor based on the impedance continuity principle, establishing a composite gradient impedance theoretical model of the connector, constructing a dielectric constant gradient distribution model of a double insulating layer, and setting a transition function between an inner layer and an outer layer; solving the S parameters and electric field distribution of the connector through electromagnetic-thermal coupling finite element simulation, optimizing the spiral angle θ and the gradient index n, establishing a quantitative model of the surface roughness of the conductor and high-frequency loss, and determining a threshold range of the surface roughness through calculation of the quantitative model; performing global optimization of structural parameters based on a multi-objective genetic algorithm, outputting a theoretical design parameter set and a report collection of performance verification, eliminating the resonance point problem of traditional connectors, and providing excellent low-loss performance in the full frequency band, which is particularly suitable for high-frequency and high-power transmission environments.

The invention belongs to the technical field of integrated circuit design verification, and particularly discloses an SoC performance verification method and device based on dynamic QoS regulation and control, a medium and equipment, and the method comprises the steps: analyzing a chip architecture, and obtaining a chip resource mapping table; constructing an automatic verification environment based on the chip resource mapping table and performing testing; scene parameter configuration is carried out according to a target application scene and based on the chip resource mapping table; and performing dynamic QoS regulation and control based on the configured scene parameters in a tested automatic verification environment so as to verify the performance of the SoC. According to the invention, the accuracy and efficiency of SoC performance verification and the consistency of the result and the actual application scene can be improved.

The invention provides an EDA software and heterogeneous process design rule collaborative verification method, which relates to the technical field of EDA software, and comprises the following steps of: extracting time sequence characteristics in a dynamic association graph through a bidirectional long-short-term memory network, analyzing node coupling strength by utilizing a multi-head graph attention network to generate a hierarchical importance scoring matrix; and outputting a conflict risk tensor and a propagation path prediction map based on a depth rule conflict prediction model, and generating a correction strategy in combination with a variational auto-encoder and a reinforcement learning network. According to the method, design rule conflicts can be accurately predicted and positioned, an effective correction scheme is provided, and the accuracy and efficiency of heterogeneous process design rule verification are improved.

The invention discloses an RISC-V chip multi-core heterogeneous design method and system applied to a power grid, and belongs to the field of artificial intelligence chip design. The design method comprises the steps that a power grid task is input, and data exchange and task scheduling are conducted between an AI core and a CPU core in a self-adaptive mode according to the power grid task; according to data exchange and task scheduling requirements, parallel computing is carried out through the special hardware unit and the optimized instruction set; through dynamic power management, the load is monitored and calculated in real time, and the power states of the AI core and the CPU core are dynamically adjusted; a plurality of parallel communication channels are provided through a network-on-chip NOC communication architecture, and a network topology structure is introduced into a chip, so that communication and data transmission among processing units are realized. According to the method, the extension characteristic of an open source instruction set is fully utilized, hardware design and software design are combined, the operational capability is improved, and the problems of bandwidth bottleneck and delay of a traditional bus architecture in a multi-core system are solved.

The invention discloses an embankment hidden danger detection and early warning method and system based on electric field and electromagnetic field coupling, and the method comprises the following steps: obtaining and processing the resistivity and dielectric constant of an embankment dam body, constructing a joint inversion objective function based on a processing result, and carrying out the detection and early warning of the embankment hidden danger. A joint inversion model is established, a minimum joint inversion objective function is used for solving, a multi-physics field joint inversion result is obtained and used for delineating an abnormal area, a time-shifting resistivity monitoring network is arranged in the area for detection, the seepage velocity is obtained, soil mass mechanical parameters are defined, and the seepage velocity is calculated. And constructing an embankment hidden danger numerical model, using seepage velocities as boundary condition input, simulating embankment dam body stability safety coefficients under different seepage velocities, setting an early warning threshold value, and giving an alarm when the embankment dam body stability safety coefficients reach the early warning threshold value. Through coupling analysis of the earth electric field, the seepage velocity and the like, data multiplicity is effectively eliminated, the defect resolution is remarkably improved, and the misjudgment risk is greatly reduced.

The invention relates to the technical field of integrated circuit manufacturing, in particular to a precise electroplating control system and method for an electroplated layer of a double-layer circuit board, and the method comprises the steps: building a multi-physical field coupling simulation model, and simulating the internal current density and ion concentration distribution of a via hole; constructing a mapping relation between the current density and the side wall electroplating thickness based on a simulation result, and predicting the electroplating thickness; through thickness prediction feedback, a time sequence adjustable pulse current control strategy is designed, the pulse amplitude, the duty ratio and the on-off period are dynamically adjusted, and current distribution optimization is guided; the state of the electroplating process is sensed in combination with real-time monitoring and analysis of multi-source parameters of electrode potential, conductivity and fluid velocity; and based on the prediction model and the real-time parameters, adjusting the pulse waveform and the time sequence through closed-loop compensation. According to the method, the uniformity and controllability of the thickness of the electroplated layer on the side wall of the via hole can be remarkably improved.

The invention discloses a grid-connected inverter parameter optimization method based on an improved genetic particle swarm algorithm. The grid-connected inverter parameter optimization method comprises the following steps: constructing a target function; performing population position initialization; calculating a fitness value of each particle at an initial moment, recording an optimal solution, and storing initial global optimal particle and individual optimal particle information; random disturbance is added to the speed and the position of the particles; updating the speed and the position of the particle; performing multi-point crossover and mutation operation; according to the current optimal solution, carrying out local domain search by adopting a fine search mode based on Laplacian distribution and carrying out global neighborhood search by adopting a search mode based on Cauchy distribution; and checking convergence conditions, if convergence occurs, outputting an optimal solution, and obtaining optimal parameters of the grid-connected inverter system. The method has the remarkable effects that by optimizing three key parameters in a control system and utilizing a nonlinear dynamic strategy to enhance the global search capability and the convergence speed of the algorithm, various defects in the prior art can be overcome.

The invention provides an electromagnetic compatibility test method and system for PCB design, a PCB comprises a schematic circuit diagram and a structural model, and the method comprises the following steps: extracting high-frequency signal characteristics in the schematic circuit diagram to obtain an electromagnetic simulation parameter set; performing multi-physical field coupling modeling according to the electromagnetic simulation parameter set and the structure model to obtain an electromagnetic field-circuit model; performing frequency-time domain hybrid excitation loading on the electromagnetic field-circuit model to obtain an electromagnetic noise distribution diagram; performing gradient descent optimization on layout parameters of the structure model according to the electromagnetic noise distribution diagram to obtain an anti-interference layout scheme; and performing multi-working-condition Monte Carlo simulation and residual error calibration on the anti-interference layout scheme to generate a correction guidance library.

The invention discloses a memory combination screening method, device and equipment and a medium, and relates to the technical field of computers, and the method comprises the following steps: generating all memory files of a system-on-chip according to a preset memory naming rule; storing each memory file to a target memory library, obtaining all memory names based on the register transfer level code and a preset memory naming rule, and generating a memory list based on each memory name; acquiring corresponding physical parameter information from a target memory library based on each memory name in the memory list, and determining target physical parameter information of each memory split combination corresponding to each memory according to the physical parameter information; and screening the memory split combination based on a preset physical information threshold and the target physical parameter information to obtain a screened memory combination. According to the method and the device, the memory list can be quickly and accurately generated, and all combinations meeting constraints are screened out.

The invention discloses a law and regulation simulation test method, device and equipment for an intelligent driving algorithm and a storage medium, and relates to the technical field of intelligent driving, and the method comprises the steps: carrying out the high-precision three-dimensional reconstruction of a law and regulation test site according to collected data, and obtaining a three-dimensional reconstruction scene, and the collected data comprises a laser radar point cloud and a multi-view camera image; obtaining simulation working condition test data based on the three-dimensional reconstruction scene; training a network model according to the simulation working condition test data and the real vehicle working condition test data to obtain a vehicle dynamics network model; and based on an automatic test program, constructing a closed-loop simulation link according to the three-dimensional reconstruction scene and the vehicle dynamics network model, and carrying out regulation simulation test on an intelligent driving algorithm. According to the invention, the efficiency and accuracy of intelligent driving regulation testing can be improved.

The present disclosure provides a verification system, a verification method, an electronic device and a storage medium. The verification system includes a simulation verification device, a first portion and a second portion. The first portion includes a first master module and a second slave module. The second slave module includes a memory unit connected to a memory access interface at a periphery of a design under test. The second portion includes a first direct programming interface, a second direct programming interface, a function library module, and a test case module. The first direct programming interface communicates with the first master module and is configured to call a first function to implement front door access to a register of the design under test. The second direct programming interface communicates with the memory unit and is configured to call a second function to implement back door access to the memory unit.

The present invention relates to the technical field of semiconductor chip production, and provides a chip production simulation method and system based on digital twin technology. The method comprises: collecting a processing task of a target chip and retrieving a corresponding test data set; constructing a corresponding design parameter domain and design function; performing optimization, using digital twin technology to construct a twin chip, testing the twin chip, and calculating the design fitness; performing iterative optimization to acquire an optimal design parameter; constructing an optimal twin chip, calculating the similarity between the optimal twin chip and the existing family chips, and performing verification; and carrying out design and production of the target chip. The technical problems of incapability of considering possible hardware faults and anomalies, and incapability of guaranteeing the performance and reliability of the chip due to the uncertainty of the chip production process are solved. More accurate simulation and prediction are carried out on the chip design, and potential hazards are repaired in advance. Moreover, a more detailed and accurate simulation result is provided, so that the technical effects of improving the design efficiency, reducing the costs, and improving the performance and reliability of the chip are achieved.

The invention discloses a chip design method, system and device based on a multi-core heterogeneous architecture and a medium. The method comprises the steps that the type and number of heterogeneous computing cores are determined according to a target application scene, and a task scheduling unit is configured; designing an on-chip interconnection structure of a heterogeneous computing core by adopting a hybrid topological structure, and verifying and adjusting a dynamic task scheduling strategy and the on-chip interconnection structure through hardware simulation; configuring a power management unit according to the energy efficiency optimization target, wherein the power management unit is used for controlling the working state of the heterogeneous computing core; operating data of the heterogeneous computing core are collected in the post-silicon verification stage, a firmware updating scheme is generated according to the operating data, and firmware updating is conducted according to the firmware updating scheme. By optimizing the chip design process under the multi-core heterogeneous architecture, the performance, the energy efficiency ratio and the reliability of the chip are improved, and the method can be widely applied to the technical field of chip design.

The invention provides an electric energy meter PCB function test method and device, a medium and equipment, and the method comprises the steps: obtaining a multi-channel signal source, automatically adjusting the characteristics of an input signal based on a feedback signal of an electric energy meter through a self-adaptive algorithm, and determining the consistency of the working characteristics of the input signal and the working characteristics of the electric energy meter; a virtual power grid environment simulation model is constructed, through integrated power simulation software and dynamic interference simulation, simulation signal source automatic adjustment signal characteristics are input into the virtual power grid environment simulation model based on the integrated power simulation software to synthesize a composite signal, and load fluctuation of an electric energy meter in actual operation is simulated based on the composite signal. Determining an electric energy meter test data set; according to the invention, the fault mode of the electric energy meter can be automatically identified, the test data can be analyzed in real time, and fault diagnosis and optimization suggestions can be automatically given. The intelligent diagnosis mode is far better than a traditional manual detection method, and the speed and accuracy of fault diagnosis can be remarkably improved.

The invention relates to the technical field of electronic information, and discloses a high-reliability storage chip packaging test method and system.The method comprises the steps that firstly, a to-be-tested storage chip and original parameter information of the to-be-tested storage chip are obtained, packaging structure data are collected to construct a three-dimensional model, chip feature data are extracted, then the chip feature data are compared with standard reference data, and potential defect information is mined; suspicious packaging parts are screened, the sensitivity of the suspicious packaging parts to environmental parameters is monitored, then fault risk types are evaluated, weak links are positioned, performance is detected, specific problem points are found out, then a test planning target is formulated, test means and standards are clarified, a test operation instruction is generated, finally, packaging testing is executed, electrical performance data are collected, and stability is verified. And generating a packaging test report. The stability of the memory chip can be improved.

The embodiment of the invention discloses an input excitation completeness detection method, system and device and a storage medium, relates to the technical field of semiconductor verification, and aims to improve the efficiency of port signal excitation completeness verification. The method comprises the following steps: analyzing a signal attribute of an input port in a tested design file; based on the signal attributes, generating a function coverage rate file covering all input signals, the function coverage rate file including value coverage logic detection assertions corresponding to different signal attributes and function coverage rates; and monitoring and detecting the function coverage state of the current input excitation signal according to the function coverage file. The method is suitable for verification scenes of semiconductors such as chips and the like.

The invention provides a DFT test task management method and device, electronic equipment and a storage medium, and belongs to the technical field of chip design verifier.The DFT test task management method comprises the steps that a data model is constructed on the basis of a design module list and a test step list, the data model is used for indicating testability design DFT test steps of all design modules, and the test steps of all the design modules are stored in the test step list; the data model comprises a plurality of DFT test tasks, attributes of each DFT test task comprise a selection state, and the selection state comprises a selected state and a non-selected state; based on the interactive input, determining at least one DFT test task of which the selection state is selected as an executable DFT regression object; and according to the DFT regression object, driving a DFT test task to be executed. According to the method, the DFT test tasks are normalized through the data model, only the DFT test tasks need to be selected for making the test plan, efficient management of the DFT test tasks is achieved, and the regression test efficiency is improved.

The invention provides an execution method and device for a test case in a verification platform, equipment and a storage medium, and the method comprises the steps: obtaining a target test case constructed by an interpreted language, and starting the execution of the target test case on the verification platform; the target test case is a program for providing an excitation component for verification of the to-be-tested design file; in response to execution of the target test case, generating a test trigger instruction through the flow controller, and transmitting the test trigger instruction to a sequence control tool in the verification platform through the socket interface; a sequence control tool is used for analyzing the test trigger instruction, the starting and excitation sending sequence of an excitation assembly in the execution process of the target test case is controlled through an analysis result, an excitation execution result is obtained, and the sequence control tool is compiled through a compilation type language; and the excitation execution result is transmitted to the flow controller through the socket interface to be output. According to the application, multi-language compatibility is realized by adopting the socket interface.