9077results about "CAD circuit design" patented technology

The invention discloses a PCB intelligent optimization layout wiring method and device, equipment and a storage medium, and relates to the technical field of electronic manufacturing, and the method comprises the steps: obtaining the initial layout of a printed circuit board; on the basis of a first optimization algorithm, automatically adjusting the layout position of the initial layout according to a functional module area and writing design requirements to obtain an adjusted layout; optimizing the heat dissipation structure of the adjusted layout through thermal analysis to obtain a reference layout; and wiring the reference layout based on a second optimization algorithm to complete the layout wiring of the printed circuit board. According to the invention, the layout and wiring efficiency and accuracy of the printed circuit board can be improved.

The invention discloses an SM4 encryption method based on an FPGA, and relates to the technical field of data encryption, and the method comprises the steps: obtaining to-be-encrypted plaintext data; a plurality of SM4 encryption cores are configured on the FPGA chip to perform parallel encryption operation on plaintext data to be encrypted; wherein each SM4 encryption core adopts a pipeline architecture, and the pipeline architecture comprises an access device, a round function arithmetic unit and a key adder; an extraction circuit based on physical noise and integrated on the FPGA chip is utilized to generate N-bit random numbers as encryption keys of each SM4 encryption core; handshake signals are collected to calculate the operation efficiency of each SM4 encryption core; adjusting FPGA resource allocation among the SM4 encryption cores by adopting a priority scheduling algorithm according to the operation efficiency; in the encryption operation process, power consumption equalization is carried out by adopting polynomial and logical operation hybrid calculation, and time sequence randomization is carried out by adopting a random waiting period. Aiming at the problem of weak anti-difference sensitivity in the prior art, the side channel attack resistance is improved.

The invention provides a dynamic method and system for thermal fatigue evaluation of integrated circuit packaging, and relates to the technical field of integrated circuits, and the method comprises the steps: employing a genetic algorithm to determine the arrangement position of a temperature sensor, and collecting a temperature data sequence of a temperature sensor array and the corresponding time information; establishing a thermal-mechanical coupling analysis model comprising a geometric model, a material constitutive relationship and a load boundary, and performing mesh generation on the thermal-mechanical coupling analysis model to obtain a finite element model; based on the finite element model, periodically solving by adopting a nonlinear iterative algorithm to obtain a welding spot stress-strain field data sequence and time information corresponding to the welding spot stress-strain field data sequence, establishing a corrected Coffin-Manson model considering a temperature-stress-time coupling effect, calculating a fatigue damage increment of the welding spot, and accumulating the fatigue damage increment in real time; and performing thermal fatigue state evaluation on the integrated circuit packaging structure according to the change rate of the accumulated fatigue damage value.

The invention provides an EDA software implementation method and system for memory IP layout optimization, and relates to the technical field of memorizers, the method comprises the following steps: receiving a memory IP design parameter and an optimization target input by a user, and calling a matched basic unit module from a pre-established hierarchical memory IP library according to the design parameter; an initial memory IP layout scheme is generated based on the basic unit module, the initial memory IP layout scheme is rapidly evaluated by utilizing a neural network model, a plurality of optimized layout candidate schemes are generated by adopting a genetic algorithm, and each optimized layout candidate scheme comprises different basic unit arrangements, metal layer use strategies and buffer insertion positions; performing parallel simulation on the optimal layout candidate scheme, and selecting an optimal layout scheme; and performing post-simulation verification on the optimal layout scheme, wherein the post-simulation verification comprises static time sequence analysis, dynamic power consumption analysis and electromagnetic compatibility analysis.

The invention relates to the field of chip verification, and provides a chip verification method, device and equipment, a medium and a chip. The method comprises the following steps: establishing a dynamic simulation verification environment of a to-be-verified design, and generating a plurality of test scenes and corresponding test excitation according to a design specification definition; sending the test excitation to a driver through a sequencer, converting the test excitation into a signal conforming to a to-be-verified design interface protocol by the driver, and transmitting the signal to the to-be-verified design; the monitor collects an input signal and an output signal of a to-be-verified design in real time, converts the input signal and the output signal into transactions, and transmits the transactions to the scoreboard; comparing the reference model with an output signal of the to-be-verified design to generate a dynamic simulation verification result; according to the dynamic simulation result, the state space is reduced, state space traversal is carried out on a design part which is not covered by dynamic simulation in the design to be verified, and a formal verification analysis result is generated; and evaluating the to-be-verified design according to the formal verification analysis result.

In some embodiments, a configured artificial intelligence system includes a plurality of intelligence models; a scoring system configured to generate know-your-model scores that quantify suitability for specific tasks of each model; a model execution system configured to provide standardized execution environment for the plurality of intelligence models; a training and reinforcement system configured to monitor outcomes relating to decisions or predictions made by the plurality of intelligence models and use outcome data as feedback to reinforce model performance; and a governance and analysis system configured to ensure model operations comply with governance standards. The intelligence controller may be configured to receive task requests, analyze task complexity, decompose tasks into manageable subtasks, and dynamically select appropriate models from the plurality of intelligence models to execute each subtask based on model suitability and performance characteristics.

The invention relates to a BMS test method, device and equipment and a storage medium, and the method comprises the following steps: carrying out the data collection of a BMS system of a battery pack, obtaining the collection data, carrying out the preprocessing of the collection data, and obtaining the preprocessing data; estimating the state of charge of the battery pack based on the preprocessed data to obtain a state of charge estimated value; constructing a time sequence change curve based on the charge state estimation value, and performing residual service life evaluation on the battery pack based on the time sequence change curve to obtain a residual service life evaluation result; performing health state analysis on the battery pack based on the residual service life evaluation to obtain a health state report of the battery pack; formulating a management strategy of the battery pack based on the health state report; the method solves the problem that the accuracy is often insufficient when the battery state evaluation is carried out by purely depending on the complex chemical reaction and dynamic change of the battery.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and an interposer disposed on a portion of the package substrate. A first integrated circuit (IC) chip is disposed on the interposer. A first memory device is disposed on the interposer and includes a first port interface including an interposer-compliant mechanical interface for coupling to the first IC chip via a first set of traces formed in the interposer. A second port interface includes a non-interposer-compliant mechanical interface for coupling to an off-interposer device. Transactions between the first IC chip and the off-interposer device pass through the first port interface and the second port interface of the first memory device.

The invention discloses a multi-agent joint layout model training method and device, equipment and a medium, and relates to the field of printed circuit board design. The method comprises the steps that parameter information related to components to be arranged and grouping information generated based on the types of the components and aiming at the components to be arranged are acquired, and a corresponding intelligent agent is configured for each group of components; according to the parameter information and by adopting a distributed mode, carrying out layout on respective corresponding components through each intelligent agent; obtaining decision data generated by the policy network in the layout process of each agent, and evaluating the decision data by using the value network to obtain learning experience data for each component; and according to the learning experience data, determining update parameters of the strategy network and the value network of each agent by using the objective function, updating the corresponding agent by using the update parameters, and obtaining a multi-agent joint layout model based on all the updated agents. And the layout capability of the printed circuit board is improved.

Systems and methods for training a machine learning model for defect detection include obtaining training data including an inspection image of a fabricated integrated circuit (IC) and design layout data of the IC, and training a machine learning model using the training data. The machine learning model includes a first autoencoder and a second autoencoder. The first autoencoder includes a first encoder and a first decoder. The second autoencoder includes a second encoder and a second decoder. The second decoder is configured to obtain a first code outputted by the first encoder. The first decoder is configured to obtain a second code outputted by the second encoder.

Disclosed in the present invention is a non-autoregressive Transformer-based modeling method for a 4-level pulse amplitude modulation high-speed transmitter. The method involves establishing a deep learning model having an encoder-decoder architecture to predict the behavior of a 4-level pulse amplitude modulation transmitter. An encoder processes unordered non-sequential inputs, including an input signal parameter and link parameters, to generate a context vector and then transmit same to a decoder. The decoder uses both the context vector generated by the encoder and a transmitter output signal sequence to generate a categorical probability distribution for each point in the sequence one by one. The model is trained using a random masking strategy, and inference is performed by means of non-autoregressive decoding and filtering, so that the model can perform parallel prediction on an output sequence, and perform a filtering process to predict an output signal. Compared to traditional simulation methods, the present invention achieves a significant acceleration effect, particularly when processing multi-link systems.

Embodiments of the present disclosure include a software solution for generating a connectivity file that forms the connections between signals in a design under test (DUT) and signals in a verification IP (VIP) interface. The connecting signals from the DUT may form a DUT interface and the DUT interface may follow a protocol. The software solution may utilize a generative AI-based tool to identify example connections that also follow the protocol. These example connections may be included in a query to a large language model (LLM) for purposes of improving the results generated by the LLM.

The invention discloses a power load model parameter identification method based on improved deep reinforcement learning, and belongs to the technical field of power load identification. The method comprises the following steps: determining a to-be-identified power load parameter based on a complete comprehensive load model considering power distribution network impedance and reactive compensation; then designing a power load parameter identification model based on a bidirectional gating cycle unit depth deterministic strategy gradient algorithm of priority experience playback; circuit data are collected for model training, and the trained model is used for parameter identification. On the basis of an existing power system mechanism model and a data driving model, the load model parameters are identified by improving the deep reinforcement learning model, and verification shows that the method can accurately identify the power system load model parameters, can improve the fitting precision of the power system load model, and has a good application prospect. The operation strategy of the power grid is optimized, and the operation cost is reduced.

The invention discloses a circuit netlist generation method supporting deep learning model multi-stage reasoning, and belongs to the technical field of electronic circuit design and automation, and the method comprises the steps: obtaining a circuit diagram image through optical scanning, carrying out the preprocessing of the image, carrying out the recognition of a component through a deep learning model YOLOv5, and determining the boundary frame coordinates and class information. And further performing port fine identification on the component, and determining the position and the direction of the port. And eliminating character interference by using an optical character recognition technology, performing wire recognition, including Hough straight line detection and jumper processing, and determining starting point and ending point coordinates of the wire. And matching the identification results of the components, the ports and the wires, constructing a topological structure of a circuit diagram, finally generating a circuit netlist, and performing error elimination and JSON format output. According to the method, automatic netlist generation of the analog circuit diagram can be realized, the analog circuit diagram file is converted into the netlist file with device function annotations, and the efficiency and quality of circuit design and simulation are improved.

The invention relates to the technical field of ultra-low power consumption microcontrollers, and discloses an ultra-low power consumption microcontroller architecture design method and system, and the method comprises the steps: constructing a heterogeneous dual-core processor comprising a high-performance core and a low-power consumption core, and dividing the heterogeneous dual-core processor into a plurality of independent power domains; constructing a sub-threshold voltage operation system on a plurality of independent power supply domains, and configuring a multi-layer storage structure in the heterogeneous dual-core processor; recording task characteristic data by using a multi-level storage structure, executing task dynamic allocation between dual cores, and creating a dynamic task allocation mechanism; and performing static analysis and function block division on the application code based on a dynamic task allocation mechanism to obtain a plurality of function code blocks, and performing storage hierarchy and processor core allocation on the plurality of function code blocks to obtain a function code allocation result. According to the method, the dynamic migration of the workload and the optimal resource allocation are realized, and the energy consumption of the microcontroller in various working scenes is reduced.

The present application relates to the technical field of chip design, and provides a chip layout and training method, an electronic device, a storage medium, and a chip system. According to the method, generalization of the layout method across different chip netlists can be improved. The method comprises: determining first relative position information, wherein the first relative position information is relative position information between different units among units laid-out in a sample chip; determining a first input of a graph neural network to be trained, wherein the first input is obtained on the basis of a first netlist corresponding to the sample chip; obtaining a first output by means of the graph neural network; performing encoding on the basis of the first output to obtain second relative position information; calculating a loss function value on the basis of the first relative position information and the second relative position information; and optimizing a trainable parameter in the graph neural network on the basis of the loss function value.

The embodiment of the invention provides a chip design system and method based on multiple agents. The system comprises a plurality of agents, and the following steps are cooperatively executed through the plurality of agents: receiving a design request of a user, and executing the whole chip design processing flow based on chip design demand information included in the design request so as to generate a chip design file (including chip layout information) for subsequent actual chip manufacturing. Visibly, according to the scheme, the intelligent agent based on LLM is applied to chip design full-process exploration, manual participation can be reduced, and the chip design efficiency can be improved.

Provided in the present invention is a thermal stress simulation method for a laminated structure. The simulation method comprises: importing a simulation model; creating a heat dissipation simulation process; completing relevant settings of a model heat source device; setting a thermal analysis simulation environment; activating a thermal stress analysis option, and selecting the type of fixed support; completing thermal-stress coupling simulation analysis; checking a post-processing result; and modifying a layout design according to the post-processing result. A potential structural risk of an electronic product can be predicted by means of thermal stress simulation, the situations of a temperature field, a stress field and a deformation field of an analysis object are obtained by means of finite element analysis, and theoretical research and an experimental test are effectively verified and supplemented, thereby rapidly implementing the verification and iteration of a product.

The invention relates to the technical field of pre-silicon verification, and discloses an isolation function verification method, device and system, and the method comprises the steps: obtaining the hierarchical structure information of a power domain module in a to-be-tested chip; determining isolation definition information of the power domain module, and identifying an isolation signal type from the isolation definition information; determining a target internal port signal corresponding to the isolation signal type in the hierarchical structure information, and judging whether to perform mapping processing on the target internal port signal based on the signal mapping information according to the isolation signal type; and generating at least one assertion of a target isolation function verification signal according to the target isolation function verification signal represented by the judgment result, and performing isolation function verification on the power domain module based on the generated assertion. According to the technical scheme provided by one or more embodiments, the check assertion can be automatically and efficiently generated to verify the chip.

The invention relates to a modeling and optimizing method for inter-layer signal crosstalk of a PCB (Printed Circuit Board). Frequency response data of all dielectric layers of the PCB under different temperature and humidity conditions are collected, and a mapping model with the temperature gradient and the humidity diffusion gradient as input and the dielectric constant as output is established. And calculating the dynamic distribution of mutual capacitance and mutual inductance under the environment change by combining the spatial layout parameters of the differential signal pair, and constructing a crosstalk sensitivity evaluation model with coupled frequency, environment and layout. And high-risk areas with crosstalk sensitivity caused by environment change are identified, and the crosstalk change rate of each area is quantified. For a sensitive area, a temperature and humidity compensation medium structure is introduced to stabilize local dielectric characteristics and reduce the influence of the environment on crosstalk. And according to the compensated medium distribution, adjusting a differential signal wiring path and impedance matching by adopting an optimization method with the aim of minimizing the crosstalk change rate, and generating a wiring layout with environmental robustness. According to the invention, the signal integrity and the transmission reliability of the multi-layer PCB in a temperature and humidity changing environment can be effectively improved.

The invention relates to the technical field of electronic circuits, in particular to a construction method and system of a high-speed differential signal transmission model. The method comprises the following steps: acquiring design data of the printed circuit board, and extracting differential signal line data; constructing a high-speed differential signal transmission model according to the differential signal line data; performing signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data; identifying a crosstalk source position based on the high-speed differential signal transmission data to obtain a crosstalk source coordinate; detecting via hole dislocation based on the crosstalk source coordinates to obtain via hole dislocation data, and evaluating a heat accumulation degree based on the via hole dislocation data; identifying an electrical fault area of the circuit board based on the heat accumulation degree; and extracting stack structure information according to the printed circuit board design data. Based on the electronic circuit technology, the precision and reliability of the high-speed differential signal transmission model are improved, and the signal transmission quality and the electrical fault detection rate are remarkably improved.

The invention relates to the technical field of PCB detection, and provides a PCB life analysis method based on reliability analysis and related equipment. The method comprises the following steps: performing multi-physics field coupling modeling on a to-be-detected circuit board to obtain a multi-field coupling data set, performing space-time alignment processing on a collected multi-source sensor data set to obtain a fusion monitoring data set, and performing feature extraction according to the multi-field coupling data set and the fusion monitoring data set to obtain a failure sensitive feature matrix; therefore, a dynamic neural network is used for modeling the failure sensitive feature matrix to obtain corresponding life prediction probability distribution data, and the life prediction probability distribution data is adjusted through actual measurement failure data calibration to obtain an accurate life prediction model. And finally monitoring the circuit board to be detected in real time through the life prediction model to obtain real-time life evaluation data. According to the invention, through fusion of multi-physics field coupling and real-time monitoring data, the service life performance of the target in a complex environment can be evaluated more accurately.

The invention discloses a quantum dot enhanced dynamic power consumption management method, a quantum dot enhanced dynamic power consumption management system and related equipment. Aiming at the problem of insufficient optimization caused by difficulty in comprehensively, accurately and dynamically sensing the internal energy distribution and conversion process of a chip by a traditional method, the method comprises the following steps of: acquiring the quantum state of the chip in real time by utilizing a quantum dot sensing array, and constructing an adaptive power consumption prediction model by combining multi-source data fusion and feature extraction; and an optimal management strategy is generated based on a multi-objective optimization framework, an execution feedback and self-learning mechanism is introduced, and finally a complete closed-loop control system is formed. The method can be widely applied to various processor chips in the fields of high-performance calculation, the Internet of Things, artificial intelligence and the like, dynamic power consumption management of the chips is achieved through the quantum dot enhancement technology, the performance is guaranteed, meanwhile, energy consumption is minimized, the battery endurance time is prolonged, the heat dissipation cost is reduced, and the energy efficiency of the chips can be remarkably improved.

The invention relates to the technical field of PCBs (printed circuit boards), in particular to an intelligent PCB detection and repair method, which comprises the following steps: S1, initializing module configuration: automatically identifying the type and structure information of a PCB; s2, a dynamic detection stage: collecting electrical parameters of the PCB, and generating fault position information; s3, circuit dynamic characteristic compensation: analyzing the nonlinear distortion characteristic of the circuit, and calculating and executing dynamic compensation; s4, an automatic repair stage: generating a repair scheme, including solder joint repair, line reconstruction or signal compensation; and S5, an intelligent recheck stage: performing comprehensive retest on the repaired PCB, verifying the performance of the repaired area, and generating a repair evaluation report. According to the invention, the repair precision and efficiency are improved, the whole repair process is intelligent and automatic, the risk of manual intervention is reduced, and the overall repair efficiency and the long-term reliability of the PCB circuit are improved.

The invention relates to the technical field of circuit board line planning, in particular to an automatic design arrangement and path planning method and system for a double-sided board and multi-layer board printed circuit. The method comprises the following steps: acquiring input parameters of a circuit board, and analyzing to generate an initial structure of a wiring grid diagram; abstracting a wiring problem into a graph model, and extracting a wiring topological structure and density distribution characteristics; a deep reinforcement learning algorithm is adopted to optimize and generate a wiring path, and factors such as a wiring direction, layer selection and path length are considered at the same time; detecting, adjusting and optimizing wiring design rule conflicts on the basis of generating the wiring path; a comprehensive evaluation system of a wiring path planning scheme is established, indexes such as wiring efficiency, density and interlayer balance are considered, preset quality requirements are met through iterative optimization, and an optimized wiring path is output. According to the method, the wiring strategy can be adaptively learned and improved, and the reliability, efficiency and quality of wiring planning are improved.

The invention belongs to the technical field of connectors and discloses a design method for a low-loss cable connector without resonance points, comprising: designing a spiral gradient groove structure on the surface of an inner conductor based on the impedance continuity principle, establishing a composite gradient impedance theoretical model of the connector, constructing a dielectric constant gradient distribution model of a double insulating layer, and setting a transition function between an inner layer and an outer layer; solving the S parameters and electric field distribution of the connector through electromagnetic-thermal coupling finite element simulation, optimizing the spiral angle θ and the gradient index n, establishing a quantitative model of the surface roughness of the conductor and high-frequency loss, and determining a threshold range of the surface roughness through calculation of the quantitative model; performing global optimization of structural parameters based on a multi-objective genetic algorithm, outputting a theoretical design parameter set and a report collection of performance verification, eliminating the resonance point problem of traditional connectors, and providing excellent low-loss performance in the full frequency band, which is particularly suitable for high-frequency and high-power transmission environments.

The invention belongs to the technical field of integrated circuit design verification, and particularly discloses an SoC performance verification method and device based on dynamic QoS regulation and control, a medium and equipment, and the method comprises the steps: analyzing a chip architecture, and obtaining a chip resource mapping table; constructing an automatic verification environment based on the chip resource mapping table and performing testing; scene parameter configuration is carried out according to a target application scene and based on the chip resource mapping table; and performing dynamic QoS regulation and control based on the configured scene parameters in a tested automatic verification environment so as to verify the performance of the SoC. According to the invention, the accuracy and efficiency of SoC performance verification and the consistency of the result and the actual application scene can be improved.

The invention provides an EDA software and heterogeneous process design rule collaborative verification method, which relates to the technical field of EDA software, and comprises the following steps of: extracting time sequence characteristics in a dynamic association graph through a bidirectional long-short-term memory network, analyzing node coupling strength by utilizing a multi-head graph attention network to generate a hierarchical importance scoring matrix; and outputting a conflict risk tensor and a propagation path prediction map based on a depth rule conflict prediction model, and generating a correction strategy in combination with a variational auto-encoder and a reinforcement learning network. According to the method, design rule conflicts can be accurately predicted and positioned, an effective correction scheme is provided, and the accuracy and efficiency of heterogeneous process design rule verification are improved.

The embodiment of the invention relates to the field of chip verification, and discloses an automatic chip verification method, system and device and a medium. Generating a register model according to the custom register table; generating a register test case based on the register attribute; performing simulation operation on the register model and the register test case according to a simulation configuration file, and collecting coverage rate information in a simulation result; the simulation configuration file comprises simulation times, test case names and coverage rate collection targets. Compared with a traditional manual operation mode, the method has the advantages that the change of the register can be quickly responded, the test case is automatically updated, and the continuity and integrity of the verification process are ensured. According to the invention, high automation of the chip verification process is realized, manual intervention is reduced, verification comprehensiveness and resource utilization rate are improved, and more reliable verification guarantee is provided for chip design. The technical problem of low chip verification efficiency can be at least solved.