3421results about "CAD circuit design" patented technology

The invention relates to the field of chip verification, and provides a chip verification method, device and equipment, a medium and a chip. The method comprises the following steps: establishing a dynamic simulation verification environment of a to-be-verified design, and generating a plurality of test scenes and corresponding test excitation according to a design specification definition; sending the test excitation to a driver through a sequencer, converting the test excitation into a signal conforming to a to-be-verified design interface protocol by the driver, and transmitting the signal to the to-be-verified design; the monitor collects an input signal and an output signal of a to-be-verified design in real time, converts the input signal and the output signal into transactions, and transmits the transactions to the scoreboard; comparing the reference model with an output signal of the to-be-verified design to generate a dynamic simulation verification result; according to the dynamic simulation result, the state space is reduced, state space traversal is carried out on a design part which is not covered by dynamic simulation in the design to be verified, and a formal verification analysis result is generated; and evaluating the to-be-verified design according to the formal verification analysis result.

In some embodiments, a configured artificial intelligence system includes a plurality of intelligence models; a scoring system configured to generate know-your-model scores that quantify suitability for specific tasks of each model; a model execution system configured to provide standardized execution environment for the plurality of intelligence models; a training and reinforcement system configured to monitor outcomes relating to decisions or predictions made by the plurality of intelligence models and use outcome data as feedback to reinforce model performance; and a governance and analysis system configured to ensure model operations comply with governance standards. The intelligence controller may be configured to receive task requests, analyze task complexity, decompose tasks into manageable subtasks, and dynamically select appropriate models from the plurality of intelligence models to execute each subtask based on model suitability and performance characteristics.

Disclosed in the present invention is a non-autoregressive Transformer-based modeling method for a 4-level pulse amplitude modulation high-speed transmitter. The method involves establishing a deep learning model having an encoder-decoder architecture to predict the behavior of a 4-level pulse amplitude modulation transmitter. An encoder processes unordered non-sequential inputs, including an input signal parameter and link parameters, to generate a context vector and then transmit same to a decoder. The decoder uses both the context vector generated by the encoder and a transmitter output signal sequence to generate a categorical probability distribution for each point in the sequence one by one. The model is trained using a random masking strategy, and inference is performed by means of non-autoregressive decoding and filtering, so that the model can perform parallel prediction on an output sequence, and perform a filtering process to predict an output signal. Compared to traditional simulation methods, the present invention achieves a significant acceleration effect, particularly when processing multi-link systems.

The invention provides a DFT test task management method and device, electronic equipment and a storage medium, and belongs to the technical field of chip design verifier.The DFT test task management method comprises the steps that a data model is constructed on the basis of a design module list and a test step list, the data model is used for indicating testability design DFT test steps of all design modules, and the test steps of all the design modules are stored in the test step list; the data model comprises a plurality of DFT test tasks, attributes of each DFT test task comprise a selection state, and the selection state comprises a selected state and a non-selected state; based on the interactive input, determining at least one DFT test task of which the selection state is selected as an executable DFT regression object; and according to the DFT regression object, driving a DFT test task to be executed. According to the method, the DFT test tasks are normalized through the data model, only the DFT test tasks need to be selected for making the test plan, efficient management of the DFT test tasks is achieved, and the regression test efficiency is improved.

Methods and systems for training a prediction model to predict a mask image in which mask rule check (MRC) violations or process violations (e.g., edge placement error, sub-resolution assist feature (SRAF) printing) are minimized or eliminated. The prediction model is trained based on a loss function that is indicative of (a) a difference between the predicted mask image and a reference image, and (b) at least one selected from: an MRC evaluation of the predicted mask image or an evaluation of a simulated image of the predicted mask image.

The invention discloses a clock optimization method, device and equipment and a computer readable storage medium, which are applied to the field of integrated circuits, and comprise the following steps: reading a netlist of each fragment, and traversing each netlist to generate an instance tree corresponding to each fragment; performing reverse tracing and forward tracing on each clock signal based on each instance tree to obtain a clock network path corresponding to each clock signal; determining a redundant clock according to each clock network path, and performing corresponding processing on the redundant clock; the redundant clock comprises an isolated redundant clock and an equivalent redundant clock. According to the method, the instance tree is generated by traversing the netlist, and the complete clock network path is obtained by combining reverse tracing and forward tracing, so that isolated redundant clocks and equivalent redundant clocks can be comprehensively captured, and automatic tracking of the clock network path and accurate identification of the redundant clocks are realized; the redundant clock is correspondingly processed, so that unnecessary clock generation logic and wiring resource occupation can be reduced, the chip power consumption and the area overhead are reduced, and the resource utilization rate is improved.

The invention relates to the technical field of fault prediction and health management, in particular to a primary and secondary fusion complete ring main unit fault diagnosis method and system. Comprising the following steps: acquiring three-phase instantaneous voltage and current signals in real time, and converting the signals into digital transient data; performing time window preprocessing on the digital transient data, and executing wavelet packet decomposition to generate a transient feature vector; calculating and analyzing the transient feature vector through a transient zero-sequence power direction method and a support vector machine model to generate a local diagnosis result; when the local diagnosis result is that cooperative positioning needs to be started, a transient current similarity coefficient and a transient waveform intensity difference coefficient are calculated based on the digital transient data, and a comprehensive positioning result is generated; determining a fault line according to the comprehensive positioning result, and generating a remote control command; and executing a fault isolation operation based on the remote control command, and executing a PHM process. According to the method, the double local transient diagnosis and the cross-terminal cooperative positioning are deeply fused, so that the high-precision determination of the boundary of the fault section is realized.

The invention belongs to the technical field of semiconductor device packaging, and discloses a power semiconductor module three-dimensional stacking vertical commutation low-inductance packaging structure. The two vertical commutation structures are stacked and integrated on the same substrate; different from traditional two-dimensional packaging in which all elements are laid on a two-dimensional plane, three-dimensional stacked packaging suitable for power devices is proposed for the first time, and power loops are stacked and integrated; the magnetic fluxes of the stacked power loops are cancelled, so that ultra-low inductance (pH level) integration is realized; under the condition that the areas of the substrates are the same, the capacity of the module is doubled; meanwhile, dynamic current sharing design is considered, and one driving chip simultaneously drives eight GaN chips to realize parallel dynamic current sharing for the first time; the method is suitable for various topological structures including half-bridge structures, full-bridge structures, three-level ANPC structures and the like; the method is suitable for various packaging schemes, including PCB on DBC packaging, DBC substrate welding / sintering packaging and embedded packaging. Taking the packaging of the half-bridge module double-sided parallel PCB on DBC as an example, low-inductance, low-thermal-resistance and high-power-density integration is realized.

The invention provides a PCB manufacturability intelligent analysis and early warning method and system based on artificial intelligence, and the method comprises the steps: collecting and marking the multi-source time sequence process parameter data in the PCB design and manufacturing process under working conditions, building a dynamic causal graph model with direction and time lag marks through a sliding window and standardization processing by applying a causal discovery algorithm, and carrying out the calculation of the dynamic causal graph model. Dynamic expression of causal relationships among process variables is realized; when manufacturing abnormity is detected, abnormity attribution is carried out by combining a Bayesian back propagation algorithm, high-contribution-degree root dependent variables are screened, the effectiveness of root causes is verified through virtual intervention simulation and statistical test, and finally verification results and a causal mode are stored in a knowledge base to support subsequent rapid matching and reasoning. According to the method, the accuracy, efficiency and interpretability of PCB manufacturing abnormity attribution are improved, and process optimization and preventive intervention are facilitated.

The invention provides a chip verification method and device, equipment, a medium and a program product, and the method comprises the steps: receiving a first operation instruction of a to-be-verified module and a second operation instruction of a reference model in parallel, the reference model being a function model used for simulating the expected behavior of the to-be-verified module; searching a first instruction record matched with the first operation instruction from a request queue of the reference model, and searching a second instruction record matched with the second operation instruction from a request queue of the to-be-verified module; and determining a verification result of the to-be-verified module according to a comparison result of the first operation instruction and the first instruction record and / or a comparison result of the second operation instruction and the second instruction record. According to the invention, a structured and reusable universal chip verification method is realized, so that a tedious customized scoreboard design is replaced, and the efficiency and accuracy of verification work are greatly improved.

The invention discloses an electromagnetic field simulation grid adaptive generation method based on a neural network. The method comprises the following steps: performing mesh generation on a semiconductor device simulation model to obtain original generation data, and constructing node features; an undirected graph is constructed, graph nodes of the undirected graph adopt node features of grid points, and connecting edges adopt Euclidean distances between the grid points and adjacent grid points; inputting the undirected graph into a double-branch neural network, and outputting a predicted node position; and correcting each node of the original subdivision data by using the predicted node position obtained by the double-branch neural network to form new subdivision data for electromagnetic field simulation. According to the method, physical field information can be fused to efficiently adjust the node density, and the geometric boundary and topological structure characteristics of the device can be strictly kept.

A computer-implemented method for simulating an aircraft system in a closed-loop functional simulation environment is disclosed. The computer-implemented method may include: receiving, at a computer system, one or more control inputs from an interface; processing, by a control system model, the one or more control inputs to generate one or more system command signals; applying the one or more system command signals to one or more virtual system models; simulating a physical response of the aircraft based on output generated by the one or more virtual system models in response to application of the one or more system command signals; generating, responsive to monitoring the output generated by the one or more virtual system models, sensor data; transmitting the sensor data to the control system model; and outputting simulation results, wherein the simulation results at least comprise an indication of the physical response of the aircraft.

The invention discloses a cluster model acceleration method and device based on an FPGA, and relates to the technical field of model acceleration, and the method comprises the steps: converting a cluster simulation model into a digital circuit structure file, and burning the digital circuit structure file into an FPGA board card; splitting the digital circuit structure file into a plurality of independent calculation modules according to functions; packaging the calculation module into a plurality of IP cores based on the requirements of different individuals in the cluster; in response to input data received in the DDR of the FPGA board card, the hardware state machine triggers all the IP cores to execute corresponding tasks in parallel, and the calculation process of each IP core is controlled by taking a main clock of the FPGA board card as a reference; and each IP core writes the task processing result into a DDR (Double Data Rate) of the FPGA board card, and reads the DDR to obtain a simulation result of the cluster simulation model. The technical problems that an existing model acceleration method is poor in real-time performance and high in economic cost in a large-scale cluster simulation scene are solved, and therefore in the large-scale cluster simulation scene, high real-time performance of simulation can be guaranteed, and the economic cost can be effectively reduced.

The invention relates to a printed circuit board multilayer interconnection method, which comprises the following steps: firstly, automatically identifying and dividing interconnection channel areas of a circuit board, acquiring multi-dimensional parameters such as materials, thermal expansion coefficients and thermal cycle working conditions, realizing differential distribution and accurate preparation of a nano composite sensing material based on the multi-dimensional parameters, and obtaining the multi-dimensional parameters of the circuit board through an in-situ physical parameter acquisition and self-adaptive discrimination algorithm. Dynamic discrimination of stress abnormity and reverse driving of a micro heater are realized, the structure is induced to generate directional deformation so as to realize local automatic compensation, multi-point parameter data before and after compensation are used for health state modeling and residual life prediction, and big data archiving is combined to feed back manufacturing process optimization.

The invention relates to an SoC fault diagnosis method, system and device and a medium. The method comprises the following steps: acquiring on-chip sensor time sequence data, SoC multi-level software event log data and an SoC design mapping table, and performing time alignment to obtain multi-modal time axis data; performing modal feature extraction and embedding generation on the multi-modal time axis data, and performing single-modal anomaly detection on each modal feature to obtain an anomaly candidate set; on the basis of the abnormal candidate set, directional dependency measurement is calculated for the multi-modal embedded vector, time delay is recognized, a candidate causal edge list is obtained, and a heterogeneous time sequence-event causal graph is constructed in combination with the SoC design mapping table and the candidate causal edge list; and calculating the contribution degree of each node to downstream anomaly and candidate root cause probability distribution for the heterogeneous time sequence-event causality graph, and analyzing candidate root causes and corresponding contribution shares thereof to obtain a structured root cause report. By adopting the method, the SoC fault detection accuracy and the fault root cause positioning precision can be improved.

The invention discloses a PCB component layout method, device and equipment based on a multi-modal large model, and relates to the technical field of electronic design automation, the method comprises the following steps: carrying out quality screening on a plurality of PCB design files which have been laid out to obtain a qualified design file set; constructing a serialized training sample set based on the qualified design file set; each training sample sequence comprises a plurality of training samples arranged according to a layout logic sequence; each training sample comprises multi-modal data representing a current layout state and a real position coordinate of a next component to be laid out; based on the serialized training sample set, training the open-source multi-modal large model to obtain a PCB component layout model; and iteratively generating a layout file of the target PCB based on the netlist file of the target PCB and the PCB component layout model. The method is high in generalization capability and low in cost based on the PCB component layout model trained by the layout data, and can realize rapid layout of components of a new PCB.

The invention provides a target layout data generation method, electronic equipment and a readable storage medium. According to the method, the PCB layout generation process is converted into the iterative optimization task of the neural network model, and dual evaluation on the line length and the density distribution in the total loss function is combined, so that the problems of low layout quality, low optimization efficiency and the like in a traditional layout algorithm are effectively solved. The gradient is calculated through back propagation, the positions of the components are updated, it can be ensured that the lengths of the electrical connecting wires and the space uniformity of the components are optimized at the same time in the layout process, and therefore the overall performance and stability of layout are improved. In addition, in combination with a preset training termination condition, overtraining is avoided, and the calculation efficiency is improved. Finally, the generated optimized layout data has higher quality and consistency, and global optimization can be realized in complex design.

The invention provides a method and a system for automatically checking and correcting a PCB (Printed Circuit Board) design rule, belonging to the technical field of PCB design. The method comprises the following steps of: analyzing data such as texts, images and tables in a PCB design document through a multi-modal large model, extracting a structured signal information table, automatically generating a dynamically adaptive checking rule, and automatically checking and correcting the PCB design rule. Comprising bit width check, connectivity verification and functional analysis. And the generated rule is optimized by combining a retrieval enhancement generation (RAG) technology with a verification rule base, so that the coverage is comprehensive and the accuracy is high. The system further evaluates the rule through a form verification tool, automatically corrects potential defects, and improves the quality and adaptability of the rule. According to the method, the efficiency and accuracy of PCB design inspection are remarkably improved, the manual intervention requirement is reduced, the method can be widely applied to complex electronic design scenes, and the rapid changing technology and market requirements are met.

The invention provides a reverse modeling design method for a passive device and a computer readable medium, and the method comprises the steps: generating samples of different layout sizes of the passive device, and building a performance data set; establishing and pre-training by taking the geometric parameters and the working frequency as input parameters and the performance parameters as output parameters to obtain a forward model; constructing a reverse neural network model; dividing a parameter space of the whole performance data set into a plurality of sub-training domains, and respectively establishing and training a reverse sub-model in each sub-training domain; after training is completed, all the reverse sub-models are integrated to form a final reverse neural network model, and the reverse neural network model is used for outputting geometric parameter solutions meeting conditions according to the specified working frequency and performance parameters. According to the method, a high-confidence data set is constructed by using a forward model, and then the data set is divided based on the uniqueness of output parameters and the reverse sub-models are obtained respectively, so that rapid and accurate mapping from target performance parameters to geometric parameters is realized.

The invention discloses a circuit board printing control method and system based on signal transmission loss. And obtaining a target differential transmission line parameter and a circuit board lamination parameter. And establishing an electromagnetic simulation model, and simulating insertion loss, return loss and impedance discontinuous point distribution. The line width, the line spacing and the interlayer hollowed-out area of the differential transmission line are dynamically adjusted through the reinforcement learning model, the proportion of the line width to the shielding layer spacing is limited by a preset critical value, and the line spacing is configured based on the multiple relation of the shielding layer spacing. And a sectional optimization strategy is adopted for the corners of the transmission line. The ratio of the aperture to the diameter of the anti-pad is optimized, and impedance mutation is reduced. According to the method, the key parameters of the target differential transmission line and the circuit board lamination parameters are acquired, and the electromagnetic simulation model is combined with the multi-physical field coupling algorithm, so that the insertion loss, the return loss and the impedance discontinuous point distribution can be accurately simulated. The method improves the adjustment efficiency, guarantees the accuracy of an adjustment result, and effectively reduces the signal transmission loss.

The invention discloses a verification method of an integrated circuit, electronic equipment, a program product and a storage medium, and is applied to the technical field of integrated circuits, and the verification method comprises the following steps: obtaining a time sequence description file used for reflecting a time sequence of a hardware interface protocol of the integrated circuit; analyzing the time sequence description file to generate a structured rule corresponding to the time sequence description file; converting the structured rule into an executable assertion; and integrating the executable assertion into a verification environment, and performing function verification on the integrated circuit by using the verification environment to obtain a verification result of the integrated circuit. By applying the scheme of the invention, end-to-end automatic generation from the time sequence description file to the verification environment is realized, manual coding requirements of workers are not needed, the development cycle is greatly shortened, the efficiency is improved, manual coding of the workers is not needed, and thus human errors can be effectively avoided.

The invention provides a power consumption feature extraction method and system for a static random access memory standard cell library, electronic equipment and a storage medium, and the method comprises the steps: S1, reading a standard cell model file, a standard cell netlist and a standard cell time sequence path of a static random access memory, and constructing and generating an excitation waveform description file; s2, establishing a simulation file of the static random access memory standard unit, simulating the static random access memory standard unit, and respectively obtaining electrical characteristic data of an input pin and an output pin of the static random access memory standard unit; s3, analyzing the electrical characteristic data of the static random access memory standard unit, and obtaining a short-circuit power consumption time sequence path and a switching power consumption time sequence path existing in the static random access memory standard unit; and S4, respectively calculating power consumption values of each switching power consumption time sequence path and each short-circuit power consumption time sequence path. According to the method, the power consumption characteristics of the SRAM standard cell are extracted in the design stage of the standard cell library, and the precision and efficiency of power consumption analysis can be improved.

A method of estimating noise for individual gates of a quantum circuit uses averaged circuit eigenvalue sampling to determine an overall eigenvalue for the circuit. The circuit is sampled a sufficient number of times to fill a design matrix, wherein the design matrix allows for solving of a system of equations to determine eigenvalues for the individual gates using the averaged eigenvalue for the overall quantum circuit, the samples, and the sample results. Applying a logarithm to these relationships enables solving the system of equations using linear estimation or linear regression, in some embodiments.

The invention discloses an automatic layout generation method based on an experience module and a related device, and relates to the technical field of computers.The method comprises the steps that a template file is extracted, an independent device is generated based on the template file, and an experience module library is constructed based on the independent device; determining coordinate mapping and size constraints of the device, and performing multi-channel chip canvas hierarchical construction based on the coordinate mapping and size constraints of the device to obtain multi-channel chip canvas hierarchical representation; based on the empirical module library and the multi-channel chip canvas hierarchical representation, a reinforcement learning model is used for layout wiring, a target layout is obtained, and the reinforcement learning model comprises a state generation model, a value network and a strategy network. Layout and wiring of devices can be controlled more accurately, stray capacitance and resistance are effectively reduced, and the performance and reliability of an analog integrated circuit are effectively improved.

The invention discloses a high-density printed circuit board circuit forming process compensation method, which comprises the following steps of: firstly, collecting and standardizing structures and detection data of multiple batches and multiple process sections, and constructing a multi-target compensation optimization model through multi-dimensional parameter integration and feature extraction; the multi-objective compensation optimization model fuses objectives such as size precision, cost, electrical and thermal behaviors, establishes inter-objective collaborative constraints, introduces a reinforcement learning algorithm, dynamically adjusts weights of all the objectives, continuously optimizes compensation amount distribution in combination with process simulation feedback, finally fuses the optimal compensation weight into actual process control and collects effect feedback, and finally achieves the purpose of optimizing the optimal compensation weight. According to the method, high-precision and multi-target adaptive optimization of process compensation is realized, and the forming quality and the production efficiency of the circuit board are improved.

The invention provides a DCIM-based method for rapidly calculating a green function of a uniaxial anisotropic layered medium and an electromagnetic simulation system. The method comprises the following steps: modeling a uniaxial anisotropic layered medium to be simulated; determining a uniaxial anisotropic dielectric material of each layer, and assigning transverse parameters and longitudinal parameters; determining longitudinal coordinates of field point and source point distribution required to be solved, fitting a uniaxial anisotropic medium Green function spectral domain expression under the field source distribution by using a DCIM method, and solving an analytical expression in a spatial domain by using Somerfeld identical equation properties; solving the size of the electromagnetic field on the plane according to the fitted analytical expression; compared with a direct numerical integration method or a finite element method numerical solution using the Green function, the method has the advantages that the airspace analytical expression corresponding to the field source distributed on the plane is directly fitted, so that the solution of the airspace Green function is greatly accelerated, and the calculation efficiency and the calculation precision are both good in an actual example.

The invention relates to a PCB component type selection method and system based on a knowledge graph and intelligent retrieval. Relates to the technical field of PCB design, and the method integrates knowledge in multiple aspects of performance parameters, packaging forms, supplier information and the like of components by constructing a PCB component knowledge graph, and establishes semantic association among the knowledge. And performing intelligent retrieval in the knowledge graph by using an information retrieval algorithm based on design requirements and constraint conditions input by a user, and quickly and accurately screening out components meeting requirements. Meanwhile, the multi-mode large model is combined to carry out comprehensive evaluation on the components, factors such as cost and supply stability are considered, optimal component type selection suggestions are provided for users, the efficiency and accuracy of component type selection in PCB design are improved, the cost is reduced, and intelligent development in the field of PCB design of electronic products is promoted.

The invention discloses a verification platform code checking method and device, electronic equipment and a storage medium, and relates to the technical field of chip verification, and the method comprises the steps: obtaining a to-be-checked and verified platform code, and determining a target checking rule configuration file based on the to-be-checked and verified platform code; analyzing the to-be-checked and verified platform code to obtain an abstract syntax tree corresponding to the to-be-checked and verified platform code; based on the abstract syntax tree, generating a dependency graph of components in the to-be-checked and verified platform code; and based on the target check rule configuration file, the abstract syntax tree and the dependency graph, performing static check on the to-be-checked and verified platform code to obtain an error check report of the to-be-checked and verified platform code. The technical problem of low inspection efficiency caused by lack of customized inspection processes and inspection rules in related technologies is solved, and the technical effect of improving the inspection efficiency is achieved.

The embodiment of the invention provides an intelligent terminal SoC prototype verification method and system based on FPGA partial dynamic reconstruction. The method comprises the steps of obtaining a predetermined dynamic module and a predetermined static module; wherein the dynamic module and the static module are obtained by adaptively dividing hardware resources of a mobile intelligent terminal chip; performing prototype joint verification based on the dynamic module and the static module to generate a coverage rate report; if the coverage rate report represents that an error exists, a dynamic module hot update mode is selected; determining an error type in a dynamic module hot update mode; according to the error type, error repair is carried out, and a repaired file is obtained; and performing joint simulation and system operation verification based on the repaired file to obtain a verification result of the SoC prototype of the mobile intelligent terminal. According to the scheme, the verification efficiency of the SoC prototype of the intelligent terminal can be improved.

The invention relates to the technical field of software simulation operation simulation, and discloses a software logic simulation operation control method and system in an audio processor. The control method is applied to logic simulation operation control equipment and specifically comprises the following steps that S101, an audio processor simulation operation request sent by a user side is received, a graphical user interface is generated according to the operation request, and the graphical user interface comprises a logic module list area, a design editing area, an attribute bar and an information display area; and the user side drags an icon of a logic circuit element from the logic module list area to the design editing area. Through a highly integrated graphical interface and intelligent interactive design, the design and simulation efficiency of an audio processor logic circuit is remarkably improved, and by adopting a'drag-and-generate 'module instantiation mechanism, an attribute bidirectional real-time synchronization technology and visual connection and signal type inspection, the reliability of the audio processor logic circuit is greatly improved. Therefore, the user can intuitively and quickly construct the complex circuit topology, and the professional threshold is greatly reduced.