143 results about "Path delay" patented technology

The invention relates to the technical field of chip design, and provides a critical path screening method based on a chip time sequence report, which comprises the following steps: collecting chip time sequence report data, screening out first N critical paths from the data based on time sequence index data, and establishing a path ID-delay type-scene three-dimensional data model; and calculating the delay ratio of the unit delay to the interconnection line delay in each critical path. Performing single-type delay, type relevance and RC condition influence comparison on different scenes to obtain delay characteristic data. The invention discloses a system for executing the method, which can avoid full data redundancy and improve the analysis efficiency by screening the first N critical paths. And the delay change rule in different scenes is quantified. The delay characteristic data reflects the actual influence of the key path delay on the time sequence, so that a designer can quickly position the delay bottleneck of the key path, and a basis and a reference are provided for the targeted optimization of the total delay of the chip in the later period.

The invention relates to the technical field of computer task scheduling, in particular to a server integration system based on edge computing, which comprises a topological path delay analysis module, a multi-dimensional priority mapping scheduling module, a cross-architecture performance conversion module, a dynamic priority rearrangement module and a task migration optimization module. According to the method, more dynamic and flexible task scheduling is realized by accurately analyzing communication delay and network topology characteristics between edge nodes and based on comprehensive evaluation of node performance and delay weight, the intelligent level of task allocation is improved, and the limitation of static load detection is effectively avoided; the adaptability of the system to inter-node communication delay and execution time offset is enhanced, a task migration strategy is optimized, reasonable allocation and efficient execution of tasks among heterogeneous nodes are ensured, performance waste caused by improper resource scheduling is reduced, the utilization rate of resources and the overall performance of the system are improved, and the service life of the system is prolonged. And the dynamic response capability of task scheduling in the edge computing environment is enhanced.

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

The invention relates to a method for operating a transceiver device (1), comprising the following steps to be performed by the transceiver device (1): transmitting a pulse radio signal (5) at a given time; receiving a reflected signal of the transmitted pulse radio signal (5); generating a channel impulse response that describes the reflected signal as a function of a path delay; determining a self-interference distance range of the path delay of the channel impulse response, wherein the reflected signal of the self-interference distance range describes a self-interference signal of the transceiver device (1); determining at least one target distance range of the path delay of the channel impulse response, wherein the reflected signal of the target distance range describes a signal of the target distance range;Determining a signal component of the target distance range signal correlated with the self-interference signal using an operator, wherein the operator maps the self-interference signal to the correlated signal component of the target distance range signal; determining a signal component of the signal uncorrelated with the self-interference signal by removing the signal component correlated with the self-interference signal using a correlation cancellation filter.

The invention provides a time synchronization method executed by slave equipment, and the method comprises the steps: receiving a time synchronization packet from master equipment, and obtaining the packet transmitting time of the master equipment and the packet receiving time of the slave equipment; calculating a clock offset value between the slave device and the master device based on the packet transmitting time of the master device, the packet receiving time of the slave device and the path delay calibration value, and correcting a local clock of the slave device; wherein the path time delay calibration value is related to the distance between the master device and the slave device. The method can correct the clock skew between the master device and the slave device in real time, and improves the time synchronization precision.

In a non-volatile memory system of a memory controller connected to a number of memory dies in which the memory dies use an unmatched architecture for the data input path of the memory dies, the data signals and clock signals from the controller may not align properly when they reach the data latches of the memory die's receiver circuit. To account for possible mis-match, the controller can compensate by individually determining and introducing a corresponding one of multiple relative delay values to the clock signal path. Which delay parameter value is used for each die can be determined based on the power consumed by the memory die when data is transmitted using the different delay values.

The invention relates to the technical field of integrated circuits and provides a command address bus training method and training device. Through optimization design of test signals and overall optimization design of the training method, influences of factors such as device characteristics, path delay, wiring layout and signal quality are fully considered, comprehensive analysis of signal integrity and power supply integrity is considered, training accuracy and signal stability are improved, and the method is suitable for being used in a large-scale industrial production line. The method is beneficial to meeting the requirements of a high-performance memory in the aspects of state alignment and synchronization, supports higher data transmission rate and higher working frequency, and is beneficial to meeting the requirements of applications such as a data center, a high-performance server, an artificial intelligence infrastructure and the like on data transmission and high-speed interconnection.

The invention relates to the technical field of water conservancy project automation control, and discloses a self-adaptive coordinated regulation gate control method and system and a storage medium. The method comprises the following steps: acquiring gate node real-time instruction data and performing time synchronization calibration to generate an initial instruction sequence; instruction features are extracted and classified based on the sequence, and an instruction sorting list is obtained; when the emergency instruction proportion exceeds a threshold value, the emergency instruction is separated, an exclusive channel is distributed, an accelerated propagation path is generated, and an optimized transmission path is determined through path delay evaluation; selecting a path with the lowest delay from the optimized paths to perform emergency instruction distribution, and acquiring a feedback signal; verifying the feedback signal and recording a response speed index, and determining the adjusted transmission configuration based on the index; the configuration is utilized to synchronize and integrate the conventional instructions to the main propagation sequence to generate a complete regulation and control instruction set. According to the method, the multi-node instruction time sequence consistency and the emergency response capability are improved, the transmission conflict is reduced, and the cooperative regulation and control efficiency is improved.

The invention provides a space-time synchronization method and device of an unmanned aerial vehicle group, a medium and equipment, and the method comprises the steps: obtaining the space information of a slave node, adjusting the position of the slave node to meet the position condition of a master node, and enabling the master node to transmit information to the slave node and receive the response information of the slave node, the method comprises the following steps: calculating clock skew and path delay in combination with sending information and response information, calibrating the time of a slave node according to the clock skew and the path delay, finally testing the synchronization precision of a master node and the slave node by adopting pulses, determining synchronization completion when the precision requirement is met, and performing time-space synchronization calibration by utilizing each unmanned aerial vehicle in an unmanned aerial vehicle group so as to improve the operation precision of the unmanned aerial vehicle group. Therefore, the consistency and robustness of cooperative operation of the unmanned aerial vehicle group are improved.

The invention relates to the technical field of pulse neural network computing hardware, in particular to a neural network computing circuit of a pulse self-attention mechanism. According to the method, invalid or inefficient pulse events are dynamically screened through the hardware mask module, the operation number is remarkably reduced, and calculation path delay and logic resource occupation are reduced; meanwhile, in order to adapt to novel networks with binary architecture such as QKFormer, calculation and storage of a V matrix are eliminated, and storage resources and calculation resources are further reduced; in addition, the event coding module only generates active neuron events, and input sparsity is achieved. A configurable IF neuron model is adopted, exponential operation is avoided, hardware implementation is facilitated, and the method is suitable for binary network deployment. The modular architecture can support function extension, assembly line and parallel work; and the parallelism degree of the design can be determined according to the actual data pulse distribution rate. Event driving and mask pruning are combined, so that the overall computing resources of the circuit are greatly reduced, and the power consumption is reduced.

A congestion control method and apparatus, a device, a storage medium, and a program product. The method comprises: acquiring a response delay corresponding to a terminal device, wherein the response delay is a duration between an update moment of a pointer to be acknowledged and the current moment, and said pointer refers to the sequence number of a first byte that has been sent by the terminal device but for which an acknowledgment message has not yet been received; acquiring a path delay of each virtual link among a plurality of virtual links corresponding to the terminal device, wherein the path delay is determined on the basis of transmission round-trip durations corresponding to a plurality of data packets on the virtual link; and adjusting a congestion window of the terminal device on the basis of the response delay, and on the basis of the path delay of each virtual link, performing load balancing processing on a plurality of physical links corresponding to the plurality of virtual links, wherein the congestion window is used for indicating the maximum data volume the terminal device may consecutively send. The congestion control method can reduce network congestion and improve the load balancing effect of physical links.

Techniques are disclosed for computing a cost of an advertised route to a next-hop network device along a path to a destination based at least in part on a preference for the path. In one example, a computing system computes a cost of a route to a next-hop network device along a path to a destination. The computed cost is based at least in part on (1) a metric for the route and (2) a preconfigured preference for the path. In some examples, the preference for the path is based at least in part on (a) a type of the path as compared to other types of other paths to the destination or (b) a latency of the path as compared to other latencies of the other paths. The computing system sends a route advertisement for the route that includes data indicative of the cost of the route.

Methods and apparatuses for comparing redundant signals in functional safe systems are provided, including methods for mitigating differing signal path delays and for signal weighting of the redundant signals are proposed. An Apparatus includes a first signal path for a first measurement signal of a physical quantity, the first signal path having a first signal propagation delay; a second signal path for a second measurement signal of the physical quantity, the second signal path having a second signal propagation delay different from the first signal propagation delay; a delay compensation circuit configured to compensate for a difference between the first and second signal propagation delays to generate delay-compensated first and second measurement signals; and comparison circuitry configured to compare the delay-compensated first and second measurement signals.

The invention provides a message flow control method, system and device and a readable storage medium. The method comprises the following steps: carrying out fragmentation processing on an input message according to a preset fragmentation size, and generating a plurality of message fragments cached in a fragmentation FIFO (First In First Out); performing length accumulation on each message fragment, wherein an accumulated value is associated with an actual length of the message fragment and a message length variation caused by encryption and decryption or message editing processing; and when the accumulated value reaches a preset boundary value, resetting the accumulated value and enabling the flow control value to execute self-adding operation. Compared with the prior art, the method has the advantages that the flow control design universality is high, the method can adapt to message length changes in scenes such as encryption, decryption or message editing, and accurate and synchronous flow control value operation is ensured; secondly, the depth of the recombined FIFO is only related to the delay of the main path and does not change along with the increase of the number of ports, so that the chip area and the power consumption are reduced; in addition, the flow control is triggered by the accumulated length boundary, and the resource efficiency and the system reliability are improved.

The present invention relates to the field of mobile communications technology, and in particular to a 5G-based ad hoc network system routing selection method and readable storage medium. The method comprises the following steps: S100, obtaining the path delay and performance parameters of intermediate nodes for each path between a first node and a second node; S200, calculating characteristic values ​​of each path based on the path delay and performance parameters; and S300, selecting a path as the routing path between the first node and the second node based on the characteristic values ​​of each path. This solution can intelligently select a more suitable route for users in different application environments, enabling 5G networks and ad hoc networks to fully leverage their respective advantages and improve network transmission efficiency.

A radar device includes a transmitter and receiver circuit and an estimation circuit. The transmitter and receiver circuit is configured to generate a second signal according to a first signal. The estimation circuit is coupled to the transmitter and receiver circuit and is configured to generate an estimated path delay according to the second signal for a back-end circuit to execute a related application.

This invention relates to the field of satellite communication technology, specifically to a dynamic routing method for large-scale low-Earth orbit (LEO) satellites that adapts to network queuing delay. Based on a greedy heuristic approach for dynamic routing in large-scale LEO satellite networks, it utilizes parameters such as satellite communication distance and direction, the estimated minimum number of hops from the current satellite to the receiving location, the average queuing delay in the network, and the queuing delay of the next-hop relay satellite. A value function is proposed to find the next-hop satellite, where the function value reflects the distance traveled to the receiving location in a single-hop transmission and the magnitude of the relay satellite's queuing delay. By plotting the change curves of the weights corresponding to the shortest transmission path delay versus the average satellite queuing delay, the optimal weights are found as the average queuing delay changes, thus achieving adaptive network load conditions. Verification shows that, compared to other routing methods that allow non-adjacent satellites to use ISL communication, this invention has the advantage of shorter total delay for networks with different on-board queue load conditions.

The application relates to the technical field of integrated circuits and provides a command address bus training method and a training device. Through optimization design of a test signal and overall optimization design of a training method, the influence of factors such as device characteristics, path delay, wire layout and signal quality is fully considered, and comprehensive analysis of signal integrity and power integrity is considered, so that the accuracy of training and signal stability are improved, the demand of high-performance memory in state alignment and synchronization is met, a higher data transmission rate and a higher working frequency are supported, and the demand of data centers, high-performance servers, artificial intelligence infrastructure and the like on data transmission and high-speed interconnection is met.

Embodiments of the present application provide a time delay measurement circuit, method, chip and electronic device. The time delay measurement circuit is applied to a chip. The time delay measurement circuit comprises a measurement circuit, a copy circuit and a crosstalk circuit. The chip further comprises a timing circuit. The copy circuit is a copy of the timing circuit. The measurement circuit is connected to the copy circuit. The copy circuit is further connected to the crosstalk circuit. The copy circuit is used to simulate a data signal in the timing circuit. The crosstalk circuit is used to generate a crosstalk signal. The crosstalk signal is used to interfere with the data signal. The measurement circuit is used to measure a path delay of the copy circuit interfered by the crosstalk signal. The path delay of the copy circuit is used to predict a time delay or a frequency of the chip. The accuracy of predicting the time delay or the frequency of the chip is improved.

The invention discloses an Ethernet clock phase synchronization method and a related device, and the method comprises the steps: obtaining a sending timestamp and a receiving timestamp through a time synchronization protocol, and calculating the time offset between a master clock and a slave clock according to the sending timestamp and the receiving timestamp; a delay configuration signal including the transmit and receive path delay control value is then generated. Control values are respectively input to programmable delay arrays on a sending path and a receiving path, and the number of unit delay units through which clock signals pass is dynamically controlled, so that the phases of a sending clock and a receiving sampling clock are accurately adjusted. According to the method, a circuit structure with unit delay time is utilized, refined dynamic compensation of the clock phase is achieved, and Ethernet clock synchronization precision and system data transmission reliability are effectively improved.

The invention discloses a Gray code synchronization detection method and device, equipment and a medium, and relates to the technical field of communication. The path information and the clock arrival information corresponding to the time sequence parameters are automatically extracted and acquired, errors caused by manual inspection are avoided, and the inspection precision is improved. The corresponding path delay time is determined according to the time sequence parameters of the multiple Gray code synchronization paths, the maximum path delay deviation is determined based on the multiple path delay time, the maximum delay deviation between different bits corresponding to different asynchronous registers is determined, and the single-bit change characteristic of the Gray codes is ensured. The Gray code synchronization strategy is determined according to the relation between the maximum path delay deviation and the preset path delay deviation, if the maximum path delay deviation is larger than the preset path delay deviation, it is indicated that the potential multi-bit flipping risk exists, and consequently the empty and full state judgment of the FIFO is wrong, and the Gray code synchronization strategy is adopted to adjust the Gray code generation circuit, so that the FIFO generation efficiency is improved. The data error risk in the design is reduced, and powerful guarantee is provided for high-reliability design.

The invention relates to a method for operating a transceiver device (1), comprising the following steps to be carried out by the transceiver device (1): transmitting an impulse radio signal (5) at a point in time; receiving a reflected signal of the transmitted impulse radio signal (5); generating a channel impulse response, which describes the reflected signal according to a path delay; determining a self-interference distance range of the path delay of the channel impulse response, wherein the reflected signal of the self-interference distance range describes a self-interference signal of the transceiver device (1); determining at least one target distance range of the path delay of the channel impulse response, wherein the reflected signal of the target distance range describes a signal of the target distance range; ascertaining a signal component of the signal of the target distance range correlated with the self-interference signal by means of an operator, wherein the operator maps the self-interference signal onto the correlated signal component of the signal of the target distance range; ascertaining a signal component of the signal uncorrelated with the self-interference signal by removing the signal component of the signal correlated with the self-interference signal by means of a correlation cancellation filter.

The application relates to the technical field of chip design, and particularly discloses a routing method and system based on timing criticality, which abstracts physical layout into a node network, constructs a weighted cost function of total wiring length and critical path length, adopts a minimum spanning tree algorithm to iteratively expand a path and record a parasitic parameter, calculates a merging cost value based on the product of the length of a coincident path and the timing criticality of a node, generates a virtual node by merging a node pair with the maximum benefit, and cyclically optimizes until a convergence condition is met, so that the dual objectives of wiring resource optimization and timing critical path delay reduction are achieved. The method is based on a more accurate time delay model, defines a target function which comprehensively considers the overall routing cost and the routing cost of a timing critical load node, makes timing analysis more accurate, reduces the signal delay and the size of a clock cycle of a load node according to the criticality of the load node, and effectively increases the running speed of a chip.

The application discloses a kind of multi-modal wearable sensor data fusion-oriented timing synchronization method, system, terminal and storage medium, the method includes: obtaining absolute timestamp as global clock source;Global clock source is as the master clock of precision time protocol, a plurality of wearable sensors are configured as slave clock, through precision time protocol, multiple rounds of message interaction are performed between master clock and slave clock, and the timestamp corresponding to each round of interaction is obtained;According to the corresponding timestamp, the current path delay and the current clock offset are calculated, and according to the preset path delay threshold and clock offset threshold, the current path delay and the current clock offset are iteratively judged, whether the local clock is corrected according to the current clock offset is determined according to the iterative judgment result, until slave clock and global clock source achieve timing synchronization;After achieving time synchronization, the periodic data sampling tasks of a plurality of wearable sensors are phase-aligned.The application significantly improves timing synchronization accuracy.

The invention relates to a route planning method and device based on network intelligent agents, a medium and equipment, and relates to the technical field of computer networks, and the method comprises the steps that a state management layer constructs a distributed network topological graph according to the network intelligent agents and the connection relation between the network intelligent agents; wherein the network agent comprises at least one of a local agent, a regional agent and a global agent; the MCP coordination layer determines a network state vector according to the distributed network topological graph; the routing decision layer determines candidate path delay, candidate path congestion cost, candidate path packet loss rate and candidate link utilization rate of the candidate routing path according to the network state vector; and the routing decision layer determines a target routing path from the candidate routing paths according to the candidate path delay, the candidate path congestion cost, the candidate path packet loss rate and the candidate link utilization rate. The path planning efficiency is improved.

The application discloses a method and system suitable for segment delay measurement of an audio decoder, comprising the following steps: writing periodic waveform data with a preset size into a DAC unit in response to a first excitation signal, and carrying out digital-to-analog conversion on the periodic waveform data through the DAC unit; inputting an audio signal obtained through the digital-to-analog conversion into an ADC unit through an audio line, and carrying out analog-to-digital conversion on the audio signal through the ADC unit; transmitting data obtained through the analog-to-digital conversion to the DAC unit, so as to enter the next cycle of digital-to-analog conversion; determining at least two of a first time, a second time, a third time and a fourth time; and determining at least one of a first complete path delay, a DAC delay, a decoding software delay and an ADC delay according to the at least two of the first time, the second time, the third time and the fourth time. The application can measure the segment delay of audio decoding.

This application discloses a method and system for inter-symbol interference cancellation in ultra-long-delay air-to-ground communication scenarios, comprising: calculating the required guard interval length before signal transmission; acquiring a received signal; wherein the received signal includes an improved data frame; the improved data frame includes a pre-group training sequence and a post-group training sequence with consistent unit sequence length, and a guard interval; calculating a direct path Doppler frequency offset estimate based on the pre-group training sequence; calculating a reflection path Doppler frequency offset estimate based on the post-group training sequence; determining a reflection path delay estimate based on the reflection path Doppler frequency offset estimate and the guard interval length; and eliminating inter-symbol interference based on the calculated estimates to obtain orthogonal frequency division multiplexing symbols. This application can stably and efficiently eliminate inter-symbol interference in high-mobility, high-delay, and high-speed air-to-ground patrol scenarios, and can be widely applied in the field of communication technology.

The invention provides a processing method for sending a data packet, which comprises the following steps of: receiving a notification sent by a host, and analyzing the notification to obtain an address of a sending queue entry; reading and analyzing the sending queue entry according to the address of the sending queue entry, and obtaining an enable bit signal of the sending queue entry, data initial address information of a to-be-sent data packet and data total length information of the to-be-sent data packet; acquiring data corresponding to the plurality of to-be-sent data packets in a cache region through a single PCIE read operation; and obtaining effective data of each to-be-sent data packet according to the data initial address information and the data total length information, and sending the effective data of each to-be-sent data packet. The invention further discloses a corresponding device and system, a storage medium and a chip product. By implementing the method and the device, the PCIE reading operation times required when the DPU reads the items and the cache data in the host can be reduced, and the path delay is reduced, so that the communication performance is effectively improved.

The invention discloses an FPGA (Field Programmable Gate Array) signal negotiation distribution method supporting dynamic networking. The method comprises the following steps: establishing a mapping relationship between FPGA nodes and logic nodes; calculating the shortest path between all FPGA pairs, counting the number of networks on each physical channel, and calculating an initial TDM ratio and path delay; introducing a relaxation ratio and a criticality ranking mechanism, performing iterative wiring optimization based on a dynamic cost function, and updating a weight topological graph; physical channels with TDM ratio overrun and serious congestion are identified, physical topology is reconstructed through channel addition, deletion and transfer operations, and channel resource allocation is guided based on comprehensive ranking scores of three types of constraint factors; according to the method, the PathFinder wiring and the topology reconstruction process are cooperatively executed, signal distribution is carried out again based on the wiring result of the last round after topology adjustment each time, a final wiring path and a reconstructed topology structure are output, the maximum path delay is reduced, and the wiring quality of a large-scale FPGA system is improved.

The present invention discloses a beam steering optimization method and system for millimeter wave networks, relating to the technical field of beam steering optimization, and comprising the following steps: using a DTW algorithm and a dynamic time warping algorithm to match the multi-hop path delay characteristics between a base station and a user device, and screening the optimal reflection path sequence; obtaining the path topology, constructing a quadratic unconstrained binary optimization model and solving it through quantum annealing to obtain a discrete phase distribution; calculating the quantization error of the discrete phase and using an interpolation algorithm to compensate in the frequency domain to obtain a phase compensation vector; loading the compensation vector into programmable metasurface hardware to form a reflection link, and constructing a phase error covariance matrix; incrementally correcting the weight parameters of the optimization model based on the matrix; finally, combining the corrected weights and the compensation vector to construct an objective function to achieve channel capacity optimization, thereby solving the problems of difficult multi-hop path selection, insufficient phase error compensation, and high complexity of beam optimization in millimeter wave communications, and improving channel capacity and communication quality.