191 results about "Path delay" patented technology

The embodiment of the invention provides a clock domain crossing path checking method and device and a related device.The method comprises the steps that a clock domain crossing path set designed by a chip is obtained, and each clock domain crossing path in the clock domain crossing path set comprises a source clock domain and a target clock domain which are different in clock domain; the source clock domain and the target clock domain of each cross-clock-domain path are subjected to clock domain constraint, equivalent synchronous time sequence paths are obtained, and the source clock domain and the target clock domain of each equivalent synchronous time sequence path are from the same clock domain under the clock domain constraint; performing time sequence analysis on the equivalent synchronous time sequence path to obtain path delay information; and checking the corresponding cross-clock-domain path based on the path delay information of the equivalent synchronous time sequence path to obtain a check result of the cross-clock-domain path. According to the technical scheme provided by the embodiment of the invention, the path comprehensiveness and completeness when the time sequence analysis is carried out on the clock domain crossing path can be improved, and the time sequence analysis accuracy of the clock domain crossing path is improved.

The invention relates to the technical field of chip design, and provides a critical path screening method based on a chip time sequence report, which comprises the following steps: collecting chip time sequence report data, screening out first N critical paths from the data based on time sequence index data, and establishing a path ID-delay type-scene three-dimensional data model; and calculating the delay ratio of the unit delay to the interconnection line delay in each critical path. Performing single-type delay, type relevance and RC condition influence comparison on different scenes to obtain delay characteristic data. The invention discloses a system for executing the method, which can avoid full data redundancy and improve the analysis efficiency by screening the first N critical paths. And the delay change rule in different scenes is quantified. The delay characteristic data reflects the actual influence of the key path delay on the time sequence, so that a designer can quickly position the delay bottleneck of the key path, and a basis and a reference are provided for the targeted optimization of the total delay of the chip in the later period.

The invention relates to a terminal device communication transmission method and device based on a single-soldier ad hoc network and a medium. Reliability is improved through a dynamic dual-mode compensation mechanism. The method specifically comprises the following steps: a terminal establishes a main communication mode (including an initial routing and transmission protocol) based on dynamic topology, and establishes a complementary auxiliary communication mode (different routing strategies or protocols but consistent capacities); dual modes are bound into a redundancy group, state differences are monitored in real time, and untransmitted data packets / path delays are associated with dynamic identification bits; performing compensation transmission on difference data pointed by the identification bit through an auxiliary mode, and clearing the identification bit after the compensation transmission is completed; and if the redundant group has no residual identification bit, terminating the main mode and switching the auxiliary mode to dominate transmission. The network state and the compensation requirement are accurately associated through the dynamic identification bit, self-adaptive compensation of difference data is achieved, waste of redundant resources is avoided, and meanwhile the end-to-end communication success rate in the high dynamic environment is ensured through the dual-mode complementary characteristic.

The invention discloses a combinational logic clustering optimization method and system based on reinforcement learning. The method comprises the following steps: S1, counting fan-out information of registers and combinational logic units in a circuit netlist; s2, according to the fan-out information, screening out registers and combinational logic units of which the fan-out quantity is greater than a first preset threshold and the worst time sequence path time sequence violation value of the output signal is smaller than a second preset threshold, and generating a target unit list; s3, acquiring fan-out combinational logic information of each unit in the target unit list; s4, on the basis of the fan-out combinatorial logic information, clustering operation is carried out on fan-out logic units on the basis of a reinforcement learning algorithm; s5, after logic clustering is completed, revising the netlist of the circuit; after the revision is completed, carrying out equivalence check; and S6, rearranging and wiring the circuit according to the modified netlist. The method can effectively reduce key path delay, optimizes circuit performance, and is especially suitable for large-scale integrated circuit design.

The invention relates to the technical field of computer task scheduling, in particular to a server integration system based on edge computing, which comprises a topological path delay analysis module, a multi-dimensional priority mapping scheduling module, a cross-architecture performance conversion module, a dynamic priority rearrangement module and a task migration optimization module. According to the method, more dynamic and flexible task scheduling is realized by accurately analyzing communication delay and network topology characteristics between edge nodes and based on comprehensive evaluation of node performance and delay weight, the intelligent level of task allocation is improved, and the limitation of static load detection is effectively avoided; the adaptability of the system to inter-node communication delay and execution time offset is enhanced, a task migration strategy is optimized, reasonable allocation and efficient execution of tasks among heterogeneous nodes are ensured, performance waste caused by improper resource scheduling is reduced, the utilization rate of resources and the overall performance of the system are improved, and the service life of the system is prolonged. And the dynamic response capability of task scheduling in the edge computing environment is enhanced.

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

The invention relates to a method for operating a transceiver device (1), comprising the following steps to be performed by the transceiver device (1): transmitting a pulse radio signal (5) at a given time; receiving a reflected signal of the transmitted pulse radio signal (5); generating a channel impulse response that describes the reflected signal as a function of a path delay; determining a self-interference distance range of the path delay of the channel impulse response, wherein the reflected signal of the self-interference distance range describes a self-interference signal of the transceiver device (1); determining at least one target distance range of the path delay of the channel impulse response, wherein the reflected signal of the target distance range describes a signal of the target distance range;Determining a signal component of the target distance range signal correlated with the self-interference signal using an operator, wherein the operator maps the self-interference signal to the correlated signal component of the target distance range signal; determining a signal component of the signal uncorrelated with the self-interference signal by removing the signal component correlated with the self-interference signal using a correlation cancellation filter.

Provided is a communication method, comprising: a network device sending a plurality of signals to a terminal device, the terminal device reporting measurement information to the network device after measuring the plurality of signals, the measurement information comprising first path time delay information of at least one signal in the plurality of signals, or an identifier of a first signal, the first signal is the signal with the minimum first path time delay in the plurality of signals. Therefore, the network equipment can determine whether the LOS path exists between the terminal equipment and the network equipment or not based on the measurement information fed back by the terminal equipment, so that the network equipment can judge whether the communication performance with the terminal equipment should be enhanced by using the sensing information of the terminal equipment or not.

The invention provides a time synchronization method executed by slave equipment, and the method comprises the steps: receiving a time synchronization packet from master equipment, and obtaining the packet transmitting time of the master equipment and the packet receiving time of the slave equipment; calculating a clock offset value between the slave device and the master device based on the packet transmitting time of the master device, the packet receiving time of the slave device and the path delay calibration value, and correcting a local clock of the slave device; wherein the path time delay calibration value is related to the distance between the master device and the slave device. The method can correct the clock skew between the master device and the slave device in real time, and improves the time synchronization precision.

In a non-volatile memory system of a memory controller connected to a number of memory dies in which the memory dies use an unmatched architecture for the data input path of the memory dies, the data signals and clock signals from the controller may not align properly when they reach the data latches of the memory die's receiver circuit. To account for possible mis-match, the controller can compensate by individually determining and introducing a corresponding one of multiple relative delay values to the clock signal path. Which delay parameter value is used for each die can be determined based on the power consumed by the memory die when data is transmitted using the different delay values.

The invention relates to the technical field of integrated circuits and provides a command address bus training method and training device. Through optimization design of test signals and overall optimization design of the training method, influences of factors such as device characteristics, path delay, wiring layout and signal quality are fully considered, comprehensive analysis of signal integrity and power supply integrity is considered, training accuracy and signal stability are improved, and the method is suitable for being used in a large-scale industrial production line. The method is beneficial to meeting the requirements of a high-performance memory in the aspects of state alignment and synchronization, supports higher data transmission rate and higher working frequency, and is beneficial to meeting the requirements of applications such as a data center, a high-performance server, an artificial intelligence infrastructure and the like on data transmission and high-speed interconnection.

The invention relates to the technical field of water conservancy project automation control, and discloses a self-adaptive coordinated regulation gate control method and system and a storage medium. The method comprises the following steps: acquiring gate node real-time instruction data and performing time synchronization calibration to generate an initial instruction sequence; instruction features are extracted and classified based on the sequence, and an instruction sorting list is obtained; when the emergency instruction proportion exceeds a threshold value, the emergency instruction is separated, an exclusive channel is distributed, an accelerated propagation path is generated, and an optimized transmission path is determined through path delay evaluation; selecting a path with the lowest delay from the optimized paths to perform emergency instruction distribution, and acquiring a feedback signal; verifying the feedback signal and recording a response speed index, and determining the adjusted transmission configuration based on the index; the configuration is utilized to synchronize and integrate the conventional instructions to the main propagation sequence to generate a complete regulation and control instruction set. According to the method, the multi-node instruction time sequence consistency and the emergency response capability are improved, the transmission conflict is reduced, and the cooperative regulation and control efficiency is improved.

The invention discloses a communication emergency roundabout route switching method and system and electronic equipment, and the method comprises the steps: obtaining each piece of communication network state data of a current communication path, and dividing the communication network state data into first-level data, second-level data and third-level data; for the hierarchy data corresponding to each hierarchy, determining a weighted total value corresponding to the hierarchy data, and calculating a comprehensive communication network state weight corresponding to the current communication path based on the weighted total value; determining a network state corresponding to the current communication path based on the comprehensive communication network state weight and a preset communication network health state threshold; when the network state is abnormal, determining an optimal roundabout path based on the path delay and the transmission quality of each available roundabout path; and generating a path switching scheme based on the optimal roundabout path to switch the current communication path to the optimal roundabout path. According to the scheme of the invention, the evaluation precision of the current network state and the response speed and precision of path switching are improved.

The invention discloses a near-field CSI distributed estimation method for broadband XL-MIMO, and the method comprises the steps: firstly, enabling a center LPU to estimate a path time delay parameter of a center sub-array channel, enabling other LPUs to rapidly extrapolate the path time delay parameters of other sub-array channels, and transmitting an estimation result to a CPU; then, based on near-field wave beam squint and parameter symmetry characteristics brought by a large array and a large bandwidth, the CPU fuses time delay parameters estimated by different sub-arrays, and decouples and independently estimates near-field channel parameters including angle, distance and range parameters; then, the CPU transmits the estimated near-field channel parameters back to the LPUs, and each LPU independently estimates the path gain of the sub-array channel; and finally, transmitting the estimated path gain to a CPU (Central Processing Unit) by the LPUs, and further reconstructing a full-dimensional broadband near-field channel. The problems that the CSI acquisition calculation complexity is too high and the reconstruction precision is low in a large-array and large-bandwidth scene are solved.

The invention provides a space-time synchronization method and device of an unmanned aerial vehicle group, a medium and equipment, and the method comprises the steps: obtaining the space information of a slave node, adjusting the position of the slave node to meet the position condition of a master node, and enabling the master node to transmit information to the slave node and receive the response information of the slave node, the method comprises the following steps: calculating clock skew and path delay in combination with sending information and response information, calibrating the time of a slave node according to the clock skew and the path delay, finally testing the synchronization precision of a master node and the slave node by adopting pulses, determining synchronization completion when the precision requirement is met, and performing time-space synchronization calibration by utilizing each unmanned aerial vehicle in an unmanned aerial vehicle group so as to improve the operation precision of the unmanned aerial vehicle group. Therefore, the consistency and robustness of cooperative operation of the unmanned aerial vehicle group are improved.

The invention discloses a multi-service edge network cache optimization method based on delayed hit, which belongs to the field of edge computing and online caching, and comprises the following steps: deciding an optimal request processing path by analyzing a local cache hit state, adjacent server cache distribution and relay path delay in real time; detecting the remaining time window of the current file acquisition operation, and dynamically evaluating the cost of waiting for a delay hit or triggering a new operation; selecting a target server based on weight sorting, dynamically eliminating low-weight files, and reducing cache conflicts in combination with a cross-server redundancy elimination mechanism; when the local cache and the relay path do not meet the delay constraint, dynamically evaluating the cloud response time and bandwidth cost of the bypassing operation, and determining the feasibility of the bypassing operation; the file weight is dynamically calculated based on historical request characteristics and operation delay, the file replacement cost is quantified by combining the cache state and the residual capacity of the server, and the average retrieval delay of user requests can be greatly reduced.

The invention relates to the technical field of pulse neural network computing hardware, in particular to a neural network computing circuit of a pulse self-attention mechanism. According to the method, invalid or inefficient pulse events are dynamically screened through the hardware mask module, the operation number is remarkably reduced, and calculation path delay and logic resource occupation are reduced; meanwhile, in order to adapt to novel networks with binary architecture such as QKFormer, calculation and storage of a V matrix are eliminated, and storage resources and calculation resources are further reduced; in addition, the event coding module only generates active neuron events, and input sparsity is achieved. A configurable IF neuron model is adopted, exponential operation is avoided, hardware implementation is facilitated, and the method is suitable for binary network deployment. The modular architecture can support function extension, assembly line and parallel work; and the parallelism degree of the design can be determined according to the actual data pulse distribution rate. Event driving and mask pruning are combined, so that the overall computing resources of the circuit are greatly reduced, and the power consumption is reduced.

The invention relates to a low-orbit satellite constellation system frequency hopping synchronization method, and belongs to the field of satellite communication. Calculating a relative distance delta L between the satellite and the terminal based on the satellite ephemeris; calculating path time delay delta T according to the relative distance delta L; calculating the relative speed delta V of the satellite and the terminal based on the satellite ephemeris; doppler frequency fd is calculated according to the relative speed delta V; based on the satellite ephemeris, calculating the relative acceleration delta alpha of the satellite and the terminal; calculating a Doppler change rate alpha f according to the relative acceleration delta alpha; based on the uplink synchronous detection signal, a time error estimation value delta T'is calculated by adopting a late early gate algorithm; calculating a frequency offset error estimation value delta fd by adopting an FFT-based frequency estimation algorithm; calculating time compensation Tsat'of the satellite and the terminal; calculating frequency compensation f'up of the satellite and the terminal; according to the invention, satellite-ground rapid time-frequency coarse synchronization under a low-orbit satellite system is realized, and satellite-ground time-frequency fine synchronization is realized by further estimating the time-frequency difference of uplink synchronous detection signals of a terminal through a satellite and feeding back terminal compensation.

A congestion control method and apparatus, a device, a storage medium, and a program product. The method comprises: acquiring a response delay corresponding to a terminal device, wherein the response delay is a duration between an update moment of a pointer to be acknowledged and the current moment, and said pointer refers to the sequence number of a first byte that has been sent by the terminal device but for which an acknowledgment message has not yet been received; acquiring a path delay of each virtual link among a plurality of virtual links corresponding to the terminal device, wherein the path delay is determined on the basis of transmission round-trip durations corresponding to a plurality of data packets on the virtual link; and adjusting a congestion window of the terminal device on the basis of the response delay, and on the basis of the path delay of each virtual link, performing load balancing processing on a plurality of physical links corresponding to the plurality of virtual links, wherein the congestion window is used for indicating the maximum data volume the terminal device may consecutively send. The congestion control method can reduce network congestion and improve the load balancing effect of physical links.

The present invention relates to the technical field of wireless communication networks, and particularly to a V2V interaction method for vehicle ad-hoc networks based on intelligent connected vehicle WiFi. It collects vehicle motion state and network load data through in-vehicle sensors, dynamically switches between AP / STA modes by combining the Deep Q-Network (DQN) model and the ε-greedy strategy, and constructs an adaptive topology structure. It extends the OLSR protocol packet to embed a path delay field, optimizes multi-hop routing selection by combining pheromone gradient calculation, and realizes message priority classification and differential privacy protection through a federated learning model. Based on the particle swarm algorithm, it dynamically adjusts the AP / STA ratio threshold to trigger node role reconfiguration to balance network load. The present invention reuses existing WiFi hardware to reduce deployment costs, combines cross-layer routing optimization and a distributed decision-making mechanism, and improves network real-time performance, scalability, and group collaboration ability in dynamic scenarios.

Techniques are disclosed for computing a cost of an advertised route to a next-hop network device along a path to a destination based at least in part on a preference for the path. In one example, a computing system computes a cost of a route to a next-hop network device along a path to a destination. The computed cost is based at least in part on (1) a metric for the route and (2) a preconfigured preference for the path. In some examples, the preference for the path is based at least in part on (a) a type of the path as compared to other types of other paths to the destination or (b) a latency of the path as compared to other latencies of the other paths. The computing system sends a route advertisement for the route that includes data indicative of the cost of the route.

Methods and apparatuses for comparing redundant signals in functional safe systems are provided, including methods for mitigating differing signal path delays and for signal weighting of the redundant signals are proposed. An Apparatus includes a first signal path for a first measurement signal of a physical quantity, the first signal path having a first signal propagation delay; a second signal path for a second measurement signal of the physical quantity, the second signal path having a second signal propagation delay different from the first signal propagation delay; a delay compensation circuit configured to compensate for a difference between the first and second signal propagation delays to generate delay-compensated first and second measurement signals; and comparison circuitry configured to compare the delay-compensated first and second measurement signals.

The invention provides a round-trip delay correction method and system based on a reverse path timestamp. The round-trip delay correction method comprises the following steps: acquiring a data packet sending timestamp, an acknowledgement packet sending timestamp and an acknowledgement packet receiving timestamp; a reverse path time delay sample is dynamically stored through a sliding window, and reference time delay is calculated by selecting a minimum value method or a least square regression method according to the sample size; removing reverse path congestion interference in the round-trip delay according to a difference value between the current reverse path delay and the reference delay to obtain a corrected round-trip delay; and the reference time delay of the same source-destination pair is shared under the symmetric topology. According to the method, forward path congestion and reverse path congestion can be accurately separated, misjudgment caused by reverse path congestion of traditional RTT is avoided, and the bandwidth utilization rate and the short flow performance of a congestion control algorithm are improved; through hardware timestamp and dynamic baseline estimation, low-cost deployment without hardware transformation is realized, and the method is suitable for high-precision time delay optimization of the data center network.

The invention provides a message flow control method, system and device and a readable storage medium. The method comprises the following steps: carrying out fragmentation processing on an input message according to a preset fragmentation size, and generating a plurality of message fragments cached in a fragmentation FIFO (First In First Out); performing length accumulation on each message fragment, wherein an accumulated value is associated with an actual length of the message fragment and a message length variation caused by encryption and decryption or message editing processing; and when the accumulated value reaches a preset boundary value, resetting the accumulated value and enabling the flow control value to execute self-adding operation. Compared with the prior art, the method has the advantages that the flow control design universality is high, the method can adapt to message length changes in scenes such as encryption, decryption or message editing, and accurate and synchronous flow control value operation is ensured; secondly, the depth of the recombined FIFO is only related to the delay of the main path and does not change along with the increase of the number of ports, so that the chip area and the power consumption are reduced; in addition, the flow control is triggered by the accumulated length boundary, and the resource efficiency and the system reliability are improved.

The present invention relates to the field of mobile communications technology, and in particular to a 5G-based ad hoc network system routing selection method and readable storage medium. The method comprises the following steps: S100, obtaining the path delay and performance parameters of intermediate nodes for each path between a first node and a second node; S200, calculating characteristic values ​​of each path based on the path delay and performance parameters; and S300, selecting a path as the routing path between the first node and the second node based on the characteristic values ​​of each path. This solution can intelligently select a more suitable route for users in different application environments, enabling 5G networks and ad hoc networks to fully leverage their respective advantages and improve network transmission efficiency.

The present disclosure relates to a QED shifter for a memory device. The memory device includes a command interface configured to receive commands from a host device. The memory device also includes a command shifter configured to receive the commands. The command shifter includes a plurality of stages coupled in series and configured to delay the commands. The command shifter includes selection circuitry configured to receive the commands and select an insertion stage for the plurality of stages of the commands. The selection circuitry is configured to select the insertion stage as a location for inserting the commands. The selected insertion stage is selected to control a duration of a delay in the command shifter. The selection of the insertion stage is at least partially based on a path delay between a clock and a data pin of the memory device.

A radar device includes a transmitter and receiver circuit and an estimation circuit. The transmitter and receiver circuit is configured to generate a second signal according to a first signal. The estimation circuit is coupled to the transmitter and receiver circuit and is configured to generate an estimated path delay according to the second signal for a back-end circuit to execute a related application.

This invention relates to the field of satellite communication technology, specifically to a dynamic routing method for large-scale low-Earth orbit (LEO) satellites that adapts to network queuing delay. Based on a greedy heuristic approach for dynamic routing in large-scale LEO satellite networks, it utilizes parameters such as satellite communication distance and direction, the estimated minimum number of hops from the current satellite to the receiving location, the average queuing delay in the network, and the queuing delay of the next-hop relay satellite. A value function is proposed to find the next-hop satellite, where the function value reflects the distance traveled to the receiving location in a single-hop transmission and the magnitude of the relay satellite's queuing delay. By plotting the change curves of the weights corresponding to the shortest transmission path delay versus the average satellite queuing delay, the optimal weights are found as the average queuing delay changes, thus achieving adaptive network load conditions. Verification shows that, compared to other routing methods that allow non-adjacent satellites to use ISL communication, this invention has the advantage of shorter total delay for networks with different on-board queue load conditions.

The application relates to the technical field of integrated circuits and provides a command address bus training method and a training device. Through optimization design of a test signal and overall optimization design of a training method, the influence of factors such as device characteristics, path delay, wire layout and signal quality is fully considered, and comprehensive analysis of signal integrity and power integrity is considered, so that the accuracy of training and signal stability are improved, the demand of high-performance memory in state alignment and synchronization is met, a higher data transmission rate and a higher working frequency are supported, and the demand of data centers, high-performance servers, artificial intelligence infrastructure and the like on data transmission and high-speed interconnection is met.

The invention provides a method for repairing retention time violation. The method comprises the following steps: acquiring a network list and a layout result of an FPGA (Field Programmable Gate Array); the network list comprises a connection relationship between the target sending unit and the target receiving unit, and the layout result comprises respective layout coordinates of the target sending unit and the target receiving unit; the target sending unit and the target receiving unit are driven by the same time signal; based on the respective layout coordinates of the target sending unit and the target receiving unit, evaluating the path time delay of the connection path by using a static time sequence analysis tool; and when the path time delay is smaller than a path time delay threshold value, adding an unused lookup table of at least one FPGA into the connection relation, and on the premise of not changing a layout result, determining respective layout coordinates of the at least one unused lookup table based on the layout result so as to repair retention time violation of the connection path. Therefore, the retention time violation of the connection path can be quickly repaired by adding the unused lookup table of the FPGA in the layout stage.