247 results about "Path delay" patented technology

The invention discloses an industrial equipment communication method and system based on the industrial internet, and the method comprises the following steps: S1, collecting the multi-modal data of industrial equipment, and generating a preliminary multi-modal fusion feature; s2, performing event-driven analysis on the preliminary multi-modal fusion features to generate event sensing data; s3, constructing a semantic-driven communication protocol, and generating a semantic data queue with a priority identifier; s4, compressing the semantic data queue and carrying out time consistency calibration; s5, optimizing a communication frequency and bandwidth resource allocation strategy in combination with a mixed firefly optimization algorithm and a dynamic differential evolution algorithm; s6, constructing an industrial equipment communication topology model, and predicting path delay and bandwidth occupation indexes of the communication network in combination with the space-time multi-task network; and S7, constructing a zero-sum game model to analyze the potential confrontation relationship in the communication process, and outputting a secure communication scheme. According to the invention, semantic-driven communication, a hybrid optimization algorithm and the like are adopted, and intelligent communication of industrial equipment is realized.

The invention provides a time division duplex multi-carrier synchronous transmission method based on 5G, which is used for solving the problems of inflexible carrier time slot allocation and inaccurate time delay compensation in synchronous transmission. By dynamically adjusting time slot allocation and working frequency bands of carriers in a network control center, the method optimizes network loads and reduces cross interference; the time delay of each carrier is compensated in real time by adopting a synchronous signal calibration algorithm, so that strict alignment of transmission time slots is ensured; the transmitting end dynamically adjusts the transmitting power according to link state information, and the receiving end reduces interference and signal attenuation through a multi-carrier cooperative interference management and multi-path delay compensation mechanism; and a receiving end performs joint decoding based on channel estimation and integrates demodulation signals of all carriers, so that the transmission efficiency and the signal quality of the 5G network are improved. The method is suitable for a base station system and a base station and repeater extension coverage system, and is especially suitable for a distributed wireless system including an optical fiber remote distributed system, a cable remote frequency shift repeater system and the like.

The invention discloses an early-stage process corner time sequence prediction method based on deep learning, an electronic device and a storage medium, and aims to capture an interaction relationship between units in a path, an early-stage time sequence prediction process is established based on a bidirectional long-short-term memory network. The time sequence and the physical information of each level of unit in the path are represented as a sequence, and the information in the sequence is transmitted and represented through the BLSTM to learn the mutual influence between the units in the path, so that the path delay after layout is accurately predicted. On the basis, the influence of the global feature of the path on the path time sequence after layout is learned by using the multi-layer perceptron network, so that the prediction precision is improved, and meanwhile, an early time sequence prediction framework is adapted to a scene of various process corners. Based on the prediction result, the iteration of the design is reduced, and the time cost of the chip design is reduced.

The embodiment of the invention provides a clock domain crossing path checking method and device and a related device.The method comprises the steps that a clock domain crossing path set designed by a chip is obtained, and each clock domain crossing path in the clock domain crossing path set comprises a source clock domain and a target clock domain which are different in clock domain; the source clock domain and the target clock domain of each cross-clock-domain path are subjected to clock domain constraint, equivalent synchronous time sequence paths are obtained, and the source clock domain and the target clock domain of each equivalent synchronous time sequence path are from the same clock domain under the clock domain constraint; performing time sequence analysis on the equivalent synchronous time sequence path to obtain path delay information; and checking the corresponding cross-clock-domain path based on the path delay information of the equivalent synchronous time sequence path to obtain a check result of the cross-clock-domain path. According to the technical scheme provided by the embodiment of the invention, the path comprehensiveness and completeness when the time sequence analysis is carried out on the clock domain crossing path can be improved, and the time sequence analysis accuracy of the clock domain crossing path is improved.

The invention relates to the technical field of chip design, and provides a critical path screening method based on a chip time sequence report, which comprises the following steps: collecting chip time sequence report data, screening out first N critical paths from the data based on time sequence index data, and establishing a path ID-delay type-scene three-dimensional data model; and calculating the delay ratio of the unit delay to the interconnection line delay in each critical path. Performing single-type delay, type relevance and RC condition influence comparison on different scenes to obtain delay characteristic data. The invention discloses a system for executing the method, which can avoid full data redundancy and improve the analysis efficiency by screening the first N critical paths. And the delay change rule in different scenes is quantified. The delay characteristic data reflects the actual influence of the key path delay on the time sequence, so that a designer can quickly position the delay bottleneck of the key path, and a basis and a reference are provided for the targeted optimization of the total delay of the chip in the later period.

The invention relates to a terminal device communication transmission method and device based on a single-soldier ad hoc network and a medium. Reliability is improved through a dynamic dual-mode compensation mechanism. The method specifically comprises the following steps: a terminal establishes a main communication mode (including an initial routing and transmission protocol) based on dynamic topology, and establishes a complementary auxiliary communication mode (different routing strategies or protocols but consistent capacities); dual modes are bound into a redundancy group, state differences are monitored in real time, and untransmitted data packets / path delays are associated with dynamic identification bits; performing compensation transmission on difference data pointed by the identification bit through an auxiliary mode, and clearing the identification bit after the compensation transmission is completed; and if the redundant group has no residual identification bit, terminating the main mode and switching the auxiliary mode to dominate transmission. The network state and the compensation requirement are accurately associated through the dynamic identification bit, self-adaptive compensation of difference data is achieved, waste of redundant resources is avoided, and meanwhile the end-to-end communication success rate in the high dynamic environment is ensured through the dual-mode complementary characteristic.

The invention discloses a dual-path time delay difference PUF circuit, which comprises two time delay modules, two arbiters, a first exclusive-OR gate, n-1 time delay arbitration modules and an exclusive-OR gate array, each time delay module comprises n switch unit arrays, each switch unit array comprises m switch units, n is an integer greater than or equal to 1, n is an integer greater than or equal to 1, and n is an integer greater than or equal to 1. Each time delay arbitration module comprises two arbiters and an exclusive-OR gate, the exclusive-OR gate array comprises n-1 exclusive-OR gates, each time delay module is divided into n switch unit arrays, and the two time delay modules are divided into n switch unit array combinations, inserting a time delay arbitration module between every two adjacent switch unit array combinations to extract an intermediate response, then performing XOR processing on the intermediate response through an XOR logic gate array to obtain a response, and then performing XOR processing on the response and responses output by two arbiters again through a first XOR gate to obtain a final response; the method has the advantages of high machine learning attack resistance and low hardware overhead.

The invention discloses a combinational logic clustering optimization method and system based on reinforcement learning. The method comprises the following steps: S1, counting fan-out information of registers and combinational logic units in a circuit netlist; s2, according to the fan-out information, screening out registers and combinational logic units of which the fan-out quantity is greater than a first preset threshold and the worst time sequence path time sequence violation value of the output signal is smaller than a second preset threshold, and generating a target unit list; s3, acquiring fan-out combinational logic information of each unit in the target unit list; s4, on the basis of the fan-out combinatorial logic information, clustering operation is carried out on fan-out logic units on the basis of a reinforcement learning algorithm; s5, after logic clustering is completed, revising the netlist of the circuit; after the revision is completed, carrying out equivalence check; and S6, rearranging and wiring the circuit according to the modified netlist. The method can effectively reduce key path delay, optimizes circuit performance, and is especially suitable for large-scale integrated circuit design.

Methods and systems are directed to protect a target logic circuit against optical probing attacks and conceal a logic state in the target logic circuit. The method comprises designing a concealing logic circuit. The concealing logic circuit can be coupled to complement of input signals of the target logic circuit, inserted as neighbor logic circuit of the target logic circuit, and placed in close optical proximity to the target logic circuit. The concealing logic circuit can operate in the opposite operation mode or logic state of the target logic circuit in response to the complement of the input signals to the target logic circuit. The method can further comprise designing an evaluation circuit that generates the complement of the input signals and minimizes a path delay between the target logic circuit input and the concealing logic circuit input.

The invention discloses a rapid automatic time sequence ECO method and system based on graph interpretability. The rapid automatic time sequence ECO method based on graph interpretability comprises the steps that topological features and electrical features are extracted from a design file, a process library and a time sequence report of a circuit, and a path delay predictor based on a graph neural network is built; forward propagation is carried out on a given key path based on a path delay predictor to predict delay; obtaining the importance of each node, edge and feature on the key path based on a graph interpretability method; and according to importance, an appropriate ECO action is automatically selected for iteration. The method aims at solving the problems that in an existing electronic design automation (EDA) process, when time sequence analysis and optimization are conducted on a complex integrated circuit path, the accuracy of path delay prediction is insufficient, an explanatory analysis tool is lacked, and the efficiency of the ECO process is low.

The invention relates to a multiplier based on radix-4Booth coding and an improved Wallace compression tree, and the multiplier comprises a partial product generation module which recodes an input multiplier into a plurality of partial products through employing a Radix-4Booth algorithm, and forms a compact partial product array; the partial product compression module is used for quickly compressing the partial product through two compressors by utilizing an improved Wallace tree compression structure, and reducing the calculation path delay; and the final summation module is used for summing the compressed partial product by using a high-speed summator to obtain a final multiplication result. According to the invention, a radix-4Booth coding algorithm is adopted, so that a partial product array is regularly arranged, the circuit area is reduced, a new tree type compression structure in which a 3-2 compressor and a 4-2 compressor are mixed is adopted to realize a Wallace tree, the compression efficiency is improved, and the key delay is reduced.

The invention relates to the technical field of computer task scheduling, in particular to a server integration system based on edge computing, which comprises a topological path delay analysis module, a multi-dimensional priority mapping scheduling module, a cross-architecture performance conversion module, a dynamic priority rearrangement module and a task migration optimization module. According to the method, more dynamic and flexible task scheduling is realized by accurately analyzing communication delay and network topology characteristics between edge nodes and based on comprehensive evaluation of node performance and delay weight, the intelligent level of task allocation is improved, and the limitation of static load detection is effectively avoided; the adaptability of the system to inter-node communication delay and execution time offset is enhanced, a task migration strategy is optimized, reasonable allocation and efficient execution of tasks among heterogeneous nodes are ensured, performance waste caused by improper resource scheduling is reduced, the utilization rate of resources and the overall performance of the system are improved, and the service life of the system is prolonged. And the dynamic response capability of task scheduling in the edge computing environment is enhanced.

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

The invention discloses a critical path delay optimization method and system based on logic depth driving graph division. The method comprises the following steps: 1) obtaining a logic netlist of an integrated circuit; 2) constructing a critical path logic cone based on the logic netlist; 3) screening out a sub-circuit with an optimization value from the logic cone through a logic depth driving graph division method; 4) simplifying the sub-circuit with the optimization value through a sub-graph logic reconstruction method to obtain a reconstruction logic unit with better time delay; 5) screening the reconstruction logic units corresponding to the sub-graphs of which the reuse rates are greater than a preset value, and replacing the reconstruction logic units into the initial logic netlist to obtain an optimized logic netlist; 6) carrying out equivalence test on the initial logic netlist and the optimized logic netlist, and 7) carrying out delay evaluation on the logic netlist passing the equivalence test, and if the evaluation is passed, obtaining a final reconstruction logic unit and logic netlist. The method has the advantages of low cost, effective reduction of key path delay and the like.

The invention relates to the technical field of wireless communication, and provides a short code RM coding method and device based on a multipath channel, a medium and a program product, in the method, RM coding redundancy bits are increased in groups to resist deviation of a related maximum value and an ideal position caused by symbol offset brought by other secondary path delays; meanwhile, as the spread spectrum can expand the signal on a relatively wider frequency band and can reduce the propagation problem caused by multipath and attenuation, the spread spectrum processing is carried out on the data after the RM redundant coding is carried out, so that the sent information has very strong anti-multipath capability, and the performance of RM coding and decoding in a multipath environment is greatly improved.

The invention relates to a method for operating a transceiver device (1), comprising the following steps to be performed by the transceiver device (1): transmitting a pulse radio signal (5) at a given time; receiving a reflected signal of the transmitted pulse radio signal (5); generating a channel impulse response that describes the reflected signal as a function of a path delay; determining a self-interference distance range of the path delay of the channel impulse response, wherein the reflected signal of the self-interference distance range describes a self-interference signal of the transceiver device (1); determining at least one target distance range of the path delay of the channel impulse response, wherein the reflected signal of the target distance range describes a signal of the target distance range;Determining a signal component of the target distance range signal correlated with the self-interference signal using an operator, wherein the operator maps the self-interference signal to the correlated signal component of the target distance range signal; determining a signal component of the signal uncorrelated with the self-interference signal by removing the signal component correlated with the self-interference signal using a correlation cancellation filter.

The invention provides a path verification method and device for avoiding a high-risk area in a low-orbit satellite network. The method comprises the following steps: determining path relay information and a detour delay threshold value corresponding to the path relay information; wherein the path relay information comprises a safe path for avoiding a high-risk area and a relay satellite node for path verification; carrying out Hash calculation on the packet sending timestamp, the path relay information and the corresponding detour delay threshold value, embedding the calculated Hash value into the data packet, and starting to transmit the data packet; and in a data packet transmission process, based on the relay satellite node and the destination node, according to the actual segment path delay truth value and the corresponding detour delay upper limit value, obtaining a path verification result. According to the method, path verification is carried out by selecting a small number of relay satellite nodes, verification does not need to be carried out by hop-by-hop satellite nodes, the calculation and communication overhead is greatly reduced, the method is also suitable for the high-dynamic satellite network, and the accuracy of path verification of the high-dynamic satellite network is effectively improved.

The invention relates to the technical field of network delay detection, in particular to an fgOTN-based power communication network delay detection method and device. The method comprises the following steps: firstly, establishing a power communication network model according to power communication equipment and a link relationship thereof, selecting any two nodes in a network as a transmitting end and a receiving end, and acquiring time delay of data during transmission at the two ends; secondly, acquiring all paths from a sending end to a receiving end under different flow conditions based on historical data, and acquiring average time delays of all the paths under different flows; meanwhile, historical data are analyzed according to the constructed delay detection model, and optimal path delays under different flows are obtained. And finally, acquiring a current flow state and time delay thereof in the power communication network, comparing the time delay with the average time delay function and the optimal time delay function, and judging whether the time delay is in a normal interval or not. And if the delay exceeds the interval, predicting the abnormal state of the network by calculating a high burst delay probability.

Provided is a communication method, comprising: a network device sending a plurality of signals to a terminal device, the terminal device reporting measurement information to the network device after measuring the plurality of signals, the measurement information comprising first path time delay information of at least one signal in the plurality of signals, or an identifier of a first signal, the first signal is the signal with the minimum first path time delay in the plurality of signals. Therefore, the network equipment can determine whether the LOS path exists between the terminal equipment and the network equipment or not based on the measurement information fed back by the terminal equipment, so that the network equipment can judge whether the communication performance with the terminal equipment should be enhanced by using the sensing information of the terminal equipment or not.

The invention provides a time synchronization method executed by slave equipment, and the method comprises the steps: receiving a time synchronization packet from master equipment, and obtaining the packet transmitting time of the master equipment and the packet receiving time of the slave equipment; calculating a clock offset value between the slave device and the master device based on the packet transmitting time of the master device, the packet receiving time of the slave device and the path delay calibration value, and correcting a local clock of the slave device; wherein the path time delay calibration value is related to the distance between the master device and the slave device. The method can correct the clock skew between the master device and the slave device in real time, and improves the time synchronization precision.

A method for detecting asymmetric path delay changes in a synchronisation network comprises: monitoring a first path delay and a second path delay over a first sample period and a second sample period, wherein the first path delay is a reported time taken for a first packet transmitted by a first node of the network to be received by a second node of the network, and the second path delay is a time taken for a second packet transmitted by the second node of the network to be received by the first node of the network; determining that a change in one or both of the first and second path delays between the first sample period and the second sample period exceeds a first threshold; and determining whether the change in one or both of the first and second path delays is an asymmetric path delay change.

In a non-volatile memory system of a memory controller connected to a number of memory dies in which the memory dies use an unmatched architecture for the data input path of the memory dies, the data signals and clock signals from the controller may not align properly when they reach the data latches of the memory die's receiver circuit. To account for possible mis-match, the controller can compensate by individually determining and introducing a corresponding one of multiple relative delay values to the clock signal path. Which delay parameter value is used for each die can be determined based on the power consumed by the memory die when data is transmitted using the different delay values.

The invention relates to the technical field of integrated circuits and provides a command address bus training method and training device. Through optimization design of test signals and overall optimization design of the training method, influences of factors such as device characteristics, path delay, wiring layout and signal quality are fully considered, comprehensive analysis of signal integrity and power supply integrity is considered, training accuracy and signal stability are improved, and the method is suitable for being used in a large-scale industrial production line. The method is beneficial to meeting the requirements of a high-performance memory in the aspects of state alignment and synchronization, supports higher data transmission rate and higher working frequency, and is beneficial to meeting the requirements of applications such as a data center, a high-performance server, an artificial intelligence infrastructure and the like on data transmission and high-speed interconnection.

The invention relates to the technical field of water conservancy project automation control, and discloses a self-adaptive coordinated regulation gate control method and system and a storage medium. The method comprises the following steps: acquiring gate node real-time instruction data and performing time synchronization calibration to generate an initial instruction sequence; instruction features are extracted and classified based on the sequence, and an instruction sorting list is obtained; when the emergency instruction proportion exceeds a threshold value, the emergency instruction is separated, an exclusive channel is distributed, an accelerated propagation path is generated, and an optimized transmission path is determined through path delay evaluation; selecting a path with the lowest delay from the optimized paths to perform emergency instruction distribution, and acquiring a feedback signal; verifying the feedback signal and recording a response speed index, and determining the adjusted transmission configuration based on the index; the configuration is utilized to synchronize and integrate the conventional instructions to the main propagation sequence to generate a complete regulation and control instruction set. According to the method, the multi-node instruction time sequence consistency and the emergency response capability are improved, the transmission conflict is reduced, and the cooperative regulation and control efficiency is improved.

The invention discloses a communication emergency roundabout route switching method and system and electronic equipment, and the method comprises the steps: obtaining each piece of communication network state data of a current communication path, and dividing the communication network state data into first-level data, second-level data and third-level data; for the hierarchy data corresponding to each hierarchy, determining a weighted total value corresponding to the hierarchy data, and calculating a comprehensive communication network state weight corresponding to the current communication path based on the weighted total value; determining a network state corresponding to the current communication path based on the comprehensive communication network state weight and a preset communication network health state threshold; when the network state is abnormal, determining an optimal roundabout path based on the path delay and the transmission quality of each available roundabout path; and generating a path switching scheme based on the optimal roundabout path to switch the current communication path to the optimal roundabout path. According to the scheme of the invention, the evaluation precision of the current network state and the response speed and precision of path switching are improved.

The invention discloses a near-field CSI distributed estimation method for broadband XL-MIMO, and the method comprises the steps: firstly, enabling a center LPU to estimate a path time delay parameter of a center sub-array channel, enabling other LPUs to rapidly extrapolate the path time delay parameters of other sub-array channels, and transmitting an estimation result to a CPU; then, based on near-field wave beam squint and parameter symmetry characteristics brought by a large array and a large bandwidth, the CPU fuses time delay parameters estimated by different sub-arrays, and decouples and independently estimates near-field channel parameters including angle, distance and range parameters; then, the CPU transmits the estimated near-field channel parameters back to the LPUs, and each LPU independently estimates the path gain of the sub-array channel; and finally, transmitting the estimated path gain to a CPU (Central Processing Unit) by the LPUs, and further reconstructing a full-dimensional broadband near-field channel. The problems that the CSI acquisition calculation complexity is too high and the reconstruction precision is low in a large-array and large-bandwidth scene are solved.

The invention provides a space-time synchronization method and device of an unmanned aerial vehicle group, a medium and equipment, and the method comprises the steps: obtaining the space information of a slave node, adjusting the position of the slave node to meet the position condition of a master node, and enabling the master node to transmit information to the slave node and receive the response information of the slave node, the method comprises the following steps: calculating clock skew and path delay in combination with sending information and response information, calibrating the time of a slave node according to the clock skew and the path delay, finally testing the synchronization precision of a master node and the slave node by adopting pulses, determining synchronization completion when the precision requirement is met, and performing time-space synchronization calibration by utilizing each unmanned aerial vehicle in an unmanned aerial vehicle group so as to improve the operation precision of the unmanned aerial vehicle group. Therefore, the consistency and robustness of cooperative operation of the unmanned aerial vehicle group are improved.

The invention discloses a multi-service edge network cache optimization method based on delayed hit, which belongs to the field of edge computing and online caching, and comprises the following steps: deciding an optimal request processing path by analyzing a local cache hit state, adjacent server cache distribution and relay path delay in real time; detecting the remaining time window of the current file acquisition operation, and dynamically evaluating the cost of waiting for a delay hit or triggering a new operation; selecting a target server based on weight sorting, dynamically eliminating low-weight files, and reducing cache conflicts in combination with a cross-server redundancy elimination mechanism; when the local cache and the relay path do not meet the delay constraint, dynamically evaluating the cloud response time and bandwidth cost of the bypassing operation, and determining the feasibility of the bypassing operation; the file weight is dynamically calculated based on historical request characteristics and operation delay, the file replacement cost is quantified by combining the cache state and the residual capacity of the server, and the average retrieval delay of user requests can be greatly reduced.

The invention relates to the technical field of pulse neural network computing hardware, in particular to a neural network computing circuit of a pulse self-attention mechanism. According to the method, invalid or inefficient pulse events are dynamically screened through the hardware mask module, the operation number is remarkably reduced, and calculation path delay and logic resource occupation are reduced; meanwhile, in order to adapt to novel networks with binary architecture such as QKFormer, calculation and storage of a V matrix are eliminated, and storage resources and calculation resources are further reduced; in addition, the event coding module only generates active neuron events, and input sparsity is achieved. A configurable IF neuron model is adopted, exponential operation is avoided, hardware implementation is facilitated, and the method is suitable for binary network deployment. The modular architecture can support function extension, assembly line and parallel work; and the parallelism degree of the design can be determined according to the actual data pulse distribution rate. Event driving and mask pruning are combined, so that the overall computing resources of the circuit are greatly reduced, and the power consumption is reduced.

The invention relates to a low-orbit satellite constellation system frequency hopping synchronization method, and belongs to the field of satellite communication. Calculating a relative distance delta L between the satellite and the terminal based on the satellite ephemeris; calculating path time delay delta T according to the relative distance delta L; calculating the relative speed delta V of the satellite and the terminal based on the satellite ephemeris; doppler frequency fd is calculated according to the relative speed delta V; based on the satellite ephemeris, calculating the relative acceleration delta alpha of the satellite and the terminal; calculating a Doppler change rate alpha f according to the relative acceleration delta alpha; based on the uplink synchronous detection signal, a time error estimation value delta T'is calculated by adopting a late early gate algorithm; calculating a frequency offset error estimation value delta fd by adopting an FFT-based frequency estimation algorithm; calculating time compensation Tsat'of the satellite and the terminal; calculating frequency compensation f'up of the satellite and the terminal; according to the invention, satellite-ground rapid time-frequency coarse synchronization under a low-orbit satellite system is realized, and satellite-ground time-frequency fine synchronization is realized by further estimating the time-frequency difference of uplink synchronous detection signals of a terminal through a satellite and feeding back terminal compensation.