77 results about "Path delay" patented technology

The invention relates to the technical field of computer task scheduling, in particular to a server integration system based on edge computing, which comprises a topological path delay analysis module, a multi-dimensional priority mapping scheduling module, a cross-architecture performance conversion module, a dynamic priority rearrangement module and a task migration optimization module. According to the method, more dynamic and flexible task scheduling is realized by accurately analyzing communication delay and network topology characteristics between edge nodes and based on comprehensive evaluation of node performance and delay weight, the intelligent level of task allocation is improved, and the limitation of static load detection is effectively avoided; the adaptability of the system to inter-node communication delay and execution time offset is enhanced, a task migration strategy is optimized, reasonable allocation and efficient execution of tasks among heterogeneous nodes are ensured, performance waste caused by improper resource scheduling is reduced, the utilization rate of resources and the overall performance of the system are improved, and the service life of the system is prolonged. And the dynamic response capability of task scheduling in the edge computing environment is enhanced.

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

The invention relates to the technical field of water conservancy project automation control, and discloses a self-adaptive coordinated regulation gate control method and system and a storage medium. The method comprises the following steps: acquiring gate node real-time instruction data and performing time synchronization calibration to generate an initial instruction sequence; instruction features are extracted and classified based on the sequence, and an instruction sorting list is obtained; when the emergency instruction proportion exceeds a threshold value, the emergency instruction is separated, an exclusive channel is distributed, an accelerated propagation path is generated, and an optimized transmission path is determined through path delay evaluation; selecting a path with the lowest delay from the optimized paths to perform emergency instruction distribution, and acquiring a feedback signal; verifying the feedback signal and recording a response speed index, and determining the adjusted transmission configuration based on the index; the configuration is utilized to synchronize and integrate the conventional instructions to the main propagation sequence to generate a complete regulation and control instruction set. According to the method, the multi-node instruction time sequence consistency and the emergency response capability are improved, the transmission conflict is reduced, and the cooperative regulation and control efficiency is improved.

The invention relates to the technical field of pulse neural network computing hardware, in particular to a neural network computing circuit of a pulse self-attention mechanism. According to the method, invalid or inefficient pulse events are dynamically screened through the hardware mask module, the operation number is remarkably reduced, and calculation path delay and logic resource occupation are reduced; meanwhile, in order to adapt to novel networks with binary architecture such as QKFormer, calculation and storage of a V matrix are eliminated, and storage resources and calculation resources are further reduced; in addition, the event coding module only generates active neuron events, and input sparsity is achieved. A configurable IF neuron model is adopted, exponential operation is avoided, hardware implementation is facilitated, and the method is suitable for binary network deployment. The modular architecture can support function extension, assembly line and parallel work; and the parallelism degree of the design can be determined according to the actual data pulse distribution rate. Event driving and mask pruning are combined, so that the overall computing resources of the circuit are greatly reduced, and the power consumption is reduced.

A congestion control method and apparatus, a device, a storage medium, and a program product. The method comprises: acquiring a response delay corresponding to a terminal device, wherein the response delay is a duration between an update moment of a pointer to be acknowledged and the current moment, and said pointer refers to the sequence number of a first byte that has been sent by the terminal device but for which an acknowledgment message has not yet been received; acquiring a path delay of each virtual link among a plurality of virtual links corresponding to the terminal device, wherein the path delay is determined on the basis of transmission round-trip durations corresponding to a plurality of data packets on the virtual link; and adjusting a congestion window of the terminal device on the basis of the response delay, and on the basis of the path delay of each virtual link, performing load balancing processing on a plurality of physical links corresponding to the plurality of virtual links, wherein the congestion window is used for indicating the maximum data volume the terminal device may consecutively send. The congestion control method can reduce network congestion and improve the load balancing effect of physical links.

Techniques are disclosed for computing a cost of an advertised route to a next-hop network device along a path to a destination based at least in part on a preference for the path. In one example, a computing system computes a cost of a route to a next-hop network device along a path to a destination. The computed cost is based at least in part on (1) a metric for the route and (2) a preconfigured preference for the path. In some examples, the preference for the path is based at least in part on (a) a type of the path as compared to other types of other paths to the destination or (b) a latency of the path as compared to other latencies of the other paths. The computing system sends a route advertisement for the route that includes data indicative of the cost of the route.

The invention provides a message flow control method, system and device and a readable storage medium. The method comprises the following steps: carrying out fragmentation processing on an input message according to a preset fragmentation size, and generating a plurality of message fragments cached in a fragmentation FIFO (First In First Out); performing length accumulation on each message fragment, wherein an accumulated value is associated with an actual length of the message fragment and a message length variation caused by encryption and decryption or message editing processing; and when the accumulated value reaches a preset boundary value, resetting the accumulated value and enabling the flow control value to execute self-adding operation. Compared with the prior art, the method has the advantages that the flow control design universality is high, the method can adapt to message length changes in scenes such as encryption, decryption or message editing, and accurate and synchronous flow control value operation is ensured; secondly, the depth of the recombined FIFO is only related to the delay of the main path and does not change along with the increase of the number of ports, so that the chip area and the power consumption are reduced; in addition, the flow control is triggered by the accumulated length boundary, and the resource efficiency and the system reliability are improved.

A radar device includes a transmitter and receiver circuit and an estimation circuit. The transmitter and receiver circuit is configured to generate a second signal according to a first signal. The estimation circuit is coupled to the transmitter and receiver circuit and is configured to generate an estimated path delay according to the second signal for a back-end circuit to execute a related application.

This invention relates to the field of satellite communication technology, specifically to a dynamic routing method for large-scale low-Earth orbit (LEO) satellites that adapts to network queuing delay. Based on a greedy heuristic approach for dynamic routing in large-scale LEO satellite networks, it utilizes parameters such as satellite communication distance and direction, the estimated minimum number of hops from the current satellite to the receiving location, the average queuing delay in the network, and the queuing delay of the next-hop relay satellite. A value function is proposed to find the next-hop satellite, where the function value reflects the distance traveled to the receiving location in a single-hop transmission and the magnitude of the relay satellite's queuing delay. By plotting the change curves of the weights corresponding to the shortest transmission path delay versus the average satellite queuing delay, the optimal weights are found as the average queuing delay changes, thus achieving adaptive network load conditions. Verification shows that, compared to other routing methods that allow non-adjacent satellites to use ISL communication, this invention has the advantage of shorter total delay for networks with different on-board queue load conditions.

Embodiments of the present application provide a time delay measurement circuit, method, chip and electronic device. The time delay measurement circuit is applied to a chip. The time delay measurement circuit comprises a measurement circuit, a copy circuit and a crosstalk circuit. The chip further comprises a timing circuit. The copy circuit is a copy of the timing circuit. The measurement circuit is connected to the copy circuit. The copy circuit is further connected to the crosstalk circuit. The copy circuit is used to simulate a data signal in the timing circuit. The crosstalk circuit is used to generate a crosstalk signal. The crosstalk signal is used to interfere with the data signal. The measurement circuit is used to measure a path delay of the copy circuit interfered by the crosstalk signal. The path delay of the copy circuit is used to predict a time delay or a frequency of the chip. The accuracy of predicting the time delay or the frequency of the chip is improved.

The application relates to the technical field of chip design, and particularly discloses a routing method and system based on timing criticality, which abstracts physical layout into a node network, constructs a weighted cost function of total wiring length and critical path length, adopts a minimum spanning tree algorithm to iteratively expand a path and record a parasitic parameter, calculates a merging cost value based on the product of the length of a coincident path and the timing criticality of a node, generates a virtual node by merging a node pair with the maximum benefit, and cyclically optimizes until a convergence condition is met, so that the dual objectives of wiring resource optimization and timing critical path delay reduction are achieved. The method is based on a more accurate time delay model, defines a target function which comprehensively considers the overall routing cost and the routing cost of a timing critical load node, makes timing analysis more accurate, reduces the signal delay and the size of a clock cycle of a load node according to the criticality of the load node, and effectively increases the running speed of a chip.

The application discloses a kind of multi-modal wearable sensor data fusion-oriented timing synchronization method, system, terminal and storage medium, the method includes: obtaining absolute timestamp as global clock source;Global clock source is as the master clock of precision time protocol, a plurality of wearable sensors are configured as slave clock, through precision time protocol, multiple rounds of message interaction are performed between master clock and slave clock, and the timestamp corresponding to each round of interaction is obtained;According to the corresponding timestamp, the current path delay and the current clock offset are calculated, and according to the preset path delay threshold and clock offset threshold, the current path delay and the current clock offset are iteratively judged, whether the local clock is corrected according to the current clock offset is determined according to the iterative judgment result, until slave clock and global clock source achieve timing synchronization;After achieving time synchronization, the periodic data sampling tasks of a plurality of wearable sensors are phase-aligned.The application significantly improves timing synchronization accuracy.

The application discloses a method and system suitable for segment delay measurement of an audio decoder, comprising the following steps: writing periodic waveform data with a preset size into a DAC unit in response to a first excitation signal, and carrying out digital-to-analog conversion on the periodic waveform data through the DAC unit; inputting an audio signal obtained through the digital-to-analog conversion into an ADC unit through an audio line, and carrying out analog-to-digital conversion on the audio signal through the ADC unit; transmitting data obtained through the analog-to-digital conversion to the DAC unit, so as to enter the next cycle of digital-to-analog conversion; determining at least two of a first time, a second time, a third time and a fourth time; and determining at least one of a first complete path delay, a DAC delay, a decoding software delay and an ADC delay according to the at least two of the first time, the second time, the third time and the fourth time. The application can measure the segment delay of audio decoding.

The invention discloses an FPGA (Field Programmable Gate Array) signal negotiation distribution method supporting dynamic networking. The method comprises the following steps: establishing a mapping relationship between FPGA nodes and logic nodes; calculating the shortest path between all FPGA pairs, counting the number of networks on each physical channel, and calculating an initial TDM ratio and path delay; introducing a relaxation ratio and a criticality ranking mechanism, performing iterative wiring optimization based on a dynamic cost function, and updating a weight topological graph; physical channels with TDM ratio overrun and serious congestion are identified, physical topology is reconstructed through channel addition, deletion and transfer operations, and channel resource allocation is guided based on comprehensive ranking scores of three types of constraint factors; according to the method, the PathFinder wiring and the topology reconstruction process are cooperatively executed, signal distribution is carried out again based on the wiring result of the last round after topology adjustment each time, a final wiring path and a reconstructed topology structure are output, the maximum path delay is reduced, and the wiring quality of a large-scale FPGA system is improved.

The invention relates to the field of flash memory storage control, in particular to a delay monitoring device based on streaming timestamp sampling. Comprising a timestamp acquisition module which is arranged in the SSD controller and is used for acquiring a timestamp on an IO path; the delay calculation and classification module is used for calculating the collected timestamps to obtain sub-path delays; the streaming statistical unit is used for calculating average delay, maximum delay and minimum delay in real time and supporting generation of delay distribution percentile data; and the threshold value alarm and PMU linkage module is used for configuring a delay threshold value by firmware, triggering the threshold value alarm and PMU linkage module when the I / O delay exceeds the threshold value, giving an alarm and storing execution snapshots of N instructions before and after the abnormal I / O. On the premise that the area and the power consumption of the SSD controller are not obviously increased, delay monitoring with the precision of ten nanoseconds is achieved. The influence of the device on the IOPS performance is lower than 1%, and high-reliability delay diagnosis and QoS guarantee can be provided in a data center scene.

The application relates to a multiplier based on radix-4 Booth coding and an improved Wallace compression tree, comprising a partial product generation module: input multipliers are re-encoded into a plurality of partial products by adopting a radix-4 Booth algorithm to form a compact partial product array; a partial product compression module: by utilizing an improved Wallace tree compression structure, the partial products are quickly compressed by two compressors to reduce the calculation path delay; and a final summation module: the compressed partial products are summed by using a high-speed adder to obtain a final multiplication result. The radix-4 Booth coding algorithm is adopted to make the partial product array arrangement regular, the circuit area is reduced, a new tree compression structure in which 3-2 compressors and 4-2 compressors are mixed is adopted to realize the Wallace tree, the compression efficiency is improved, and the key delay is reduced.

A method and system for accurately calculating path delay is disclosed. After establishing time synchronization between the master and slave network elements at both ends of the path, the method uses the delay error and the stamping scheme identifier sent by the master network element to obtain the delay error. The slave network element queries a pre-set delay error table based on the delay error and the stamping scheme identifier of the master network element to obtain the corresponding delay error sum. The delay error sum is the sum of the delay error sum within the master network element and the delay error sum within the slave network element. The slave network element uses the delay error sum to correct the measured path delay obtained through the time synchronization protocol to obtain the true path delay. This effectively eliminates the end-to-end internal processing delay introduced by the hardware stamping position being far from the physical layer boundary, significantly improving the measurement accuracy of path delay.

The invention relates to the technical field of communication, discloses an electromagnetic spectrum abnormal signal monitoring method and system based on double acquisition and comparison, and aims to solve the problems of asynchronous double-channel sampling and high abnormal signal omission ratio and false alarm rate caused by clock drift and physical path delay in the prior art. According to the method, a hardware-level self-adaptive clock synchronization compensation circuit is constructed, clock path delay is quantized and offset in real time before analog-to-digital conversion, and a first sampling clock and a second sampling clock which are accurately synchronized are generated; a dual-channel ADC is used for synchronously collecting the same radio frequency signal, and abnormal signals are judged and identified through spectrum coherence analysis and differential spectrum threshold. The system comprises a main clock unit, a self-adaptive synchronous compensation circuit, a dual-channel ADC module and a data processing comparison module. The picosecond-level synchronization precision is achieved, external time service is not needed, the missing detection and false alarm rate is remarkably reduced, and the method is suitable for high-reliability frequency spectrum monitoring in the complex electromagnetic environment.

Provided herein are various enhancements for skew balancing in semiconductor circuits, such as during the synthesis, timing, routing, and phases of circuit design. In one example implementation, a method includes simulating a circuit to determine initial path delay values for a set of paths in the circuit, and determining a reference value for the set of paths based on the initial path delay values. The method also includes generating constraints using the reference value and a skew target for the set of paths, and performing a timing analysis to redesign the circuit using the constraints.

The application provides a time comparison method and device, electronic equipment and storage medium, and relates to the technical field of satellite navigation and timing. The method comprises the following steps: extracting the observation value of the total delay of the oblique path of the RDSS signal by using the fixed elevation penetration path of the RDSS signal; decomposing the theoretical value of the total delay of the oblique path of the RDSS signal into a zenith delay variable and a horizontal gradient variable; minimizing the difference between the theoretical value and each observation value to obtain the optimal solution of the tropospheric vertical path delay in the zenith direction and the optimal solution of the horizontal gradient vector, and constructing the target constraint function of the tropospheric delay in the double-difference carrier phase observation equation of the RNSS signal; calculating the estimated value of the double-difference phase ambiguity based on the double-difference carrier phase observation equation and the target constraint function, and calculating the time bias based on the estimated value of the double-difference phase ambiguity. The application can not only maintain the high precision close to the TWSTFT method, but also has the advantages of low cost and high availability of the GNSS PPP method.

The invention discloses an intelligent controller resource dynamic allocation method and system based on software defined hardware, and relates to the technical field of resource allocation, and the method comprises the steps: calculating the comprehensive distance cost based on the geometric center coordinate and threading number between any two reconfigurable islands in an FPGA; generating an optimal island allocation scheme of a control link in the FPGA based on the threading number and the comprehensive distance cost; calculating the link path delay of the control link based on the fixed delay of the segmentation line and the optimal island allocation scheme; calculating a second update value of the discrete integrator in the FPGA based on the update event of the segmentation line; a delay difference is calculated based on the link path delay and a base path delay of the control link. According to the invention, the execution efficiency of the system is improved, and the resource consumption is optimized in the dynamic configuration environment.

This invention discloses a clock synchronization control method and system for an optical communication sub-control board, relating to the field of clock synchronization technology. The method includes: acquiring and recovering a clock signal and detecting the current locking mode; determining the processing delay mode corresponding to the transmission path within the sub-control board based on the current locking mode, and calculating the corresponding path delay factor based on the processing delay mode; constructing a mapping model between the processing delay mode and the phase drift amplitude of the recovered clock based on the path delay factor and the phase measurement value of the recovered clock signal; determining the link transmission delay of the sub-control board in the current locking mode based on the mapping model, and outputting a synchronized clock after delay compensation of the phase drift amplitude of the recovered clock based on the link transmission delay. This invention achieves clock synchronization control based on the evolution of the board's internal processing state, which helps reduce timing deviations caused by state switching.

A hardware reset method, a configuration method for hardware reset, an electronic device and a storage medium. The hardware reset method comprises: converting a plurality of reset events for a plurality of hardware abstractions into a plurality of interrupt events; determining, by a micro control unit, a target hardware abstraction corresponding to a target interrupt event in the plurality of interrupt events and a reset timing of the target interrupt event; and triggering a reset operation corresponding to the target hardware abstraction based on the target hardware abstraction corresponding to the target interrupt event and the reset timing of the target interrupt event. The hardware reset method can modify the reset timing of the target interrupt event by updating the micro control unit after chip tape-out is completed, thereby improving the reliability and flexibility of hardware reset. Since the control path delay of the micro control unit to other hardware abstractions is small, the real-time performance when controlling complex reset timing is improved.

The invention discloses a radar device and an estimation method. The radar device comprises a transmitting and receiving circuit and an estimation circuit. The transmitting and receiving circuit is used for generating a second signal according to a first signal. The estimation circuit is coupled to the transmitting and receiving circuit and is used for generating an estimated path delay according to the second signal and generating an estimated phase interference according to the estimated path delay for a back-end circuit to execute a related application.

The application discloses a fault positioning method and system of an integrated circuit, and belongs to the technical field of integrated circuit testing and fault diagnosis. The method comprises the following steps: obtaining an initial circuit dependency mapping relationship from an integrated circuit design database, generating a potential fault propagation sequence set, and determining the matching accuracy of each sequence starting node; acquiring a preliminary fault source set by using the frequency characteristics, amplitude range and abnormal trigger time window of an abnormal signal; refining the fault source list according to the downstream abnormal count, abnormal propagation level depth and influence range boundary to calculate the influence strength value; generating a fault propagation influence chain in combination with the node influence weight; simulating the propagation path by using a depth-first search to verify the circuit stability by matching the abnormal trigger time window; and finally updating the path delay and topological structure to realize closed-loop iteration optimization. The scheme can accurately distinguish the initial fault source and the secondary propagation effect, model the dynamic dependency relationship between nodes and the signal propagation timing constraint, and improve the fault positioning precision.

This application discloses a time synchronization method and electronic device, relating to the field of time synchronization technology. The method includes: determining whether the synchronization state of a first device and a second device has changed based on a first difference between a second time and a first time and / or a second difference between a third time and a fourth time; when the synchronization state changes, determining a first phase change value and a second phase change value of the second device; determining whether a transmission link between the first device and the second device has switched based on the first and second phase change values; and calculating a first path delay between the first device and the second device after determining that a transmission link switch has occurred. This process recalculates the first path delay when a switch in the transmission link between the first device and the second device is detected, avoiding large path delay errors caused by link switching and improving the accuracy of time synchronization.

The present application provides a communication method and an apparatus, which are applied to the technical field of communications. The communication method comprises: within a first time period, a first apparatus sends a plurality of first measurement packets to a second apparatus by means of a PON apparatus; upon receiving the plurality of first measurement packets, the second apparatus sends a plurality of corresponding second measurement packets to the first apparatus by means of the PON apparatus, and the first apparatus receives the plurality of second measurement packets from the second apparatus by means of the PON apparatus; the first apparatus determines a plurality of loopback path delays on the basis of the plurality of first measurement packets and the plurality of second measurement packets; and the first apparatus performs data transmission with the second apparatus on the basis of a downlink unidirectional delay and / or an uplink unidirectional delay, wherein the downlink unidirectional delay and / or the uplink unidirectional delay are obtained on the basis of the plurality of loopback path delays. The method can eliminate the requirements of the PON apparatus for clock synchronization in PON communication.

An FPGA is disclosed, which includes a first delay line section to which an input pulse having the time difference between the occurrence of a start signal and an end signal as its width is input, a code conversion section that converts the order of the elements of a thermometer code output by the first delay line section and outputs it, and a calculation section that uses the converted code output by the code conversion section to determine the occurrence time difference, wherein the converted code is obtained by arranging the order of the elements of the thermometer code according to a predetermined standard, and the predetermined standard is the data path delay from the output node of the input pulse to the output node of each of the plurality of flip-flops included in the first delay line section.

The application discloses a kind of satellite network transmission protocol timer adaptive adjustment method.For the problem that ACK feedback is extremely sparse in satellite network, leading to the difficulty of end-to-end delay estimation and timely convergence, the application obtains the delay cycle table of transmission path between any source-destination node pair based on the periodic topology link planning of satellite network, and maintains it locally in each node.During the connection establishment and operation of the transmission protocol, the transmission path delay of the current time window is obtained by searching the table in real time, and this is used as a reference to configure the time class timing parameters of the satellite network transmission protocol, and it is adaptively reconfigured when the delay cycle switches.The application makes the timer parameters of the transmission protocol consistent with the actual link, eliminates false timeout judgment and redundant retransmission, and improves the link utilization efficiency and end-to-end transmission performance.

The invention relates to a data transmission circuit, a chip, a data transmission method, a medium and a program product. The data transmission circuit comprises a first-stage trigger used for outputting data to a second-stage trigger module under the control of a clock signal output by a clock source; the second-stage trigger module comprises N + 1 second triggers, the updating cycle of output data of each second trigger is the clock cycle of N + 1 clock sources, and the triggered clock cycles of the second triggers are different; n + 1 is a natural number greater than or equal to 1; the third-stage trigger module comprises a data selector and a third trigger which are connected, and the data selector is used for selecting one path of data from the multiple paths of data output by the second-stage trigger module in each clock period of the clock source and outputting the selected path of data to the third trigger; and the third trigger is used for outputting data output by the data selector. According to the data transmission circuit, the path length is reduced, so that the path delay is reduced.