1737results about "Digital circuit testing" patented technology

The invention relates to a probe suite multifunctional test method and system based on wafer test, and the method comprises the steps: obtaining the to-be-tested data of a wafer and the parameter information of a probe and a probe card; and through a preset intelligent algorithm, the contact state of the probe tip and the wafer is judged according to the working parameters, and the contact pressure and the probe impedance are dynamically adjusted. Meanwhile, environmental parameters including temperature, humidity and electromagnetic interference intensity in a test area are obtained, and when the environmental parameters exceed a preset range, the environment is automatically optimized. And detecting wafer characteristics based on the to-be-tested data, preprocessing the initial test data to obtain wafer test data, and performing real-time analysis and anomaly detection. And finally, according to an analysis detection result, whether the probe is adjusted or self-repaired is judged, and meanwhile, the test parameters and the working mode of the probe card are dynamically adjusted, so that high-precision and high-stability wafer test is realized, the performance of the probe and a test system is guaranteed, and the accuracy and the reliability of semiconductor test are improved.

A test and measurement instrument has a port to receive a signal from a device under test (DUT), one or more processors configured to execute code that causes the one or more processors to acquire a waveform from the signal, derive a pattern waveform from the waveform using one of either hardware or software clock recovery, perform linear fit pulse response (LFPR) extractions on the pattern waveform to extract more than one LFPR, determine a reference pulse response from the more than one LFPRs, compare at least one of the LFPRs to the reference pulse response to determine a difference, and tune the DUT to reduce the difference. The test and measurement instrument may also use the multiple LFPRs as an input to a machine learning network to perform measurement predictions for the DUT.

Systems and methods are disclosed that relate to applications and platforms for performing in-system testing for autonomous or semi-autonomous systems and applications. In some embodiments, resources of a computing system may be grouped into one or more subsets of system elements (e.g., “a chiplet”) and may be configured to be controlled via an associated local controller, which may enable and / or disable the chiplet as targeted. In embodiments, the local controllers may receive instructions from a central controller and, via the enabling and / or disabling of the chiplets, may maintain a number of resources consumed during system testing within a threshold. As a result, the system may be configured to perform system testing without additional resources and / or without redirecting resources that may be intended for other operations.

Power-gated domains are provided for design for test (DFT) and / or design for debug (DFX) logic units in a semiconductor chip. Power-gated domains allow power consumption to be reduced when DFT and DFD logic units are not in use. Power-gated domains can include reset features and output port power isolation.

In various examples, faults are detected based at least in part on result value(s) generated by hardware component(s) by performing one or more diagnostic tests in accordance with a diagnostic test pattern. The diagnostic test pattern may be used to perform an assessment of functionality of the hardware component(s) by causing the hardware component(s) to generate the result value(s), which may be used to identify one or more hardware faults (e.g., by comparing the result value(s) to expected value(s)).

A mixed-signal circuit may include an analog circuit and a digital circuit coupled to the analog circuit, wherein the analog circuit is configured to, in a normal operation mode, provide an analog signal to the digital circuit, and wherein the digital circuit is configured to, in the normal operation mode, provide a digital signal to the analog circuit, the mixed-signal circuit may further include a test signal generator configured to, during a test operation mode, receive the digital signal from the digital circuit, generate a test signal based on the digital signal, and provide the test signal to the digital circuit, wherein the test signal generator is configured to generate the test signal using an emulation of the analog circuit, and wherein the mixed-signal circuit is tested based on an output of the digital circuit that is generated in response to the test signal.

An electronic device for improving a performance of a signal chain is described. The signal chain includes multiple electronic components. The electronic device further includes a control circuit. The control circuit is configured to receive a set of figures of merit, wherein the set of figures of merit includes at least one component-specific figure of merit for several different settings of several of the electronic components, respectively. The control circuit is configured to determine and / or receive at least one n-th moment characteristic of a signal of the signal chain. The control circuit is configured to determine at least one performance parameter for a plurality of different combinations of settings of the electronic components, respectively, wherein the at least one performance parameter is indicative of a performance of the signal chain. The control circuit is configured to determine the at least one performance parameter based on the set of figures of merit and based on the at least one n-th moment characteristic. The control circuit is configured to select a combination of settings of the electronic components based on the performance parameters determined for different combinations of settings of the electronic components. Further, a configuration method of configuring a signal chain is described.

Fault detection circuits and methods. An example of a fault detection circuit includes a comparator configured to compare a voltage at a voltage terminal with a reference voltage, a digital logic circuit coupled to a test terminal and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the digital logic circuit including at least one digital logic gate, and an edge detection circuit configured to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal.

A system includes an input to receive a digital waveform signal, a memory, and one or more processors configured to execute code to cause the one or more processors to: generate a horizontal ramp sweep signal based on the digital waveform signal; receive a selection input to identify a segment of the digital waveform signal; gate the horizontal ramp sweep signal and the digital waveform signal based on the selection input to produce cyclic loop image data for the segment of the digital waveform; store the cyclic loop image data in the memory; and provide the cyclic loop image data as one or more inputs into a machine learning system. A method of waveform classification using a cyclic loop image includes receiving an input waveform, receiving a selection of a segment of the input waveform, transforming the segment of the input waveform into cyclic loop image data, the transforming comprising generating a horizontal ramp sweep signal based on edge transitions in the input waveform, and storing the cyclic loop image data in a memory; and sending the cyclic loop image data to a machine learning system to determine an attribute of the input waveform.

An error rate measurement apparatus includes a display control unit, an operation display unit, and a control unit. The display control unit displays a firsts coefficient value in a selectable manner by tabs of a number corresponding to a Full Swing value, performs matrix display on a display screen by using each one of combinations of each second coefficient value and each third coefficient value in the first coefficient value on the selected tab, and displays each coefficient value on the display screen in a three-dimensional bird-eye view by using each second coefficient value and each third coefficient value as a combination of a horizontal direction coordinate axis and a vertical direction coordinate axis and using the first coefficient value as a depth direction coordinate axis. The operation display unit selects a range including at least one cell as a scanning target in the matrix display or a bird-eye display.

A system comprises a plurality of regions, wherein ones of the plurality of regions are partitioned from others of the plurality of regions and at least one of the plurality of regions is a region under test. The system comprises at least one noise generator configured to generate noise in at least the region under test, and at least one noise monitor configured to monitor one or more effects of the noise generated in the region under test. The system comprises a test controller configured to: cause the at least one noise generator to generate the noise in at least the region under test; receive information from the at least one noise monitor indicative of the one or more effects of the noise generated in the region under test; and determine one or more conditions based on at least a portion of the received information.

Scan testing features on a chip may include a streaming scan network (SSN) with core streaming scan hubs (CSHs). A CSH may include a parent bus interface, a child bus interface, and a streaming scan hub (SSH). A CSH may also include multiplexing logic configured to select whether the child bus interface is included in the SSN or excluded from the SSN. Multiple CSHs may be interconnected in a hierarchical topology through the child bus interfaces.

An eye-diagram index analytic method includes: calculating a transfer function of multiple coupled lines; converting the transfer function into a pulse response; calculating an eye-diagram index according to the pulse response; and correcting the eye-diagram index according to peak distortion analysis.

Systems and methods for assessing display health in response to accidents are described. In some embodiments, an Information Handling System (IHS) may include an Embedded Controller (EC) and a memory coupled to the EC, where the memory comprises program instructions that, upon execution by the EC, cause the IHS to initiate an integrated display's Built-In-Self-Test (BIST) in response to a determination that the IHS suffered an accident.

This disclosure provides systems, methods, and devices for memory systems that support enhanced processing core scheduling schemes. In a first aspect, a system-on-a-chip (SoC) includes functional logic configured to perform one or more functions and self-testing logic configured to perform a self-testing operation on the functional logic. The SoC also includes a plurality of power domains, including a functional power domain coupled to the functional logic and configured to provide power to the functional logic and a self-testing power domain coupled to the self-testing logic and configured to provide power to the self-testing logic. The SoC further includes power control logic configured to control power delivery from the plurality of power domains to the functional logic and the self-testing logic and configured to power collapse the self-testing logic. Other aspects and features are also claimed and described.

The invention discloses test equipment, a test system, a test method and a test device.The test equipment provided by the invention is internally provided with an FPGA chip capable of controlling a target power supply for supplying power to a to-be-tested MCU, and in practical application, different test logic programs can be configured in the FPGA chip according to practical requirements, so that the test efficiency is improved; according to the technical scheme, the FPGA chip in the test equipment can generate the high-frequency clock signal, so that the time accuracy during voltage burr fault injection of the to-be-tested MCU can be ensured, and the test effect of the to-be-tested MCU can be further ensured.

A power vector analyzer to analyze power from a device under test (DUT) includes one or more channels to measure a reference voltage signal from a power line connected to the DUT, one or more channels to measure a reference current signal from the power line, a user interface comprising a display and one or more controls, and a quadrature synchronous detector (QSD) for each phase of apparent power being measured, the QSD configured to use a reference voltage signal from the one or more channels and a reference current signal from the one or more channels to determine the apparent power for each phase of power being measured by the DUT and display the apparent power for each phase on the display.

The embodiment of the invention provides a chip and electronic equipment, the chip comprises a plurality of chip ports, a port multiplexing logic module and a scanning test logic module, the port multiplexing logic module is provided with a plurality of groups of first ports and a plurality of groups of second ports, and the plurality of chip ports are divided into a plurality of groups according to preset granularity; each group of chip ports is connected to at least one of a plurality of groups of first ports and a plurality of groups of second ports of the port multiplexing logic module, and the plurality of groups of first ports or the plurality of groups of second ports of the port multiplexing logic module are connected to the scanning test logic module; and the port multiplexing logic module is used for controlling gating of a path between the chip port and the scanning test logic module by taking a preset granularity as a unit according to the control instruction. According to the embodiment of the invention, the problems of unreasonable I / O allocation and long test time of large-scale complex chips in related technologies can be solved, the degree of freedom of I / O allocation is improved by setting the granularity of I / O allocation, the I / O resources are dynamically adjusted in the test stage, and the chip test time is shortened.

Methods and apparatuses directed to. In some examples, a die package includes voltage logic that provides a voltage to a voltage rail, clock logic that generates a clock signal, and adaptive clock distribution logic that receives the clock signal and the voltage. The adaptive clock distribution logic can increment an event count when the clock signal is above a threshold frequency, or when the voltage is below a threshold voltage level. The die package also includes a processor that can monitor the event counts during operation and determine a status of the adaptive clock distribution logic based on the event counts. In some examples, the processor can test the adaptive clock distribution logic by causing the clock signal to operate above the threshold frequency, or causing the voltage logic to provide the voltage below the threshold voltage level. The processor can then read the event counts to determine the status.

A method and data processing system for characterizing a logical cell in an integrated circuit are provided. The method comprises identifying an input pin and output pin of the cell as a selected input pin and output pin, evaluating a model of the logical cell for each pair of input signals from a set comprising pairs of input signals, identifying a subset of the set based on the evaluation, and determining a propagation delay for each pair in the subset.

According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.

Example automatic test equipment (ATE) includes a transmitter to output a waveform to a transmission line; circuitry to detect data for the waveform on the transmission line, with the circuitry being configured to scan the waveform across a range of times and across a range of voltages to obtain the data for the waveform; and memory to store the data detected by the circuitry.

The invention discloses a low-orbit satellite-borne digital logic anomaly inspection method and a navigation baseband chip. Comprising the following steps: setting a corresponding verification data set and a configuration item for each digital logic unit; setting timing duration to inspect each digital logic unit in the chip at fixed time; judging whether the current polled digital logic unit is idle or not, if so, continuing to execute the subsequent steps, otherwise, switching to the next digital logic unit to continue polling; obtaining a verification data set and a configuration item corresponding to the current digital logic unit; configuring according to the configuration item, and sending standard data into a digital logic unit for starting to obtain feature data; judging whether the feature data is consistent with expected data or not, and if yes, judging that the digital logic unit works normally; if not, judging that the digital logic unit is abnormal; and repairing and reconfiguring the digital logic unit which is judged to be abnormal. According to the scheme of the invention, independent detection and anomaly repair of each digital logic unit can be realized, and the method is more targeted.

A test system has ovens configured to hold devices under test (DUTs), DUT switches, each connected to the DUTs in an oven, splitters, each splitter connected to a DUT switch, an instrument switch connected to one output of each splitter, the other output of each splitter connected to a test instrument, and one or more processors to control the instrument switch to select one of the DUT switches connected to an oven, control the selected DUT switch to connect each DUT in the oven to a channel of the test and measurement instrument, use machine learning to tune the DUT to a set of parameters until the DUT passes or fails, repeat the connecting, tuning, and testing of each DUT until all DUTs in an oven have been tested, and repeat the selection and control of the DUT switches until each DUT in each oven has been tuned and tested.

A scan island for automated data retrieval from an integrated circuit (IC) includes a data extraction module configured to extract data from multiple scan chains and random-access memory (RAM) modules in response to a trigger event, storing the data in an external non-volatile storage medium. The scan island further comprises a clock and reset module, which includes a free-running independent clock to enable continuous operation of the scan island upon occurrence of the trigger event, and a local reset module that re-initializes the scan island in a known state following the trigger event without external intervention. The scan island operates as an isolated partition within the IC, ensuring secure and autonomous data retrieval and recovery processes.

The invention discloses a chip testing method, system, medium and equipment, and relates to the technical field of chip testing electrical digital data processing. The method comprises the following steps: judging a chip to carry out an aging test or repair according to a first performance comparative analysis result of the chip; judging and determining an aging test process or repair of the chip according to a second performance comparative analysis result of the chip; and judging and determining a chip aging test result level according to the third performance comparative analysis result of the chip. According to the invention, performance evaluation analysis, stability analysis and evaluation and comprehensive test analysis and evaluation are respectively carried out on the dynamic random access memory chip, and the chip aging test result level is comprehensively judged according to the comparative analysis of the analysis and evaluation result and the corresponding threshold value. The effect of improving the aging test evaluation and judgment accuracy of the chip of the dynamic random access memory is achieved, and the problem that the aging test evaluation and judgment accuracy of the chip of the dynamic random access memory is insufficient in the prior art is solved.

An oscilloscope having a Nyquist frequency lower than an analog bandwidth includes an input configured to receive a signal under test; an analog-to-digital converter (ADC) to receive the signal under test, sample the signal under test at a sample rate, and produce digital samples of the signal under test; one or more processors configured to execute code that causes the one or more processors to: determine a set of candidate unit intervals by generating corresponding candidate histograms using the candidate unit intervals; determine a best unit interval from the candidate unit intervals based upon entropy measures of each candidate histogram; and reconstruct a representation of the signal under test using the digital samples and the best unit interval.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

An error rate measurement apparatus includes a display unit that displays a setting screen for setting a measurement condition of an error rate of an input signal from a DUT, and a processing unit that calculates a measurement time based on the measurement condition input to the setting screen, in which the setting screen includes a target confidence level input portion for inputting a target confidence level, a transmission rate input portion for inputting a transmission rate, a target error rate input portion for inputting a target error rate, an assumed-number-of-errors input portion for inputting an assumed number of errors during the measurement time, and a measurement time display portion for displaying the measurement time.

The invention relates to the field of data processing, in particular to a data caching method of an on-chip logic analyzer and a related device. The method comprises the following steps: acquiring to-be-processed input data through a trigger unit; marking corresponding to-be-analyzed data bits in the input data by adopting a significant bit mask; comparing whether the to-be-analyzed data bit is matched with the mode mask to obtain a matching result of the to-be-analyzed data bit; and according to the matching result and / or the data caching mode of the trigger unit, controlling the data storage process of the custom storage array and the ping-pong buffer area, so that target input data meeting the caching requirement in the input data is stored in the ping-pong buffer area. According to the method, the trigger conditions can be flexibly set according to specific analysis requirements, different debugging and analysis scenes are met, data related to the target event are more accurately captured, the adaptability and debugging efficiency of the logic analyzer and the utilization rate of storage resources are improved, and powerful support is provided for deep data analysis.