448results about "Digital circuit testing" patented technology

Disclosed is a test board which includes a substrate that includes a device under test (DUT) placement area where a first DUT and a second DUT are disposed, a first load switch connected in series with the first DUT and configured to be set to a switch on state or a switch off state based on a first enable signal, a second load switch connected in series with the second DUT and configured to be set to the switch on state or the switch off state depending on a second enable signal, and a test controller. The test controller may be configured to perform a test operation in a (1-1)-th mode by activating the first enable signal and deactivating the second enable signal and then perform the test operation in a (1-2)-th mode by deactivating the first enable signal and activating the second enable signal.

The invention provides a test vector construction method, which is used for constructing a test vector set required by a to-be-tested digital circuit, and comprises the following steps: S1, obtaining the to-be-tested digital circuit and a to-be-tested fault list corresponding to the to-be-tested digital circuit, the to-be-tested fault list comprising a plurality of circuit faults; s2, multiple rounds of simplification operation are executed until the number of circuit faults which can be detected by all the obtained test vectors is larger than or equal to a preset threshold value, all the test vectors obtained by each round of simplification operation are stored in a variable-capacity vector pool, the capacity of the vector pool corresponding to each round is a preset multiple of the capacity of the vector pool corresponding to the previous round, and the test vectors are stored in the variable-capacity vector pool; wherein each round of simplification operation comprises a static simplification stage and a dynamic simplification stage, the static simplification stage repeatedly fills a vector pool and reduces the number of test vectors in the vector pool, and the dynamic simplification stage fills a part of the uncertain items in the test vectors with the uncertain items obtained in the static simplification stage as 0 or 1.

Containerized orchestration of secure socket layer virtual private network benchmarking is disclosed. A test portal can accommodate developing test event information (TEI) based on test input information. Test input information can be used to generate event images, e.g., containers, that can be readily scaled, mutated, etc., via a containerization environment instance. One or more event image can be groups into a pod. An event image can be a new container, a previously used container, or a permutation of a container. Event image(s) can be retrieved from external sources, e.g., a library, a commercial vendor of event images, etc. TEI can be based on a pod(s) and communicated to a device-under-test (DUT). DUT performance can be measured, and results can be accessed by an entity, e.g., a test engineer, a results analysis engine, etc. Results can be employed to direct subsequent DUT testing.

Systems and methods for direct-to-RF (radio frequency) software-defined radio implementation of an active load-pull system are provided. A system may include a controller, a primary field-programmable gate array (FPGA) to control and collect waveform data from vector signal analyzers (VSAs), each comprising an analog-to-digital converter (ADC) connected to an ADC signal-conditioning circuit to directly capture RF measurements of an input signal at an RF fundamental frequency of test and harmonics, each ADC signal-conditioning circuit altering a signal amplitude and isolating a wanted RF frequency of measurement at either the RF fundamental frequency of test or a harmonic to be received by its ADC, first and second couplers generating each input signal by extracting forward and reverse traveling waves at RF from input and output ports of a device under test (DUT), the VSAs capturing the input signals directly at the RF fundamental frequency of test or a harmonic.

Systems and methods are provided for detecting bit errors and further processing bit error information. A method, according to one implementation, includes the step of receiving a binary test sequence pattern generated by a pattern generator at an input to a digital communications system under test, wherein the binary test sequence pattern includes a plurality of sub-patterns. The method also includes the step of receiving an output binary sequence from an output of the digital communications system. Also, the method includes comparing the binary test sequence pattern with the output binary sequence to detect bit errors. Based on correlation characteristics between the bit errors and each of the sub-patterns, the method also includes the step of determining whether the bit errors are caused by random factors or are caused by deterministic factors associated with the digital communications system.

The invention discloses a circuit board testing and quality screening automation method and system, and aims to solve the problems of low efficiency, insufficient precision and imperfect quality control of traditional circuit board testing. Precise positioning of the circuit board is achieved through the high-precision X / Y / Z three-dimensional positioning mechanical arm, parallel testing is conducted in combination with equipment such as a multi-channel oscilloscope, a signal source and a spectrum analyzer, and the testing efficiency is improved. Temperature and humidity control testing is carried out through the environment simulation bin, the thermal imager scans temperature distribution of the circuit board, a high-precision instrument is used for detecting signal integrity and analyzing electromagnetic compatibility, and the performance of the high-speed circuit board is ensured. A machine learning algorithm predicts potential faults, a test process is optimized, an automatic sorting system is adopted to separate qualified and unqualified circuit boards, and high consistency and high reliability of product quality are ensured. Through the automatic and intelligent testing process, the production efficiency, the quality control capability and the testing precision are greatly improved, and the labor cost and the production risk are reduced.

The density and power consumption of modern integrated circuits, such as Graphic Processing Units (GPUs), Central Processing Units (CPUs), and Network Processing Units (NPUs) is growing rapidly, which necessitates designing advanced cooling systems. Existing solutions for characterizing and validating these cooling system are inadequate. A flexible, scalable Thermal Test Vehicle (TTV) is disclosed which is based on an array of power transistors, measurement / control circuitry, and onboard computer. The TTV is configured for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

The invention discloses a digital circuit dependency analysis method, which comprises the following steps of: by analyzing the equality of a Boolean differential circuit, converting a dependency judgment problem of D on S into a problem of judging whether the Boolean differential circuit is constantly 0 or not; when whether the Boolean differential circuit is constantly 0 cannot be judged through X value simulation, logic negation is performed on the Boolean differential circuit, so that a dependency judgment problem is formally converted into a satisfiability problem, SAT solving is performed on the problem, whether D depends on S or not is judged according to a solving result, and if not, the Boolean differential circuit is judged to be zero. If the Boolean differential circuit is constrained, the satisfiability problem of the Boolean differential circuit is reconstructed, and the constrained Boolean differential circuit is subjected to SAT solution to further determine the dependency. According to the method, the digital circuit dependency analysis efficiency and accuracy are remarkably improved, the method is suitable for combinational logic circuit scenes of any scale and any complexity, the application range and efficiency of engineering application are greatly improved, and the method has remarkable industrial application value and popularization prospects.

Embodiments herein relate to testing chiplets during the manufacturing process. In one aspect, an on-chiplet interface is provided which allows testing of inter-chiplet communications of a chiplet on a package substrate without requiring the use of another chiplet. The interface communicates with an external Field-Programmable Gate Array (FPGA) on the package substrate at a reduced frequency compared to a frequency of the inter-chiplet communications. The FPGA can in turn communicate with a workstation to receive instructions and provide test results. The FPGA sends test pattern signals to, and evaluates corresponding responses from, circuitry of the chiplet which implements an inter-chiplet communication standard such as the Universal Chiplet Interconnect Express (UCIe) standard. In another aspect, the physical layer (PHY) circuits of two chiplet are tested with respective FPGAs.

Technologies for a jitter injection generator and a spectrum hardware engine for measuring and assessing phase noise and a jitter transfer function are described. One communication device includes a timing and synchronization circuit that generates a signal with time-domain data, and a spectrum hardware engine that converts this data into frequency-domain data. The spectrum hardware engine has registers storing past outputs, multipliers for computing products using these values and a pre-computed coefficient, and a summation block for combining the current input with these products to get the current output. This output is sent to a computing device to estimate phase noise.

Systems and methods for assessing display health in response to accidents are described. In some embodiments, an Information Handling System (IHS) may include an Embedded Controller (EC) and a memory coupled to the EC, where the memory comprises program instructions that, upon execution by the EC, cause the IHS to initiate an integrated display's Built-In-Self-Test (BIST) in response to a determination that the IHS suffered an accident.

A signal driver system can include one or more force amplifiers configured to provide drive signals to an output node, such as a device under test (DUT) node. The system can include a first switch circuit coupled between a first force amplifier and the output node, and the first switch circuit can include multiple parallel instances of switch circuits with respective different resistance characteristics. The system can include a second switch circuit coupled between a second force amplifier and the output node. The system can include a control circuit configured to control the switch circuit instances of the first switch circuit to mitigate glitch at the output node, for example, when switching between the first and second drive signals.

The integrated circuit includes a delay monitor that monitors a delay of the data signal from the digital circuitry by generating a pulse having a width determined by the delay. In some embodiments, a delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal for clocking the data signal. The pulse generator generates a pulse according to the received data signal and the clock signal, wherein a width of the pulse is determined by a delay of the data signal relative to the clock signal. The event generator generates events that are temporally distributed with respect to the clock signal. As a result, the delay may be estimated based on an overlap between the event and the pulse.

A test system includes a test and measurement instrument, ovens to hold devices under test (DUT), each oven having an oven switch selectably connected to the DUTs, channel switches selectably connected to the oven switches and to one channel of the instrument, one or more processors to: select an oven and its oven switch, connect that oven switch to a subset of DUTs in that oven, connect the channel switches to that oven switch to receive signals from the subset of DUTs, send the signals to channels of the instrument to acquire waveforms from the subset of DUTs in parallel, and repeat connecting of the channel switches and that oven switch until the instrument has acquired waveforms from each DUT in that oven, use machine learning to tune each DUT, test whether each DUT in that oven is optimally tuned, and repeat until all DUTs have been tuned and tested.

The performance of an adaptive microelectronic circuit is at least partly configurable by selecting a value of an operating parameter. On processing paths, data inputs of register units are coupled to outputs of respective logic units for temporarily storing output values of said logic units. A plurality of timing event monitors respond to a digital value at a data input of a monitored register unit changing later than an allowable time limit by generating a timing event observation signal. The plurality of timing event monitors form a plurality of monitor groups, each monitor group being coupled to a branch of a triggering signal tree for coupling a monitor-group-specific triggering signal to the monitor group independently of other monitor groups. A control unit selectively allows or disables the propagation of the respective triggering signals into said branches of the triggering signal tree.

The invention is suitable for the technical field of semiconductor chip testing, and provides a digital signal data acquisition method and system based on chip testing, and the method comprises the steps: a semiconductor testing machine generates and issues a global trigger instruction at a time, and achieves the unified driving of multiple pins based on a digital signal sequence through a first trigger instruction facing a tested chip, starting sampling and digitization of corresponding electric signals by a second trigger instruction oriented to the data sending equipment, aggregating the electric signals according to a test session, and sending the aggregated electric signals to the data processing equipment; the data processing equipment carries out parallel calculation on the received digital signal sampling data and caches a result; and the semiconductor test machine obtains the instruction through the test result and carries out asynchronous backward reading. Therefore, control, acquisition and calculation are decoupled and can be propelled in an overlapped manner, serial waiting and instruction round-trip are reduced, the test time can be shortened, and throughput and resource utilization rate are improved.

A monitoring apparatus for monitoring propagation delay of a signal along a path through an integrated circuit is disclosed. The monitoring device comprises a delay device configured to receive the signal and to generate a delayed signal, the delayed signal being a version of the received signal that is time delayed with respect to the received signal, a detection window device configured to generate a detection window signal based on a clock signal of the integrated circuit, and a determination device configured to determine the detection window signal based on the clock signal. The determination means is configured to determine whether a value of the received signal differs from a value of the delayed signal during a time defined by the detection window signal, and to generate a determination signal based on the determination.

A probe card includes a plurality of power lines that are electrically connected to the plurality of DUTs, a plurality of ground lines that are electrically connected to the plurality of DUTs and to each other, and a plurality of power compensation circuits that are electrically connected to respective ones of the plurality of power lines and respective ones of the plurality of ground lines, where the plurality of power compensation circuits are configured to generate and provide a plurality of compensated power supply voltages to the respective ones of the plurality of power lines, and where the plurality of compensated power supply voltages are configured to inhibit a variation of a ground voltage of the respective ones of the plurality of ground lines.

A method for Design For Test (DFT) for Source Synchronous Interfaces (SSI) includes shifting a test vector into a master register slice with a DFT clock. A functional clock is generated. The test vector and the functional clock are launched from a first SSI of the master register slice. The test vector and the functional clock are captured with a second SSI of a slave. The test vector is shifted out of the slave with the DFT clock.

To provide an automatized test system for transmitting a test signal to a device under test (DUT) and measuring a response signal from the DUT.SOLUTION: The test system can provide a test signal to, or receive a test signal from, a device under test (DUT) via a first signal path. The test system can be configured to present a stable (e.g., 50 ohm) impedance at a DUT interface. In an example, the stable impedance comprises a physical polysilicon resistor in series with an output stage of a driver circuit of the test system. The impedance of the output stage can be a function of an incremental impedance of transistors in a push-pull output circuit. In an example, a control loop is provided to change a bias condition for the transistors to adjust the impedance of the output stage.SELECTED DRAWING: Figure 1

This invention relates to the field of integrated circuit technology, and provides a measurement circuit and method for the setup and hold times of a D flip-flop. The measurement circuit uses a path matching module and a path adjustment module to coarsely adjust the delay time of the delay chain to obtain the setup and hold times of the D flip-flop; then, it uses a data signal delay adjustment module and a clock signal delay adjustment module to finely adjust the setup and hold times, narrowing the range of values ​​for the D flip-flop's setup and hold times. This improves measurement accuracy and testing efficiency, and solves the problem of insufficient measurement accuracy in existing technologies for measuring the setup and hold times of D flip-flops.

A fault injection evaluation method and system, and a computer program product and a medium. The fault injection evaluation method comprises: configuring a target number of cycles for a circuit under test (101), wherein the target number of cycles is the number of cycles during which said circuit operates after being reset; injecting a fault into said circuit (102); outputting a reset signal to said circuit, and acquiring a fault output result that is output by said circuit after the fault is injected (103); and on the basis of the fault output result and a reference output result, performing a comparison to acquire a fault evaluation result (104). By means of the method, it is not necessary to additionally provide a reference circuit, so that the structural complexity of the fault injection evaluation system can be reduced, and the consumption of resources required during evaluation can be reduced.

The invention discloses a closed-loop adaptive generative adversarial network filter. A test and measurement system includes: a plurality of nodes, one or more nodes including sensors configured to receive signals; one or more generative adversarial network (GAN) models; one or more signal generators configured to generate and transmit signals; and one or more processors configured to execute the code to cause the one or more processors to receive a request for a signal having a signal profile from one of the plurality of nodes, transmit the signal profile and the request to one of the one or more GAN models, receive a matching signal profile that matches the signal profile, and transmit the matching signal profile to the one of the one or more GAN models. And transmit the matching signal profile to one of the one or more signal generators to generate and transmit a matching signal.

An integrated circuit includes a comparator, a clock generator, and control circuitry. The comparator has a first input, a second input, and an output configured to provide an output clock. The clock generator is configured to generate a differential periodic signal formed from a first periodic signal and a second periodic signal. The clock generator provides the first periodic signal to the first input of the comparator and the second periodic signal to the second input of the comparator, and the clock generator is configured to vary an amplitude of the differential periodic signal based on a control input. The control circuitry is configured to measure hysteresis of the comparator by providing the control input to the clock generator to incrementally vary the amplitude of the differential periodic signal until detecting a predetermined number of state changes of the output clock.

Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector. The self-testing glitch signal is further fed back to the glitch controller for verification, and the glitch controller presents an error of the self-testing glitch signal by an error flag.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

A test and measurement system includes a machine learning system configured to communicate with a test automation system, a user interface configured to allow a user to provide one or more user inputs and to provide results to the user, and one or more processors, the one or more processors configured to execute code that causes the one or more processors to receive one or more user inputs through the user interface, the one or more user inputs at least identifying a selected machine learning system configuration to be used to configure the machine learning system, receive a waveform created by operation of a device under test, apply the configured machine learning system to analyze the waveform, and provide an output of predicted metadata about the waveform.

According to an aspect there is provided an optical monitoring device comprising:a first input for receiving a portion of a first optical signal coupled from a first waveguide into the first input;a second input for receiving at least a portion of a second optical signal coupled into the second input;a mixing unit for controlling combining of the portion of the first optical signal with the at least a portion of the second optical signal into a combined signal at an output from the mixing unit; andat least one photodetector for detecting the combined signal.The optical monitoring device is configured to apply a modulation signal to modulate at least one of a phase of the portion of the first and / or second optical signal, a coupling of the portion of the first and / or second optical signal into the respective input, or an amplitude of the portion of the first and / or second optical signal being transferred into the combined signal.

A detection device includes a window clock output circuit configured to output a first window clock having a second period greater than a first period of a common clock, and a second window clock having the second period and delayed by a specific amount of time relative to the first window clock, and a defect detection circuit configured to detect consecutive edges included in the common clock from logic high periods of the first window clock and the second window clock and logic low periods of the first window clock and the second window clock.

In an aspect, a method of detecting settling of an analog electrical signal in semiconductor device testing includes providing in a semiconductor device tester a device under test (DUT); providing an input signal to the DUT and measuring the input signal; tracking the measurements over time by overlapping the measured input signal with sequential measurement windows that do not overlap with each other, each measurement window spanning a constant measurement period and a constant signal value range while shifting according to measured changes in the input signal such that each measurement window overlaps at least a portion of the measured input signal corresponding to a preceding measurement window; setting a settle count representing a number of consecutive and unshifted measurement windows having unshifted constant signal value ranges; setting a settle count representing a number of consecutive and unshifted measurement windows having unshifted constant signal value ranges; and determining that a settle point has been reached after detecting that the settle count has been met or exceeded by the measured input signal tracked by the sequential measurement windows. Aspects also include an apparatus for adapted performing the aforementioned method and a non-transitory computer storage medium containing instructions that when read by one or more computer processors perform the aforementioned method.