1279results about "Digital circuit testing" patented technology

The invention relates to a probe suite multifunctional test method and system based on wafer test, and the method comprises the steps: obtaining the to-be-tested data of a wafer and the parameter information of a probe and a probe card; and through a preset intelligent algorithm, the contact state of the probe tip and the wafer is judged according to the working parameters, and the contact pressure and the probe impedance are dynamically adjusted. Meanwhile, environmental parameters including temperature, humidity and electromagnetic interference intensity in a test area are obtained, and when the environmental parameters exceed a preset range, the environment is automatically optimized. And detecting wafer characteristics based on the to-be-tested data, preprocessing the initial test data to obtain wafer test data, and performing real-time analysis and anomaly detection. And finally, according to an analysis detection result, whether the probe is adjusted or self-repaired is judged, and meanwhile, the test parameters and the working mode of the probe card are dynamically adjusted, so that high-precision and high-stability wafer test is realized, the performance of the probe and a test system is guaranteed, and the accuracy and the reliability of semiconductor test are improved.

Power-gated domains are provided for design for test (DFT) and / or design for debug (DFX) logic units in a semiconductor chip. Power-gated domains allow power consumption to be reduced when DFT and DFD logic units are not in use. Power-gated domains can include reset features and output port power isolation.

Fault detection circuits and methods. An example of a fault detection circuit includes a comparator configured to compare a voltage at a voltage terminal with a reference voltage, a digital logic circuit coupled to a test terminal and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the digital logic circuit including at least one digital logic gate, and an edge detection circuit configured to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal.

A system includes an input to receive a digital waveform signal, a memory, and one or more processors configured to execute code to cause the one or more processors to: generate a horizontal ramp sweep signal based on the digital waveform signal; receive a selection input to identify a segment of the digital waveform signal; gate the horizontal ramp sweep signal and the digital waveform signal based on the selection input to produce cyclic loop image data for the segment of the digital waveform; store the cyclic loop image data in the memory; and provide the cyclic loop image data as one or more inputs into a machine learning system. A method of waveform classification using a cyclic loop image includes receiving an input waveform, receiving a selection of a segment of the input waveform, transforming the segment of the input waveform into cyclic loop image data, the transforming comprising generating a horizontal ramp sweep signal based on edge transitions in the input waveform, and storing the cyclic loop image data in a memory; and sending the cyclic loop image data to a machine learning system to determine an attribute of the input waveform.

An error rate measurement apparatus includes a display control unit, an operation display unit, and a control unit. The display control unit displays a firsts coefficient value in a selectable manner by tabs of a number corresponding to a Full Swing value, performs matrix display on a display screen by using each one of combinations of each second coefficient value and each third coefficient value in the first coefficient value on the selected tab, and displays each coefficient value on the display screen in a three-dimensional bird-eye view by using each second coefficient value and each third coefficient value as a combination of a horizontal direction coordinate axis and a vertical direction coordinate axis and using the first coefficient value as a depth direction coordinate axis. The operation display unit selects a range including at least one cell as a scanning target in the matrix display or a bird-eye display.

Scan testing features on a chip may include a streaming scan network (SSN) with core streaming scan hubs (CSHs). A CSH may include a parent bus interface, a child bus interface, and a streaming scan hub (SSH). A CSH may also include multiplexing logic configured to select whether the child bus interface is included in the SSN or excluded from the SSN. Multiple CSHs may be interconnected in a hierarchical topology through the child bus interfaces.

An eye-diagram index analytic method includes: calculating a transfer function of multiple coupled lines; converting the transfer function into a pulse response; calculating an eye-diagram index according to the pulse response; and correcting the eye-diagram index according to peak distortion analysis.

Systems and methods for assessing display health in response to accidents are described. In some embodiments, an Information Handling System (IHS) may include an Embedded Controller (EC) and a memory coupled to the EC, where the memory comprises program instructions that, upon execution by the EC, cause the IHS to initiate an integrated display's Built-In-Self-Test (BIST) in response to a determination that the IHS suffered an accident.

This disclosure provides systems, methods, and devices for memory systems that support enhanced processing core scheduling schemes. In a first aspect, a system-on-a-chip (SoC) includes functional logic configured to perform one or more functions and self-testing logic configured to perform a self-testing operation on the functional logic. The SoC also includes a plurality of power domains, including a functional power domain coupled to the functional logic and configured to provide power to the functional logic and a self-testing power domain coupled to the self-testing logic and configured to provide power to the self-testing logic. The SoC further includes power control logic configured to control power delivery from the plurality of power domains to the functional logic and the self-testing logic and configured to power collapse the self-testing logic. Other aspects and features are also claimed and described.

A power vector analyzer to analyze power from a device under test (DUT) includes one or more channels to measure a reference voltage signal from a power line connected to the DUT, one or more channels to measure a reference current signal from the power line, a user interface comprising a display and one or more controls, and a quadrature synchronous detector (QSD) for each phase of apparent power being measured, the QSD configured to use a reference voltage signal from the one or more channels and a reference current signal from the one or more channels to determine the apparent power for each phase of power being measured by the DUT and display the apparent power for each phase on the display.

A method and data processing system for characterizing a logical cell in an integrated circuit are provided. The method comprises identifying an input pin and output pin of the cell as a selected input pin and output pin, evaluating a model of the logical cell for each pair of input signals from a set comprising pairs of input signals, identifying a subset of the set based on the evaluation, and determining a propagation delay for each pair in the subset.

According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.

Example automatic test equipment (ATE) includes a transmitter to output a waveform to a transmission line; circuitry to detect data for the waveform on the transmission line, with the circuitry being configured to scan the waveform across a range of times and across a range of voltages to obtain the data for the waveform; and memory to store the data detected by the circuitry.

The invention discloses a low-orbit satellite-borne digital logic anomaly inspection method and a navigation baseband chip. Comprising the following steps: setting a corresponding verification data set and a configuration item for each digital logic unit; setting timing duration to inspect each digital logic unit in the chip at fixed time; judging whether the current polled digital logic unit is idle or not, if so, continuing to execute the subsequent steps, otherwise, switching to the next digital logic unit to continue polling; obtaining a verification data set and a configuration item corresponding to the current digital logic unit; configuring according to the configuration item, and sending standard data into a digital logic unit for starting to obtain feature data; judging whether the feature data is consistent with expected data or not, and if yes, judging that the digital logic unit works normally; if not, judging that the digital logic unit is abnormal; and repairing and reconfiguring the digital logic unit which is judged to be abnormal. According to the scheme of the invention, independent detection and anomaly repair of each digital logic unit can be realized, and the method is more targeted.

A test system has ovens configured to hold devices under test (DUTs), DUT switches, each connected to the DUTs in an oven, splitters, each splitter connected to a DUT switch, an instrument switch connected to one output of each splitter, the other output of each splitter connected to a test instrument, and one or more processors to control the instrument switch to select one of the DUT switches connected to an oven, control the selected DUT switch to connect each DUT in the oven to a channel of the test and measurement instrument, use machine learning to tune the DUT to a set of parameters until the DUT passes or fails, repeat the connecting, tuning, and testing of each DUT until all DUTs in an oven have been tested, and repeat the selection and control of the DUT switches until each DUT in each oven has been tuned and tested.

A scan island for automated data retrieval from an integrated circuit (IC) includes a data extraction module configured to extract data from multiple scan chains and random-access memory (RAM) modules in response to a trigger event, storing the data in an external non-volatile storage medium. The scan island further comprises a clock and reset module, which includes a free-running independent clock to enable continuous operation of the scan island upon occurrence of the trigger event, and a local reset module that re-initializes the scan island in a known state following the trigger event without external intervention. The scan island operates as an isolated partition within the IC, ensuring secure and autonomous data retrieval and recovery processes.

An oscilloscope having a Nyquist frequency lower than an analog bandwidth includes an input configured to receive a signal under test; an analog-to-digital converter (ADC) to receive the signal under test, sample the signal under test at a sample rate, and produce digital samples of the signal under test; one or more processors configured to execute code that causes the one or more processors to: determine a set of candidate unit intervals by generating corresponding candidate histograms using the candidate unit intervals; determine a best unit interval from the candidate unit intervals based upon entropy measures of each candidate histogram; and reconstruct a representation of the signal under test using the digital samples and the best unit interval.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

The invention relates to the field of data processing, in particular to a data caching method of an on-chip logic analyzer and a related device. The method comprises the following steps: acquiring to-be-processed input data through a trigger unit; marking corresponding to-be-analyzed data bits in the input data by adopting a significant bit mask; comparing whether the to-be-analyzed data bit is matched with the mode mask to obtain a matching result of the to-be-analyzed data bit; and according to the matching result and / or the data caching mode of the trigger unit, controlling the data storage process of the custom storage array and the ping-pong buffer area, so that target input data meeting the caching requirement in the input data is stored in the ping-pong buffer area. According to the method, the trigger conditions can be flexibly set according to specific analysis requirements, different debugging and analysis scenes are met, data related to the target event are more accurately captured, the adaptability and debugging efficiency of the logic analyzer and the utilization rate of storage resources are improved, and powerful support is provided for deep data analysis.

Disclosed is a test board which includes a substrate that includes a device under test (DUT) placement area where a first DUT and a second DUT are disposed, a first load switch connected in series with the first DUT and configured to be set to a switch on state or a switch off state based on a first enable signal, a second load switch connected in series with the second DUT and configured to be set to the switch on state or the switch off state depending on a second enable signal, and a test controller. The test controller may be configured to perform a test operation in a (1-1)-th mode by activating the first enable signal and deactivating the second enable signal and then perform the test operation in a (1-2)-th mode by deactivating the first enable signal and activating the second enable signal.

The invention relates to a waveform data preloading method and device and electronic equipment. The method comprises the following steps: receiving test coding results corresponding to a plurality of pins and issued by an upper computer, wherein the test coding results comprise data formats, coded data and repeated indication parameters; wherein the data format is used for representing the data type of the coded data; the repetition indication parameter is used for indicating that the coded data is not repeatedly reserved during decompression, or indicating the number of repetition times of the coded data during decompression; decompressing the coded data based on the data format and the repeated indication parameter to obtain original waveform data for testing each pin; preloading the original waveform data corresponding to each pin into a storage unit; wherein the original waveform data corresponding to the same pin are stored in the same row of the storage unit, and the original waveform data corresponding to different pins are stored in different rows. According to the method, the preloading efficiency can be improved.

The invention provides a test vector construction method, which is used for constructing a test vector set required by a to-be-tested digital circuit, and comprises the following steps: S1, obtaining the to-be-tested digital circuit and a to-be-tested fault list corresponding to the to-be-tested digital circuit, the to-be-tested fault list comprising a plurality of circuit faults; s2, multiple rounds of simplification operation are executed until the number of circuit faults which can be detected by all the obtained test vectors is larger than or equal to a preset threshold value, all the test vectors obtained by each round of simplification operation are stored in a variable-capacity vector pool, the capacity of the vector pool corresponding to each round is a preset multiple of the capacity of the vector pool corresponding to the previous round, and the test vectors are stored in the variable-capacity vector pool; wherein each round of simplification operation comprises a static simplification stage and a dynamic simplification stage, the static simplification stage repeatedly fills a vector pool and reduces the number of test vectors in the vector pool, and the dynamic simplification stage fills a part of the uncertain items in the test vectors with the uncertain items obtained in the static simplification stage as 0 or 1.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

A disclosed technique includes based on a clock pattern, determining an enable configuration for setting enable signals for one or more multi-cycle paths of a hardware logic network; controlling a selector to set the enable configuration for the one or more multi-cycle paths; and executing testing operations for the hardware logic network with the one or more multi-cycle paths enabled according to the enable configuration.

Methods, apparatus, and computer programs are disclosed to detect computing system hardware defects using a portable storage device. In one embodiment, a method includes accessing a portable storage device to obtain an identifier and a set of test patterns to test a set of circuits of a computing system, the identifier to map to the set of test patterns. The method further includes determining that the set of test patterns is to be executed on the computing system based on the identifier to be obtained from accessing the portable storage device. Responsive to the determination, and executing the set of test patterns loaded from the portable storage device on the set of circuits of the computing system to detect one or more hardware defects of the set of circuits.

A method for determining a sparse memory size during emulation, the method including: determining, by a profiler memory coupled to a user memory, that one or more pages of the user memory are used by a first test sequence of a testbench during the emulation; identifying, by the profiler memory, a first set of indexes of the one or more pages of the user memory used by the first test sequence; determining a number of unique pages of the user memory that are used by the first test sequence for the emulation based on the first set of indexes; determining, by a processor, the sparse memory size for the user memory based on the number of unique pages of the user memory that are used by the testbench for the emulation and a page size of the user memory.

Containerized orchestration of secure socket layer virtual private network benchmarking is disclosed. A test portal can accommodate developing test event information (TEI) based on test input information. Test input information can be used to generate event images, e.g., containers, that can be readily scaled, mutated, etc., via a containerization environment instance. One or more event image can be groups into a pod. An event image can be a new container, a previously used container, or a permutation of a container. Event image(s) can be retrieved from external sources, e.g., a library, a commercial vendor of event images, etc. TEI can be based on a pod(s) and communicated to a device-under-test (DUT). DUT performance can be measured, and results can be accessed by an entity, e.g., a test engineer, a results analysis engine, etc. Results can be employed to direct subsequent DUT testing.

A device includes a communication interface, a command processing circuit, a clock synchronization circuit, and a controllable clock source. The command processing circuit has a command input, a reference frequency output, and a reference phase output. The command input is coupled to the communication interface. The clock synchronization circuit has a reference frequency input, a reference phase input, and a frequency control output. The reference frequency output is coupled to the reference frequency input, and the reference phase input coupled to the reference phase output. The clock synchronization circuit includes a frequency synchronization circuit and a phase synchronization circuit. The controllable clock source has a frequency control input and a clock output. The frequency control input is coupled to the frequency control output.

Fault detection circuits and methods. An example of a fault detection circuit includes a comparator configured to compare a voltage at a voltage terminal with a reference voltage, a digital logic circuit coupled to a test terminal and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the digital logic circuit including at least one digital logic gate, and an edge detection circuit configured to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal.

An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serializer without utilizing a deserializer.