1120results about "Digital circuit testing" patented technology

The invention relates to a probe suite multifunctional test method and system based on wafer test, and the method comprises the steps: obtaining the to-be-tested data of a wafer and the parameter information of a probe and a probe card; and through a preset intelligent algorithm, the contact state of the probe tip and the wafer is judged according to the working parameters, and the contact pressure and the probe impedance are dynamically adjusted. Meanwhile, environmental parameters including temperature, humidity and electromagnetic interference intensity in a test area are obtained, and when the environmental parameters exceed a preset range, the environment is automatically optimized. And detecting wafer characteristics based on the to-be-tested data, preprocessing the initial test data to obtain wafer test data, and performing real-time analysis and anomaly detection. And finally, according to an analysis detection result, whether the probe is adjusted or self-repaired is judged, and meanwhile, the test parameters and the working mode of the probe card are dynamically adjusted, so that high-precision and high-stability wafer test is realized, the performance of the probe and a test system is guaranteed, and the accuracy and the reliability of semiconductor test are improved.

Power-gated domains are provided for design for test (DFT) and / or design for debug (DFX) logic units in a semiconductor chip. Power-gated domains allow power consumption to be reduced when DFT and DFD logic units are not in use. Power-gated domains can include reset features and output port power isolation.

A system includes an input to receive a digital waveform signal, a memory, and one or more processors configured to execute code to cause the one or more processors to: generate a horizontal ramp sweep signal based on the digital waveform signal; receive a selection input to identify a segment of the digital waveform signal; gate the horizontal ramp sweep signal and the digital waveform signal based on the selection input to produce cyclic loop image data for the segment of the digital waveform; store the cyclic loop image data in the memory; and provide the cyclic loop image data as one or more inputs into a machine learning system. A method of waveform classification using a cyclic loop image includes receiving an input waveform, receiving a selection of a segment of the input waveform, transforming the segment of the input waveform into cyclic loop image data, the transforming comprising generating a horizontal ramp sweep signal based on edge transitions in the input waveform, and storing the cyclic loop image data in a memory; and sending the cyclic loop image data to a machine learning system to determine an attribute of the input waveform.

Scan testing features on a chip may include a streaming scan network (SSN) with core streaming scan hubs (CSHs). A CSH may include a parent bus interface, a child bus interface, and a streaming scan hub (SSH). A CSH may also include multiplexing logic configured to select whether the child bus interface is included in the SSN or excluded from the SSN. Multiple CSHs may be interconnected in a hierarchical topology through the child bus interfaces.

Systems and methods for assessing display health in response to accidents are described. In some embodiments, an Information Handling System (IHS) may include an Embedded Controller (EC) and a memory coupled to the EC, where the memory comprises program instructions that, upon execution by the EC, cause the IHS to initiate an integrated display's Built-In-Self-Test (BIST) in response to a determination that the IHS suffered an accident.

This disclosure provides systems, methods, and devices for memory systems that support enhanced processing core scheduling schemes. In a first aspect, a system-on-a-chip (SoC) includes functional logic configured to perform one or more functions and self-testing logic configured to perform a self-testing operation on the functional logic. The SoC also includes a plurality of power domains, including a functional power domain coupled to the functional logic and configured to provide power to the functional logic and a self-testing power domain coupled to the self-testing logic and configured to provide power to the self-testing logic. The SoC further includes power control logic configured to control power delivery from the plurality of power domains to the functional logic and the self-testing logic and configured to power collapse the self-testing logic. Other aspects and features are also claimed and described.

A power vector analyzer to analyze power from a device under test (DUT) includes one or more channels to measure a reference voltage signal from a power line connected to the DUT, one or more channels to measure a reference current signal from the power line, a user interface comprising a display and one or more controls, and a quadrature synchronous detector (QSD) for each phase of apparent power being measured, the QSD configured to use a reference voltage signal from the one or more channels and a reference current signal from the one or more channels to determine the apparent power for each phase of power being measured by the DUT and display the apparent power for each phase on the display.

According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.

Example automatic test equipment (ATE) includes a transmitter to output a waveform to a transmission line; circuitry to detect data for the waveform on the transmission line, with the circuitry being configured to scan the waveform across a range of times and across a range of voltages to obtain the data for the waveform; and memory to store the data detected by the circuitry.

The invention discloses a low-orbit satellite-borne digital logic anomaly inspection method and a navigation baseband chip. Comprising the following steps: setting a corresponding verification data set and a configuration item for each digital logic unit; setting timing duration to inspect each digital logic unit in the chip at fixed time; judging whether the current polled digital logic unit is idle or not, if so, continuing to execute the subsequent steps, otherwise, switching to the next digital logic unit to continue polling; obtaining a verification data set and a configuration item corresponding to the current digital logic unit; configuring according to the configuration item, and sending standard data into a digital logic unit for starting to obtain feature data; judging whether the feature data is consistent with expected data or not, and if yes, judging that the digital logic unit works normally; if not, judging that the digital logic unit is abnormal; and repairing and reconfiguring the digital logic unit which is judged to be abnormal. According to the scheme of the invention, independent detection and anomaly repair of each digital logic unit can be realized, and the method is more targeted.

A test system has ovens configured to hold devices under test (DUTs), DUT switches, each connected to the DUTs in an oven, splitters, each splitter connected to a DUT switch, an instrument switch connected to one output of each splitter, the other output of each splitter connected to a test instrument, and one or more processors to control the instrument switch to select one of the DUT switches connected to an oven, control the selected DUT switch to connect each DUT in the oven to a channel of the test and measurement instrument, use machine learning to tune the DUT to a set of parameters until the DUT passes or fails, repeat the connecting, tuning, and testing of each DUT until all DUTs in an oven have been tested, and repeat the selection and control of the DUT switches until each DUT in each oven has been tuned and tested.

An oscilloscope having a Nyquist frequency lower than an analog bandwidth includes an input configured to receive a signal under test; an analog-to-digital converter (ADC) to receive the signal under test, sample the signal under test at a sample rate, and produce digital samples of the signal under test; one or more processors configured to execute code that causes the one or more processors to: determine a set of candidate unit intervals by generating corresponding candidate histograms using the candidate unit intervals; determine a best unit interval from the candidate unit intervals based upon entropy measures of each candidate histogram; and reconstruct a representation of the signal under test using the digital samples and the best unit interval.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

Disclosed is a test board which includes a substrate that includes a device under test (DUT) placement area where a first DUT and a second DUT are disposed, a first load switch connected in series with the first DUT and configured to be set to a switch on state or a switch off state based on a first enable signal, a second load switch connected in series with the second DUT and configured to be set to the switch on state or the switch off state depending on a second enable signal, and a test controller. The test controller may be configured to perform a test operation in a (1-1)-th mode by activating the first enable signal and deactivating the second enable signal and then perform the test operation in a (1-2)-th mode by deactivating the first enable signal and activating the second enable signal.

The invention relates to a waveform data preloading method and device and electronic equipment. The method comprises the following steps: receiving test coding results corresponding to a plurality of pins and issued by an upper computer, wherein the test coding results comprise data formats, coded data and repeated indication parameters; wherein the data format is used for representing the data type of the coded data; the repetition indication parameter is used for indicating that the coded data is not repeatedly reserved during decompression, or indicating the number of repetition times of the coded data during decompression; decompressing the coded data based on the data format and the repeated indication parameter to obtain original waveform data for testing each pin; preloading the original waveform data corresponding to each pin into a storage unit; wherein the original waveform data corresponding to the same pin are stored in the same row of the storage unit, and the original waveform data corresponding to different pins are stored in different rows. According to the method, the preloading efficiency can be improved.

The invention provides a test vector construction method, which is used for constructing a test vector set required by a to-be-tested digital circuit, and comprises the following steps: S1, obtaining the to-be-tested digital circuit and a to-be-tested fault list corresponding to the to-be-tested digital circuit, the to-be-tested fault list comprising a plurality of circuit faults; s2, multiple rounds of simplification operation are executed until the number of circuit faults which can be detected by all the obtained test vectors is larger than or equal to a preset threshold value, all the test vectors obtained by each round of simplification operation are stored in a variable-capacity vector pool, the capacity of the vector pool corresponding to each round is a preset multiple of the capacity of the vector pool corresponding to the previous round, and the test vectors are stored in the variable-capacity vector pool; wherein each round of simplification operation comprises a static simplification stage and a dynamic simplification stage, the static simplification stage repeatedly fills a vector pool and reduces the number of test vectors in the vector pool, and the dynamic simplification stage fills a part of the uncertain items in the test vectors with the uncertain items obtained in the static simplification stage as 0 or 1.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

Containerized orchestration of secure socket layer virtual private network benchmarking is disclosed. A test portal can accommodate developing test event information (TEI) based on test input information. Test input information can be used to generate event images, e.g., containers, that can be readily scaled, mutated, etc., via a containerization environment instance. One or more event image can be groups into a pod. An event image can be a new container, a previously used container, or a permutation of a container. Event image(s) can be retrieved from external sources, e.g., a library, a commercial vendor of event images, etc. TEI can be based on a pod(s) and communicated to a device-under-test (DUT). DUT performance can be measured, and results can be accessed by an entity, e.g., a test engineer, a results analysis engine, etc. Results can be employed to direct subsequent DUT testing.

Fault detection circuits and methods. An example of a fault detection circuit includes a comparator configured to compare a voltage at a voltage terminal with a reference voltage, a digital logic circuit coupled to a test terminal and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the digital logic circuit including at least one digital logic gate, and an edge detection circuit configured to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal.

An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serializer without utilizing a deserializer.

The invention provides a wireless connection method and system for digital circuit JATG debugging, a medium and equipment, and the method comprises the steps: 1, achieving the wireless connection through employing a JATG interface signal wireless unvarnished transmission A-end part and a B-end part, enabling the A-end part to be connected with an adapter through a JATG interface flat cable, enabling the B-end part to be connected with a JATG interface of target equipment, and enabling the A-end part to be connected with the adapter through a JATG interface flat cable; data transmission is carried out between the A-end component and the B-end component through WIFI signals. The adapter is connected with the debugging computer through a USB data line and communicates with target equipment through a wireless signal; 2, setting a multi-bit dial switch to set a unique matching address for each B-end component; and step 3, controlling the A-end component and the corresponding B-end component to be wirelessly matched and connected through a dial switch or a USB serial port command after power-on, and performing online debugging, testing and program updating on target equipment by using IDE software interface operation after wireless connection is completed.

A component die validation built-in self-test (VBIST) engine is presented. In an aspect, a component die includes component circuitry for performing a component function, interface circuitry for communicating with another die, and a VBIST circuit. The VBIST circuit includes a traffic generator that generates test data streams, a tracker that receives and validates test data streams, and a configurable switching matrix for coupling the traffic generator to at least one of the component circuitry, the interface circuitry, or the tracker, and for coupling at least one of the component circuitry, the interface circuitry, or the traffic generator to the tracker. The VBIST circuit can send traffic to and from the component circuitry directly, or indirectly via the interface circuitry in loopback mode, and can be used for memory initialization and test.

Systems and methods for direct-to-RF (radio frequency) software-defined radio implementation of an active load-pull system are provided. A system may include a controller, a primary field-programmable gate array (FPGA) to control and collect waveform data from vector signal analyzers (VSAs), each comprising an analog-to-digital converter (ADC) connected to an ADC signal-conditioning circuit to directly capture RF measurements of an input signal at an RF fundamental frequency of test and harmonics, each ADC signal-conditioning circuit altering a signal amplitude and isolating a wanted RF frequency of measurement at either the RF fundamental frequency of test or a harmonic to be received by its ADC, first and second couplers generating each input signal by extracting forward and reverse traveling waves at RF from input and output ports of a device under test (DUT), the VSAs capturing the input signals directly at the RF fundamental frequency of test or a harmonic.

The invention relates to the technical field of chip detection, and discloses a power supply adjusting and testing system, method and device for chip post-silicon verification, a medium and a product, the system comprises a voltage regulating module, a control module and at least one detection module; each detection module is arranged on a power supply path between each power domain of the chip to be detected and the corresponding power module; the control module is in communication connection with the voltage regulating module and the detection module. The control module is used for generating a target voltage regulation signal according to the debugging and testing instruction so as to control the voltage regulation module to perform voltage bias corresponding to the target power supply domain; and when the target power data on the power supply path of the target power supply domain meets a termination condition, controlling the voltage regulating module to terminate voltage bias. By integrating the functions of voltage regulation, detection and control, a traditional external instrument is replaced, the problems that a test environment is complex to build, the power supply quality is damaged and multi-channel parallel test is limited are solved, and the test efficiency and the chip verification reliability are remarkably improved.

A method for detecting non-convergence error in a transient circuit simulation wherein a circuit netlist and control statements associated with a circuit for the transient circuit simulation are received. A transient circuit simulation is performed responsive to a time point. Whether a non-convergence error has occurred during transient circuit simulation is determined. A transient debug mode is actuated responsive to determination of occurrence of the non-convergence error. The steps of performing the transient circuit simulation and determining whether a non-convergence error has occurred are repeated after actuation of the transient debug mode. Results of the transient circuit simulation are provided responsive to a determination of non-occurrence of a non-convergence error.

A test device includes a plurality of input / output terminals configured to be electrically connected to the devices formed on the wafer, a comparative circuit configured to receive a plurality of test signals from a device under test formed on the wafer, and generate a plurality of test result signals, based on the plurality of test signals, and a memory configured to receive the plurality of test result signals and store bad cell information and repair information related to the device under test, which are indicated by the plurality of test result signals, wherein the total number of the plurality of test signals received from the device under test at one time is an integer.

The invention provides a protection method and system based on key signal single particle error state coding characterization, which realizes key signal error state characterization and storage through key signal STMR and error key signal ID number coding and through data frames and control frames, and finally completes error state analysis by using a monitoring unit program in a PS system. And forming a protection decision. According to the invention, the resource overhead and the data transmission bandwidth of the user function circuit can be reduced, the reliability of the user function circuit system realized based on the SoC type FPGA is improved, and the method has applicability and operability for the digital circuit system of the electronic equipment for space navigation.

The present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, the codeword comprising payload data stored in a plurality of memory cells of the array, parity data associated with the payload data stored in parity cells of the memory array, wherein a number of parity cells to be used to store the parity data is selectable based on a status of the plurality of memory cells and is related to a selected Error Correction Code (ECC) protection level, and extra payload data stored in unused parity cells, the device further comprising a decoding unit configured to perform an ECC operation on the stored codeword based on the selected ECC protection level. The encoding unit and the decoding unit comprise respective circuit portions configured to be selectively activable based on the selected ECC protection level, and each circuit portion is configured to manage a respective predetermined payload and parity quantity of the codeword.

Aspects of the present disclosure include a method, a switch, and / or a computer readable medium for analyzing a window of samples at an expected position of a plurality of input edges of a plurality of input waveforms, detecting the plurality of input edges, measuring a displacement of each input edge, with respect to a previous position, of the plurality of input edges, generating a value of the displacement of each input edge, incrementing a corresponding counter value of a plurality of accumulator values in response to each value of the displacement of a corresponding accumulator of the plurality of accumulators, normalizing the plurality of accumulator values, generating the plurality of accumulator values, summing the plurality of accumulator values output by the plurality of accumulators to generate an accumulated jitter value, and sending jitter result information based on the accumulated jitter value.

Systems and methods are provided for detecting bit errors and further processing bit error information. A method, according to one implementation, includes the step of receiving a binary test sequence pattern generated by a pattern generator at an input to a digital communications system under test, wherein the binary test sequence pattern includes a plurality of sub-patterns. The method also includes the step of receiving an output binary sequence from an output of the digital communications system. Also, the method includes comparing the binary test sequence pattern with the output binary sequence to detect bit errors. Based on correlation characteristics between the bit errors and each of the sub-patterns, the method also includes the step of determining whether the bit errors are caused by random factors or are caused by deterministic factors associated with the digital communications system.