3455results about "Digital circuit testing" patented technology

A main power supply continuously provides a current to a power input terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases during state changes in synchronous logic circuits implemented within the DUT. To limit variation (noise) in voltage at the power input terminal arising from these temporary increases in current demand, a charged capacitor is connected to the power input terminal during each DUT state change. The capacitor discharges into the power input terminal to supply additional current to meet the DUT's increased demand. Following each DUT state change the capacitor is disconnected from the power input terminal and charged to a level sufficient to meet a predicted increase in current demand during a next DUT state change.

A method and apparatus for tracing hardware states using dynamically reconfigurable test circuits provides improved debug and troubleshooting capability for functional logic implemented within field programmable logic arrays (FPGAs). Special test logic configurations may be loaded to enhance the debugging of a system using FPGAs. Registers are used to capture snapshots of internal signals for access by a trace program and a test multiplexer is used to provide real-time output to test pins for use with external test equipment. By retrieving the hardware snapshot information with a trace program running on a system in which the FPGA is used, software and hardware debugging are coordinated, providing a sophisticated model of overall system behavior. Special test circuits are implemented within the test logic configurations to enable detection of various events and errors. Counters are used to capture count values when system processor execution reaches a hardware trace point or when events occur. Comparators are used to detect specific data or address values and event detectors are used to detect particular logic value combinations that occur within the functional logic.

The present invention discloses a testing circuit and method for thin film transistor display array, for testing the yield of thin film transistor array. The testing circuit comprising: An array tester, a test panel (DUT), a sense amplifier array. The sense amplifier is composed by a plurality of trans- impedance amplifier unit and a plurality of parasitic capacitance discharge circuit unit. Every sense amplifier includes: a trans-impedance amplifier, which is implemented by an operational amplifier, two switches and an operation capacitance, the trans-impedance amplifier is used to form an integrated circuit, the output is transmitted to a sampling/hold circuit via a switch; a parasitic capacitance discharge circuit is used to form a discharge rout for the charge of the parasitic capacitance.

An integrated circuit system has a reference data table for holding information that is used to control at least one circuit block in the system and also has a power supply circuit, a body bias control circuit, a clock delivery circuit, a temperature monitor circuit, and/or a configuration control circuit. The performance of the system is improved by obtaining system performance data by testing the system at different supply voltages, different body-bias voltages, different clock speeds, and/or different temperatures. Values based on the data are entered into the reference data table. The power supply circuit, the body bias control circuit, the clock delivery circuit, and/or the temperature monitor circuit data is adjusted using the entered values.

A system and method of ensuring hardware security of a device, such as an integrated circuit having secure data stored thereon. The integrated circuit or other hardware device can implement one or more configurable fuses that limit access to one or more secure locations within the device. The secure locations may contain secure data. The state of the configurable fuses can be ensured, thereby limiting access to secure locations, by forcing the occurrence of a logical state prior to allowing access to hardware locations configured by the fuses. A configurable non-secure access code can be used to force the occurrence of the logical state. Receipt of the non-secure access code by the hardware device forces the occurrence of the hardware state, thereby ensuring access only to those secure locations configured by the fuses.

A method for testing a semiconductor device with a multi-gigabit communications receiver includes combining a data output from a high-speed communications transmitter with a perturbation signal generated by automatic test equipment. The combined signal data signal including jitter and low voltage swings is input to the communications receiver port under test. The automatic test equipment determines the bit error rate of the parallel data output from the receiver port under test. This test method is appropriate for semiconductor devices with multiple transceiver ports.

Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

A method and apparatus for locating integrated circuit defects associated with different aspects of the integrated circuit industry. The integrated circuit is configured in a known failing mode, with a first power supply providing a constant voltage and variable current. Next, one or more additional dedicated power supplies are connected to various points of interest throughout the integrated circuit, wherein these dedicated power supplies have a preset current and the voltage is allowed to vary. The integrated circuit is then scanned with a laser beam, which induces current changes on in the integrated circuit especially in defective areas. These current changes then cause voltage changes on the dedicated power supplies. When such a voltage change occurs on the dedicated power supplies, its position is noted.

Embodiments of the invention include on-chip characterization of transistor degradation. In one embodiment, includes one or more functional blocks to perform one or more functions and an integrated on-chip characterization circuit to perform on-chip characterization of transistor degradation. The integrated on-chip characterization circuit includes a selectively enabled ring oscillator to generate a reference oscillating signal, a free-running ring oscillator to generate a free-running oscillating signal, and a comparison circuit coupled to the selectively enabled ring oscillator and the free-running ring oscillator. From the reference oscillating signal and the free-running oscillating signal, the comparison circuit determine a measure of transistor degradation.

A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error limit.

A method and a system for compensating for a permutation of L pairs of cable such that the compensation is localized in a trellis decoder of a receiver. The L pairs of cable correspond to L dimensions of a trellis code associated with the trellis decoder. The trellis code includes a plurality of code-subsets. The permutation of the L pairs of cable is determined. A plurality of sets of swap indicators based on the permutation of the L pairs of cable is generated. Each of the sets of swap indicators corresponds to one of the code-subsets. The code-subsets are remapped based on the corresponding sets of swap indicators.

A wireless integrated circuit test method and system is presented. The invention allows testing of one or more integrated circuits configured with a wireless interface and a test access mechanism which controls input of test data received over a wireless connection from a test station to test structures which test functional blocks on the integrated circuit. Via the wireless connection, multiple integrated circuits or similarly equipped devices under test can be tested simultaneously. The invention also enables concurrent testing of independently testable functional blocks on any given integrated circuit under test.

An integrated circuit tester produces an output TEST signal following a pulse of a reference CLOCK signal with a delay that is a sum of an inherent drive delay and an adjustable drive delay. The tester also samples an input RESPONSE signal following a pulse of the reference CLOCK signal with a delay that is a sum of an inherent compare delay and an adjustable compare delay. The inherent drive and compare signal path delays within an integrated circuit tester are measured by first connecting a salphasic plane to transmission lines that normally convey signals between the tester and terminals of an integrated circuit device under test. A standing wave signal appearing on that salphasic plane is phase locked to the CLOCK signal so that a zero crossing of the standing wave occurs at a fixed interval after each pulse of the CLOCK signal. Each transmission line concurrently conveys the standing wave to the tester to provide timing references for measuring the inherent drive and compare signal path delays within the tester. Transmission line signal paths are also measured. Delays are added to the drive and compare signal paths to compensate for the measured inherent drive, compare and transmission line delays.