747results about "Digital circuit testing" patented technology

This disclosure provides systems, methods, and devices for memory systems that support enhanced processing core scheduling schemes. In a first aspect, a system-on-a-chip (SoC) includes functional logic configured to perform one or more functions and self-testing logic configured to perform a self-testing operation on the functional logic. The SoC also includes a plurality of power domains, including a functional power domain coupled to the functional logic and configured to provide power to the functional logic and a self-testing power domain coupled to the self-testing logic and configured to provide power to the self-testing logic. The SoC further includes power control logic configured to control power delivery from the plurality of power domains to the functional logic and the self-testing logic and configured to power collapse the self-testing logic. Other aspects and features are also claimed and described.

A test system has ovens configured to hold devices under test (DUTs), DUT switches, each connected to the DUTs in an oven, splitters, each splitter connected to a DUT switch, an instrument switch connected to one output of each splitter, the other output of each splitter connected to a test instrument, and one or more processors to control the instrument switch to select one of the DUT switches connected to an oven, control the selected DUT switch to connect each DUT in the oven to a channel of the test and measurement instrument, use machine learning to tune the DUT to a set of parameters until the DUT passes or fails, repeat the connecting, tuning, and testing of each DUT until all DUTs in an oven have been tested, and repeat the selection and control of the DUT switches until each DUT in each oven has been tuned and tested.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

Disclosed is a test board which includes a substrate that includes a device under test (DUT) placement area where a first DUT and a second DUT are disposed, a first load switch connected in series with the first DUT and configured to be set to a switch on state or a switch off state based on a first enable signal, a second load switch connected in series with the second DUT and configured to be set to the switch on state or the switch off state depending on a second enable signal, and a test controller. The test controller may be configured to perform a test operation in a (1-1)-th mode by activating the first enable signal and deactivating the second enable signal and then perform the test operation in a (1-2)-th mode by deactivating the first enable signal and activating the second enable signal.

The invention provides a test vector construction method, which is used for constructing a test vector set required by a to-be-tested digital circuit, and comprises the following steps: S1, obtaining the to-be-tested digital circuit and a to-be-tested fault list corresponding to the to-be-tested digital circuit, the to-be-tested fault list comprising a plurality of circuit faults; s2, multiple rounds of simplification operation are executed until the number of circuit faults which can be detected by all the obtained test vectors is larger than or equal to a preset threshold value, all the test vectors obtained by each round of simplification operation are stored in a variable-capacity vector pool, the capacity of the vector pool corresponding to each round is a preset multiple of the capacity of the vector pool corresponding to the previous round, and the test vectors are stored in the variable-capacity vector pool; wherein each round of simplification operation comprises a static simplification stage and a dynamic simplification stage, the static simplification stage repeatedly fills a vector pool and reduces the number of test vectors in the vector pool, and the dynamic simplification stage fills a part of the uncertain items in the test vectors with the uncertain items obtained in the static simplification stage as 0 or 1.

Containerized orchestration of secure socket layer virtual private network benchmarking is disclosed. A test portal can accommodate developing test event information (TEI) based on test input information. Test input information can be used to generate event images, e.g., containers, that can be readily scaled, mutated, etc., via a containerization environment instance. One or more event image can be groups into a pod. An event image can be a new container, a previously used container, or a permutation of a container. Event image(s) can be retrieved from external sources, e.g., a library, a commercial vendor of event images, etc. TEI can be based on a pod(s) and communicated to a device-under-test (DUT). DUT performance can be measured, and results can be accessed by an entity, e.g., a test engineer, a results analysis engine, etc. Results can be employed to direct subsequent DUT testing.

An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serializer without utilizing a deserializer.

Systems and methods for direct-to-RF (radio frequency) software-defined radio implementation of an active load-pull system are provided. A system may include a controller, a primary field-programmable gate array (FPGA) to control and collect waveform data from vector signal analyzers (VSAs), each comprising an analog-to-digital converter (ADC) connected to an ADC signal-conditioning circuit to directly capture RF measurements of an input signal at an RF fundamental frequency of test and harmonics, each ADC signal-conditioning circuit altering a signal amplitude and isolating a wanted RF frequency of measurement at either the RF fundamental frequency of test or a harmonic to be received by its ADC, first and second couplers generating each input signal by extracting forward and reverse traveling waves at RF from input and output ports of a device under test (DUT), the VSAs capturing the input signals directly at the RF fundamental frequency of test or a harmonic.

A method for detecting non-convergence error in a transient circuit simulation wherein a circuit netlist and control statements associated with a circuit for the transient circuit simulation are received. A transient circuit simulation is performed responsive to a time point. Whether a non-convergence error has occurred during transient circuit simulation is determined. A transient debug mode is actuated responsive to determination of occurrence of the non-convergence error. The steps of performing the transient circuit simulation and determining whether a non-convergence error has occurred are repeated after actuation of the transient debug mode. Results of the transient circuit simulation are provided responsive to a determination of non-occurrence of a non-convergence error.

Systems and methods are provided for detecting bit errors and further processing bit error information. A method, according to one implementation, includes the step of receiving a binary test sequence pattern generated by a pattern generator at an input to a digital communications system under test, wherein the binary test sequence pattern includes a plurality of sub-patterns. The method also includes the step of receiving an output binary sequence from an output of the digital communications system. Also, the method includes comparing the binary test sequence pattern with the output binary sequence to detect bit errors. Based on correlation characteristics between the bit errors and each of the sub-patterns, the method also includes the step of determining whether the bit errors are caused by random factors or are caused by deterministic factors associated with the digital communications system.

The invention discloses a circuit board testing and quality screening automation method and system, and aims to solve the problems of low efficiency, insufficient precision and imperfect quality control of traditional circuit board testing. Precise positioning of the circuit board is achieved through the high-precision X / Y / Z three-dimensional positioning mechanical arm, parallel testing is conducted in combination with equipment such as a multi-channel oscilloscope, a signal source and a spectrum analyzer, and the testing efficiency is improved. Temperature and humidity control testing is carried out through the environment simulation bin, the thermal imager scans temperature distribution of the circuit board, a high-precision instrument is used for detecting signal integrity and analyzing electromagnetic compatibility, and the performance of the high-speed circuit board is ensured. A machine learning algorithm predicts potential faults, a test process is optimized, an automatic sorting system is adopted to separate qualified and unqualified circuit boards, and high consistency and high reliability of product quality are ensured. Through the automatic and intelligent testing process, the production efficiency, the quality control capability and the testing precision are greatly improved, and the labor cost and the production risk are reduced.

The density and power consumption of modern integrated circuits, such as Graphic Processing Units (GPUs), Central Processing Units (CPUs), and Network Processing Units (NPUs) is growing rapidly, which necessitates designing advanced cooling systems. Existing solutions for characterizing and validating these cooling system are inadequate. A flexible, scalable Thermal Test Vehicle (TTV) is disclosed which is based on an array of power transistors, measurement / control circuitry, and onboard computer. The TTV is configured for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

The invention discloses a digital circuit dependency analysis method, which comprises the following steps of: by analyzing the equality of a Boolean differential circuit, converting a dependency judgment problem of D on S into a problem of judging whether the Boolean differential circuit is constantly 0 or not; when whether the Boolean differential circuit is constantly 0 cannot be judged through X value simulation, logic negation is performed on the Boolean differential circuit, so that a dependency judgment problem is formally converted into a satisfiability problem, SAT solving is performed on the problem, whether D depends on S or not is judged according to a solving result, and if not, the Boolean differential circuit is judged to be zero. If the Boolean differential circuit is constrained, the satisfiability problem of the Boolean differential circuit is reconstructed, and the constrained Boolean differential circuit is subjected to SAT solution to further determine the dependency. According to the method, the digital circuit dependency analysis efficiency and accuracy are remarkably improved, the method is suitable for combinational logic circuit scenes of any scale and any complexity, the application range and efficiency of engineering application are greatly improved, and the method has remarkable industrial application value and popularization prospects.

Embodiments herein relate to testing chiplets during the manufacturing process. In one aspect, an on-chiplet interface is provided which allows testing of inter-chiplet communications of a chiplet on a package substrate without requiring the use of another chiplet. The interface communicates with an external Field-Programmable Gate Array (FPGA) on the package substrate at a reduced frequency compared to a frequency of the inter-chiplet communications. The FPGA can in turn communicate with a workstation to receive instructions and provide test results. The FPGA sends test pattern signals to, and evaluates corresponding responses from, circuitry of the chiplet which implements an inter-chiplet communication standard such as the Universal Chiplet Interconnect Express (UCIe) standard. In another aspect, the physical layer (PHY) circuits of two chiplet are tested with respective FPGAs.

An error rate measurement apparatus includes a display unit that displays a setting screen for setting a measurement condition of an error rate of an input signal from a DUT, and a processing unit that calculates a measurement time based on the measurement condition input to the setting screen, in which the setting screen includes a target confidence level input portion for inputting a target confidence level, a transmission rate input portion for inputting a transmission rate, a target error rate input portion for inputting a target error rate, an assumed-number-of-errors input portion for inputting an assumed number of errors during the measurement time, and a measurement time display portion for displaying the measurement time.

Technologies for a jitter injection generator and a spectrum hardware engine for measuring and assessing phase noise and a jitter transfer function are described. One communication device includes a timing and synchronization circuit that generates a signal with time-domain data, and a spectrum hardware engine that converts this data into frequency-domain data. The spectrum hardware engine has registers storing past outputs, multipliers for computing products using these values and a pre-computed coefficient, and a summation block for combining the current input with these products to get the current output. This output is sent to a computing device to estimate phase noise.

The invention discloses an automatic test method for a digital chip PWM module, and the method comprises the steps: enabling a plurality of PWM capture channels to be connected with a plurality of PWM output channels, and enabling the fault input channels of the PWM output channels to be connected with a general purpose input / output (GPIO); creating an output signal data frame, wherein the data frame records a channel number, a channel state, a period value, a pulse width value, an output channel frequency division value, an effective level and a fault level; a PWM channel is started for capturing, and the pulse width and the period of an output channel are captured; the method comprises the steps of setting a period value, a pulse width value and an output frequency division value of a PWM output channel, outputting a PWM signal with a set duty ratio, initializing a data frame, and recording a channel number, the period value, the pulse width value, the frequency division value, an effective level and a fault level of the current PWM output channel; when the PWM capture channel detects that the state of the PWM output channel is RUN, whether the capture pulse width and period are consistent with the output pulse width and period of the output channel is compared, and when the capture pulse width and period are consistent with the output pulse width and period of the output channel and the number of normal capture times reaches a set threshold value, the PWM output period and duty ratio test is completed.

An error rate measurement apparatus includes a provisional confidence level calculation unit that calculates a provisional confidence level CLx by using the sum x, an upper and lower limit value update unit that substitutes the sum x for the variable min_x in a case where the provisional confidence level CLx is equal to or lower than a target confidence level CLs, and substitutes the sum x for the variable max_x in a case where the provisional confidence level CLx is higher than the target confidence level CLs, and a measurement time calculation unit that calculates, in a case where changes in a value of the sum x calculated by the average value calculation unit are converged in a predetermined range, a value obtained by dividing the converged sum x by a product of a data rate and a target error rate ERs, as the measurement time.

Systems and methods for assessing display health in response to accidents are described. In some embodiments, an Information Handling System (IHS) may include an Embedded Controller (EC) and a memory coupled to the EC, where the memory comprises program instructions that, upon execution by the EC, cause the IHS to initiate an integrated display's Built-In-Self-Test (BIST) in response to a determination that the IHS suffered an accident.

A specific logic circuitry of a semiconductor Integrated Circuit (IC) is measured by a sensor. The sensor includes: a signal splitter that splits a signal from the specific logic circuitry into two test paths; a delay element that receives and applies a delay to a first test path, the delay based on a predetermined timing margin that is selected from a group of discrete timing margin values comprising a shortest timing margin value and at least one longer timing margin value; a comparison circuit that compares the delayed first test path and a second test path and provides a measurement output according to the comparison for an instance of measuring; and a controller that sets the predetermined timing margin such that, over the instances of measuring, a frequency of selection of the shortest timing margin value is higher than a frequency of selection of each longer timing margin value.

A signal driver system can include one or more force amplifiers configured to provide drive signals to an output node, such as a device under test (DUT) node. The system can include a first switch circuit coupled between a first force amplifier and the output node, and the first switch circuit can include multiple parallel instances of switch circuits with respective different resistance characteristics. The system can include a second switch circuit coupled between a second force amplifier and the output node. The system can include a control circuit configured to control the switch circuit instances of the first switch circuit to mitigate glitch at the output node, for example, when switching between the first and second drive signals.

The integrated circuit includes a delay monitor that monitors a delay of the data signal from the digital circuitry by generating a pulse having a width determined by the delay. In some embodiments, a delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal for clocking the data signal. The pulse generator generates a pulse according to the received data signal and the clock signal, wherein a width of the pulse is determined by a delay of the data signal relative to the clock signal. The event generator generates events that are temporally distributed with respect to the clock signal. As a result, the delay may be estimated based on an overlap between the event and the pulse.

A system 100 performs functional testing of a device 102 on a production line. The system comprises a self-testing protocol to conduct a functionality test on a plurality of components in the device a

A test system includes a test and measurement instrument, ovens to hold devices under test (DUT), each oven having an oven switch selectably connected to the DUTs, channel switches selectably connected to the oven switches and to one channel of the instrument, one or more processors to: select an oven and its oven switch, connect that oven switch to a subset of DUTs in that oven, connect the channel switches to that oven switch to receive signals from the subset of DUTs, send the signals to channels of the instrument to acquire waveforms from the subset of DUTs in parallel, and repeat connecting of the channel switches and that oven switch until the instrument has acquired waveforms from each DUT in that oven, use machine learning to tune each DUT, test whether each DUT in that oven is optimally tuned, and repeat until all DUTs have been tuned and tested.

The performance of an adaptive microelectronic circuit is at least partly configurable by selecting a value of an operating parameter. On processing paths, data inputs of register units are coupled to outputs of respective logic units for temporarily storing output values of said logic units. A plurality of timing event monitors respond to a digital value at a data input of a monitored register unit changing later than an allowable time limit by generating a timing event observation signal. The plurality of timing event monitors form a plurality of monitor groups, each monitor group being coupled to a branch of a triggering signal tree for coupling a monitor-group-specific triggering signal to the monitor group independently of other monitor groups. A control unit selectively allows or disables the propagation of the respective triggering signals into said branches of the triggering signal tree.

The invention is suitable for the technical field of semiconductor chip testing, and provides a digital signal data acquisition method and system based on chip testing, and the method comprises the steps: a semiconductor testing machine generates and issues a global trigger instruction at a time, and achieves the unified driving of multiple pins based on a digital signal sequence through a first trigger instruction facing a tested chip, starting sampling and digitization of corresponding electric signals by a second trigger instruction oriented to the data sending equipment, aggregating the electric signals according to a test session, and sending the aggregated electric signals to the data processing equipment; the data processing equipment carries out parallel calculation on the received digital signal sampling data and caches a result; and the semiconductor test machine obtains the instruction through the test result and carries out asynchronous backward reading. Therefore, control, acquisition and calculation are decoupled and can be propelled in an overlapped manner, serial waiting and instruction round-trip are reduced, the test time can be shortened, and throughput and resource utilization rate are improved.

A method of identifying error patterns during automated device testing comprises receiving a data pattern from a plurality of capture modules programmed on a programmable logic device, wherein the plurality of capture modules are programmable and operable to selectively capture data traffic to be monitored, and wherein the data traffic comprises a flow of traffic between a DUT and the programmable logic device. The method further comprises comparing the data pattern with known signatures in an error signature database. Also, the method comprises correlating the data pattern with one or more matching known signatures in the error signature database and assigning a score to each of the one or more matching known signatures in the error signature database based a level of correlation.

A monitoring apparatus for monitoring propagation delay of a signal along a path through an integrated circuit is disclosed. The monitoring device comprises a delay device configured to receive the signal and to generate a delayed signal, the delayed signal being a version of the received signal that is time delayed with respect to the received signal, a detection window device configured to generate a detection window signal based on a clock signal of the integrated circuit, and a determination device configured to determine the detection window signal based on the clock signal. The determination means is configured to determine whether a value of the received signal differs from a value of the delayed signal during a time defined by the detection window signal, and to generate a determination signal based on the determination.

A probe card includes a plurality of power lines that are electrically connected to the plurality of DUTs, a plurality of ground lines that are electrically connected to the plurality of DUTs and to each other, and a plurality of power compensation circuits that are electrically connected to respective ones of the plurality of power lines and respective ones of the plurality of ground lines, where the plurality of power compensation circuits are configured to generate and provide a plurality of compensated power supply voltages to the respective ones of the plurality of power lines, and where the plurality of compensated power supply voltages are configured to inhibit a variation of a ground voltage of the respective ones of the plurality of ground lines.

A method for Design For Test (DFT) for Source Synchronous Interfaces (SSI) includes shifting a test vector into a master register slice with a DFT clock. A functional clock is generated. The test vector and the functional clock are launched from a first SSI of the master register slice. The test vector and the functional clock are captured with a second SSI of a slave. The test vector is shifted out of the slave with the DFT clock.