57 results about "Field programmable logic" patented technology

The invention discloses an underwater magnetic field measuring device based on a diamond NV color center. The underwater magnetic field measuring device comprises a diamond NV color center module, an incident laser excitation module, a multi-path optical coupling module, a microwave excitation module, a fluorescence acquisition and photoelectric conversion module, a signal processing and control module and a magnetic field module, the multi-path optical coupling module is used for dividing an optical fiber into multiple paths and collecting fluorescence generated by the diamond block; the microwave excitation module is used for switching between two single-quantum resonance frequencies to drive an NV color center to realize double-quantum DQ reading; and the signal processing and control module comprises an FPGA (Field Programmable Gate Array) processing unit of a field programmable logic array chip. According to the invention, a dual-quantum DQ working point of a diamond NV color center is used as a measurement channel, common-mode influence of D is removed through differential measurement, the problem of D drift caused by temperature drift, stress and material aging is physically and obviously inhibited, and the device can still realize ultrahigh-sensitivity measurement in a complex underwater environment.

The invention discloses a data processing method of an integrated backboard and electronic equipment, and relates to the technical field of computer storage systems, and the method comprises the following steps: receiving a data processing request issued by a host through a field programmable logic gate array onboard a backboard, and obtaining to-be-processed data in a target solid state disk based on the data processing request, the method comprises the following steps of: firstly, carrying out streaming operation on to-be-processed data based on a field programmable logic gate array to obtain processed data, and finally, sending the processed data to a host from a target bus through the field programmable logic gate array based on a preset routing strategy, namely, replacing the host with the field programmable logic gate array to carry out a data processing task. Therefore, the host load is obviously reduced, the performance is improved, and the problems of high load, performance bottleneck, low efficiency, high delay and the like caused by centralized data processing of hosts in related technologies are solved at least.

The invention provides a novel driving circuit for a heterogeneous hybrid device, and the circuit comprises an upper computer, a field programmable gate array, a SiC MOSFET driving voltage control module, a Si IGBT driving voltage control module, a power module, a first driving positive voltage generation circuit, and a first driving negative voltage generation circuit. The system comprises a first driving positive voltage generation circuit, a first driving negative voltage generation circuit, a second driving positive voltage generation circuit, a second driving negative voltage generation circuit, a switch time sequence switching module, a SiC MOSFET driving chip, a Si IGBT driving chip, a SiC MOSFET switching tube and a Si IGBT switching tube. The novel driving circuit for the heterogeneous hybrid device provided by the invention has the functions of switching multiple switch time sequences and switching multi-stage driving voltage, and can meet the requirements in different application scenes.

The invention relates to a tone mapping method and device, electronic equipment and a storage medium. According to the method, a first logical operation unit, a second logical operation unit, a third logical operation unit and a lookup table of a field programmable logic gate array are matched with one another. Specifically, by inputting the Y channel median value into the lookup table, the Y channel value adjustment coefficient can be directly obtained, and exponential operation between the Y channel median value and the Y channel value adjustment coefficient does not need to be carried out. By inputting the ratio of the Y channel value of each pixel stretched to the full domain to the median value of the Y channel of each pixel stretched to the full domain into the lookup table, the compression value of the Y channel can be directly obtained, and exponential operation of the ratio and the compression value of the Y channel is not needed, so that the data processing efficiency is improved, and the operation resources are saved.

The disclosure provides a point cloud monitoring method, device and equipment, relates to the technical field of image processing, specifically to the technical field of point cloud processing, and can be applied to an automatic driving scene. A specific embodiment of the method comprises the following steps: acquiring point cloud data collected by a laser radar to a field programmable logic gate array (FPGA); acquiring configuration parameters of a first monitoring item configured by an advanced reduced instruction set machine (ARM) to the FPGA; and processing the point cloud data using the configuration parameters on the FPGA to obtain a monitoring result of the first monitoring item. The embodiment is suitable for monitoring more point cloud data and can obtain a good monitoring result.

The invention relates to a digital demodulation method for a mining wireless electromagnetic wave scenograph, belongs to the technical field of mining electromagnetic wave detection, and aims at solving the problems that an existing scenograph depends on an analog filtering and rectifying circuit, so that the circuit is complex, and the reliability is poor. According to the method, after a receiver receives and amplifies an electromagnetic wave signal, the electromagnetic wave signal is sampled by an analog-to-digital conversion module, a field programmable logic gate array performs fast Fourier transform on a digital signal, and an amplitude corresponding to a transmitting frequency is extracted as an effective signal, so that digital demodulation is realized. Filtering and rectifying circuits do not need to be simulated, the circuit structure can be remarkably simplified, the reliability and the real-time performance of an instrument are improved, and the stable detection requirement in the mine environment is met.

The application discloses a multiplexing measurement and control method and device of a three-axis micromechanical gyroscope, which comprises the following steps: firstly, a global clock is generated; in the working clock of any gyroscope, an alternating current driving signal, a feedback force signal, a preset reference phase signal and a reference displacement signal are outputted to the gyroscope by a coordinate rotation digital computer, and the gyroscope reaches a force balance state through a driving modal control loop and a detection modal control loop, and the angular velocity of the gyroscope is obtained; the three gyroscopes multiplex the same coordinate rotation digital computer in the respective working clock. The application combines time division multiplexing with a coordinate rotation digital computer algorithm, and can accurately and synchronously detect and close-loop control the three-axis micromechanical gyroscope in real time in limited field programmable logic gate array resources. The method and device can be widely applied to concurrent processing requirements of multi-axis or multi-path high-speed, high-precision and high-integration measurement and control instruments.

The utility model relates to a universal protocol processing board and system. The universal protocol processing board comprises a carrier board and a plurality of core boards, the core board comprises a central processing unit, and the carrier board comprises a field programmable logic gate array and a plurality of inter-board communication components; the central processing unit of each core board is connected with the field programmable logic gate array through an inter-board communication assembly; the field programmable logic gate array is at least used for forwarding a preset number of to-be-processed signals to each central processing unit through the inter-board communication component; and the central processor is at least used for performing protocol conversion on the received to-be-processed signal. Thus, the central processing unit of each core board is connected with the field programmable logic gate array through the inter-board communication assembly, the field programmable logic gate array can be used for signal forwarding, it is guaranteed that the multiple central processing units process related tasks in parallel, and then the processing efficiency of the general protocol processing board is effectively improved.

The application provides a time correction method and system for inter-crystal scattering events of a PET detector based on SiPM, and the application instantiates multiple time-to-digital converters in a field programmable logic gate array device, performs pulse width measurement on the electrical signals output by each SiPM detector, since the pulse width is positively correlated with the energy of the signal, the non-inter-crystal scattering events and the inter-crystal scattering events can be determined by the pulse width, and the position of the inter-crystal scattering events is determined to reduce the position selection error. During the correction, firstly, the non-inter-crystal scattering events are generally corrected, then further, the time difference between the inter-crystal scattering events occurring in each crystal and the non-inter-crystal scattering events on the response line is counted offline, the additional time difference of each inter-crystal scattering event caused by the time walk effect is obtained, and then the inter-crystal scattering events are secondarily corrected in time online, so that the time resolution of the system is improved.

The application belongs to the technical field of signal processing, and specifically discloses an anti-deception interference method and system based on dynamic weight and timing constraints, wherein the method comprises the following steps: using a field programmable logic gate array to perform hardware-level real-time preprocessing on synthetic aperture radar original echo data, and triggering hardware-level adaptive routing truncation according to an amplitude distortion gradient, and outputting preprocessed data after algorithm power deployment; based on the preprocessed data, multi-modal features are extracted in parallel, and the multi-modal features comprise image domain incoherent topology features, local phase dispersion degree features and spatial geometric constraint features; the application aims to solve the problems of single feature source representation, poor environmental adaptability of fusion mechanism, not using deception interference timing physical contradictions and large model calculation overhead in existing synthetic aperture radar anti-interference schemes, which leads to limited real-time performance.

The application relates to the technical field of equipment motion control, and discloses a proton treatment rotating gantry motion control method, system, equipment and medium, the method comprises the following steps: in response to a gantry motion intention, performing pre-checking on a field programmable logic controller before motion, collecting a plurality of discrete input quantities and absolute angle feedback, and generating a safety snapshot; if the safety snapshot meets a motion prohibition condition, the motion is rejected and the reason is output; if the prohibition condition is not triggered, a target gantry angle and a speed given value are written to the PLC, and an ascending edge pulse is applied to a position starting coil to trigger the motion. It is determined whether the gantry is in place, after the gantry is in place, a standardized gantry public interlocking signal set is output to a treatment control layer, and the gantry is controlled to enter a stable standby state, and the treatment control layer calculates a proton beam emission permission based on the interlocking signal set. Through the safety snapshot pre-checking, mixed angle determination and standardized interlocking output, the motion control safety and positioning accuracy of the gantry are improved.

The application discloses a startup method, a shutdown method, a logic device, a server and a readable storage medium. The logic device is located in the server, and the logic device is in communication connection with a field programmable gate array of the server. After the server is powered on, the logic device is triggered to reload firmware. After the reloading of the firmware is completed, standby components of the server are powered on, and the state of the standby components is monitored. After the field programmable gate array is monitored to start, level information is transmitted to the field programmable gate array. After standby timing control is completed, in the case that a startup signal is received, power-on timing interaction is performed with the field programmable gate array, and a processor is subjected to startup processing. The application has the technical effect that only standby timing and power-on timing of the logic device and the field programmable logic gate array are needed to realize startup action, the decoupling of server startup and shutdown and the baseboard management controller is realized, and therefore the server startup and shutdown are accelerated.

The application provides a request processing method and device, a storage medium and a program product, relates to the technical field of communication, and solves the technical problem of poor flexibility of communication processing request processing in the related art. The method comprises the following steps: receiving a function request; the function request is used for requesting a physical layer function service; based on the type of the function request, the function request is processed based on a target unit; the target unit comprises one of the following: the baseband unit and the radio frequency remote unit; the baseband unit comprises one of the following: the field programmable logic gate array chip and the central processing unit.

The invention discloses a control system for a high-capacity test, which is characterized in that a test debugging system control computer PC1 is sequentially connected with a central programmable logic controller PLC1 and test field programmable logic controllers PLC2... PLCn through optical fibers, and the test field programmable logic controllers PLC2... PLCn are respectively connected with test field equipment through cables; the test process system control computer PC2 is connected with the time sequence host SX through an optical fiber, the time sequence host SX is connected with the power amplifier cabinet GF through an optical fiber, and the power amplifier cabinet GF is respectively connected with the test field equipment through a cable; the emergency stop switch AN1 is connected with the electromagnetic switch DC through a cable, the electromagnetic switch DC is connected with the travel switch XC through a live-line work insulation rope, and the travel switch XC is connected with the test site switch. And the optical fiber and the live working insulating rope are insulators, so that high voltage is prevented from being introduced into an operation table when equipment on a test site fails, and the safety of test operators is ensured.

The invention relates to a digitally-controlled quadrature modulation laser single side band frequency shift and phase locking device and method, a field programmable logic gate array of the device is connected with four digital-to-analog converters, every two digital-to-analog converters are connected with a quadrature modulator, the two quadrature modulators are also connected to an optical quadrature modulator, and the optical quadrature modulator is connected with the four digital-to-analog converters. The output of the laser source realizes single side band frequency shift through an optical quadrature modulator, part of optical signals are converted into electric signals through a third beam splitter, and parameters of the optical modulator are adjusted in real time through a voltage control port. And the other path of laser is interfered with the frequency-shifted optical signal in the beam combiner through the first beam splitter, demodulated by the orthogonal down-conversion mixer, fed back with phase information, and transmitted back to the field programmable logic gate array through the three-channel analog-to-digital converter to form closed-loop control. According to the invention, the influence of sideband signals generated by adjustment is reduced; moreover, the frequency shift bandwidth can be higher, the influence of a spatial light path is reduced, and the stability is improved.

The present disclosure relates to a task processing method and device based on heterogeneous chips, a storage medium, and an electronic device, and relates to the field of computer technology. The method includes: preprocessing original data to be processed to obtain data processing tasks and task categories included in the original data to be processed; controlling task processing units to execute data processing tasks and obtain task processing results; calculating current parameter values ​​of field programmable logic gate arrays based on the task processing time and current load data of the field programmable logic gate arrays included in the task processing results; determining the current operating state of the field programmable logic gate array based on the current parameter values, and adjusting the operating frequency of the field programmable logic gate array and / or the number of task processing units based on the current operating state and a preset task execution strategy. The present disclosure improves the processing efficiency of data processing tasks.

The application relates to a method for solving a Spearman simple correlation coefficient, which comprises the following steps: a field programmable logic gate array operation circuit is used to realize fast solving of the Spearman simple correlation coefficient; a fast version of the Spearman simple correlation coefficient is obtained by simplifying the Spearman simple correlation coefficient, so that field programmable logic gate array operation hardware circuit designed based on the Spearman simple correlation coefficient can be simplified, and the operation speed is accelerated; and the Spearman simple correlation coefficient is solved based on a parallel computing mode of the field programmable logic gate array, so that the calculation time can be further shortened, and the purpose of solving the Spearman simple correlation coefficient in real time and quickly is achieved.

The utility model discloses a robot motion controller and a robot system.The robot motion controller comprises a main control unit and a field programmable logic gate array which are electrically connected, and the main control unit is used for controlling operation of the field programmable logic gate array; the field programmable logic gate array comprises an input and output interface and a safety detection circuit, the input and output interface is used for receiving an external safety signal, and the safety detection circuit is used for processing safety logic in the operation process of the robot according to the safety signal and sending a processing result to the main control unit. According to the design, the size of the robot motion controller can be simplified, and the function of the robot motion controller is ensured.

The invention discloses a gated clock conversion method and device, electronic equipment and a storage medium, and relates to the field of chip development and chip test.The method comprises the steps that each gated clock unit in electronic circuit design is obtained, and each gated clock unit is configured in each field programmable logic gate array; obtaining a truth table of each gated clock unit according to the logic expression of each gated clock unit, and splitting the truth table into different sub-truth tables according to the clock signal value to obtain a target sub-truth table with an inconstant output result; and obtaining a sub-logic expression after the clock signal is deleted according to the target sub-truth table, and obtaining an enable signal of the sequential logic device according to the sub-logic expression. According to the technical scheme provided by the embodiment of the invention, not only is the conversion duration of the gated clock shortened and the logic comprehensive performance of the electronic circuit design greatly improved, but also the conversion complexity of the gated clock is reduced.

The present invention discloses an electric injection encoding device and method based on a two-segment semiconductor laser. The device comprises: a laser comprising a gain region and an absorption region, and performing frequency encoding or spatiotemporal encoding according to a gain region signal and / or an absorption region signal; a controller for controlling the temperature of the laser; a current source for outputting a current signal; a field programmable logic gate array for providing a signal to be encoded to the gain region; a bias device for loading the current signal and the electric signal to be encoded to the gain region; a voltage source for providing a voltage signal; a field programmable logic gate array for providing a signal to be encoded to the absorption region; a bias device for loading the voltage signal and the signal to be encoded to the absorber region; an optical isolator connected to the laser and an adjustable optical attenuator; the adjustable optical attenuator connected to a spectrometer; an optical coupler for dividing the encoded optical signal into two light paths; a photodetector for converting one light path into an electrical signal; an oscilloscope for measuring the electrical signal; and a spectrometer for measuring the other light path.

The embodiment of the present application discloses a field programmable logic gate array circuit, a data processing method and a circuit design method. The field programmable logic gate array circuit comprises a communication interface, at least one function module, the function module comprises a plurality of function operator modules and a switching matrix module, the switching matrix module comprises a plurality of switching matrices, the function operator module is connected with the switching matrix, wherein one or more switching matrices are connected between any two function operator modules; and the communication interface is directly or indirectly connected with at least part of the switching matrices. The present application can avoid re-designing the complete flow of the FPGA, and improve the flexibility of the FPGA.

The invention relates to an intelligent robot using a flexible field programmable logic controller, and relates to the technical field of intelligent welding systems, and the intelligent robot comprises a data acquisition module which is used for acquiring an image of a vehicle body part fixed at a welding processing position; the flexible field programmable logic controller is used for determining path deviation data based on the images of the vehicle body parts and the welding detection paths corresponding to the vehicle body parts and judging whether path adjustment is carried out or not based on the path deviation data, and if yes, a real-time welding path is generated based on the images of the vehicle body parts and a preset welding path; the vehicle body welding module is used for welding vehicle body parts; the welding seam detection module is used for determining welding seam detection light source parameters and collecting welding seam images based on welding parameters in the welding process and the materials of the automobile body parts; and the flexible field programmable logic controller is also used for detecting the welding quality based on the welding seam image. The welding quality of the vehicle body parts is improved.

The embodiment of the invention provides a field programmable logic gate array and a pressure testing method, and the field programmable logic gate array comprises an internal memory and a network card, a segment is arranged in the internal memory, and the segment is used for storing a data packet used in a pressure test process; the data packet is stored in the segment; in a pressure test, the network card interacts with the processor through the segment. The technical scheme provided by the invention is used for solving the problem of low precision of the existing pressure test.

The application discloses a kind of adaptive error compensation circuit and method based on multi-ring resonator gyroscopes. Including multi-ring resonator gyroscopes, detection electrode, feedback control electrode, improved T-type resistance-capacitance charge amplification filter circuit, ADC analog-digital conversion circuit, field programmable logic gate array, digital signal processing circuit, DAC digital-analog conversion circuit, signal feedback control circuit;Improved T-type resistance-capacitance charge amplification filter circuit is used instead of traditional annular diode amplification filter circuit, improved proportional-integral resonant controller is used instead of traditional proportional-integral controller, more reasonable control error is inhibited, and system control precision is improved.The circuit structure has the characteristics of strong adaptability, good stability, high accuracy, high precision, small size, easy integration, etc., and can be widely applied.

The application provides a high-performance servo driver and a control method, which are applied to the technical field of high-performance servo driver control and include that a servo control loop module is arranged in a digital signal processor, and an AI learning algorithm module is arranged in a field programmable logic array; the AI learning algorithm module: based on operation parameters generated by a servo system where the high-performance servo driver is located, the AI learning algorithm is trained and learned to obtain a characteristic model and an output compensation current component; the servo control loop module: used for performing vibration suppression on the servo system according to the compensation current component. Compared with the prior art, the application can effectively suppress vibrations of arbitrary amplitudes, vibrations of arbitrary time lengths and vibrations caused by arbitrary factors through vibration suppression of the compensation current component; the vibration suppression is performed at the cycle pace of a current loop, so that there is no delay or the delay can be completely ignored relative to a mechanical system, and high-speed or super-high-speed operation occasions can be completely adapted.

1. The name of the design product: field programmable logic gate array security protector shell. 2. The use of the design product: the design product is used to protect field programmable logic gate arrays in the fields of communication, electronics, video signal processing, aerospace, etc. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view 1.

The present invention discloses a field programmable logic gate array (FPGA), which includes a plurality of programmable unit blocks arranged in rows and columns to form an array, and a wiring network including segmented routing and direct routing. The connection block is configured to fan in the segmented routing and direct routing from four cardinal directions, receive fan-in signals, and couple to the programmable block; the switch block is configured to drive and send fan-out signals to the segmented routing; one of the segmented routings in each cardinal direction is directly connected to the switch block via a dedicated circuit to drive long-distance outputs in the four cardinal directions, thereby allowing fan-out signals to be sent to each cardinal direction, including the fan-in direction that receives fan-in signals. The field programmable logic gate array provided by the present invention has a field programmable logic gate array wiring architecture that can minimize die size and more efficiently utilize wiring network resources. The wiring architecture can improve the power efficiency of the wiring network structure without affecting routability.

The present application relates to the technical field of double optical comb spectrum, and specifically discloses a passive suppression method for relative carrier envelope phase noise in a double optical comb spectrum system, which comprises the following steps: constructing a hardware optical path, generating a double optical comb signal through a common pump unit and a differential dispersion compensation unit, and performing phase matching at a physical level by using a passive optical delay matching unit; inputting the double optical comb signal into a field programmable logic gate array core of a customized system-level chip, executing synchronous acquisition and passive suppression processing of phase noise of the double optical comb signal, and obtaining a suppressed signal. In the actual industrial field measurement process, the present application first completes the basic phase constraint of the double optical comb signal at the physical level through common pumping and optical delay matching, then directly uses the field programmable logic gate array core inside the system-level chip to perform real-time passive noise suppression, and seamlessly hands over to the neural network processor core to execute multi-spectrum interference elimination.

The present application provides a method for data transmission control across field programmable logic gate arrays and related devices. The method includes: using a first register device to latch a set of data from a first field programmable logic gate array according to a first clock, wherein the set of data is sorted according to data load and pointer signal attributes and divided into multiple sets of local data; using a time division multiplexing interface to sequentially transmit the multiple sets of local data from the first register device to a second register device at multiple time points according to a time division multiplexing clock; and using the second register device to sequentially receive the multiple sets of local data to output the set of data to a second field programmable logic gate array, wherein the second field programmable logic gate array operates according to a second clock different from the first clock.

The application discloses a video signal generator supporting multiple protocol outputs and timing programming, comprising a power module, a clock module, an optical fiber data receiving module, a cache management module and a multiple protocol video and timing generation module. The application takes a field programmable logic gate array as a core architecture, solves the problems of single protocol and non-self-defined video timing of a traditional video signal generator, has the ability of multiple channel independent and synchronous output and non-standard timing video generation, and can provide required signal sources for development and test of various video display devices.