293 results about "Field programmable logic" patented technology

Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration memory cells, and so forth. Embodiments describe circuits and methods for implementing multiple supplies as sources of V_dd, multiple voltage thresholding V_t, signal level translators, and power gating of circuitry to deactivate portions of the circuit which are inactive. The supply voltage levels can be fixed, or programmable. Methods are described for performing circuit CAD in the routing and assignment process on FPGAs, in particular for optimizing FPGA use having the power reduction circuits taught. Routing methods describe utilizing slack timing, power sensitivity, trace-based simulations, and other techniques to optimize circuit utilization on a multi V_dd FPGA.

The invention discloses a configuration, refreshing and program upgrading integrated system for an SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array), belongs to the technical field of aerospace and aims to solve the problem of SEU (Single Event Upset) of the SRAM type FPGA in a spatial irradiation environment. The configuration, refreshing and program upgrading integrated system has a capability of performing program upgrading on the SRAM type FPGA which is in on-orbit work for a long time. The configuration, refreshing and program upgrading integrated system comprises an on-site programmable logic gate array SRAM type FPGA, a comprehensive management anti-fuse FPGA, a configuration program storage chip PROM (Programmable Read-Only Memory), an on-orbit upgrading program storage chip EEPORM (Electrically-Erasable Programmable Read-Only Memory) and an RS422 interface chip. The configuration, refreshing and program upgrading integrated system disclosed by the invention can be used for effectively solving the problem of the SEU of the SRAM type FPGA which is in on-orbit work for a long time and correcting the SEU and single event accumulation inside the SRAM type FPGA without being shut down, also has the function of on-orbit program upgrading of the SRAM type FPGA, and has the characteristics of instantaneity, reliability, flexibility, universality and low cost.

The invention discloses a convolutional neural network IP core based on FPGA, and aims to realize operation acceleration of a convolutional neural network on an FPGA. According to the basic model of the convolutional neural network, the specific architecture of the convolutional neural network comprises a convolution operation IP core, a pooling operation IP core, a full connection operation IP core, a bubbling method convolution layer, a bubbling method pooling layer, a full connection layer, a feature map storage module and a parameter storage module. The IP cores support construction of convolutional neural networks of different scales, and the IP cores of different types and numbers are instantiated according to the required network model. Different neural network layers are constructed by instantiating the IP core, and the parallelism of the FPGA is fully utilized to realize the operation acceleration of the convolutional neural network; and designing an IP core through a VerilogHDL language to realize transplantation of different FPGAs. The operation speed and efficiency of the convolutional neural network are greatly improved, and the processing power consumption of the convolutional neural network is reduced.

The invention relates to a configurable frequency synthesis circuit based on a delay locked loop. The circuit comprises the delay locked loop, a frequency synthesizer and a configuring SRAM, wherein, the delay locked loop consists of a phase discriminator, a controller and a variable delay chain; and the frequency synthesizer consists of a frequency doubling synthesizer and a frequency division synthesizer. The phase discriminator receives a reference clock and a feedback clock and outputs comparison signals and locking signals after phase demodulation comparison; the comparison signals and the locking signals are processed by the controller, and the controller outputs control voltage then in order to enable the variable delay chain to generate N phase clocks that are output to the frequency synthesizer; and the frequency doubling synthesizer and the frequency division synthesizer enable the set/reset time of a R/S trigger in the frequency doubling synthesizer to generate frequency doubling clock signals under the control of the configuring SRAM, and lead the set/reset time of the R/S trigger in the frequency division synthesizer to generate frequency division clock signals. The configurable frequency synthesis circuit has simple circuit organization, flexibly changes a frequency synthesis coefficient by changing the code flow value in the embedded configuring SRAM so as to obtain a frequency division coefficient and a frequency doubling coefficient as required, and can be applied to a field programmable logic array.

Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will provide an indication of the stored data at this location in the memory array within the EEPROM or will act as the absence of a transistor at this location in the logic array within the FPLA. The memory array or the logic array includes densely packed cells, each cell having a semiconductor pillar providing shared source and drain regions for two vertical body transistors that have control gates overlaying floating gates distributed on opposing sides of the semiconductor pillar. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data or to represent a logic function, an area of only 2F2 is needed per respective bit of data or bit of logic, where F is the minimum lithographic feature size.

An exceptionally effective SoC design is achieved by the user of wrappers that comprise a functionally reconfigurable module (FRM) that is capable of affecting the operational functionality of the wrapper and that, consequently, is capable of affecting the operational functionality of a designed SoC. One embodiment of a core+wrapper combination comprises distinct input and output cells within the wrapper, and a separate FRM. Another embodiment may embed the input and output cells within the FRM. The FRM may be implemented with, for example, a field programmable logic array (FPLA). An additional advance is realized by providing a number of spare leads in the signal paths network that interconnects the various SoC elements.

The invention relates to the technical field of communication and discloses a board system, aiming at solving the problems that an FPGA (Field Programmable Logic Array) online update mode is inapplicable for the FPGA online update of a separated type system of a motherboard plus multiple communication interface cards in the prior art, and the update mode is high in cost and low in reliability. The system comprises a motherboard and n interface cards, wherein the motherboard comprises a CPU (Center Processing Unit), a CPLD (Complex Programmable Logic Device) unit and n slot positions; each slot position is connected with the CPLD unit; the CPLD unit is connected with the CPU; the n interface cards are connected onto the n slot positions in a plugging and one-to-one correspondence way through n connectors so as to realize signal interconnection with the motherboard; as an integer, n is greater than or equal to 2; the CPLD unit comprises a gating module and a counting module; the interface cards comprise an FPGA unit, a selector switch, a main flash module and a slave flash module; the main flash module and the slave flash module are connected with the FPGA unit through the selector switch. In addition, the invention also discloses an FPGA online update method of the communication interface cards, which is applicable for the separated type system of the motherboard plus the multiple interface cards.

This invention relates to a measuring method and device of impulse form. The invention includes one constant proportion timing discriminate module and one time-to-digital conversion module. Data of time-to-digital conversion modular enter calculator for handling. Constant proportion timing discriminate module has a group of leading edge discriminator and a group of back edge discriminator, which separately discriminate a series of points where the ratio of pulse front edge and back edge voltage and spike voltage are certain worth corresponding time. multipass time-to-digital conversion module convert time interval between first time and subsequently time to digital quantity, adopt digital counting method and combine digital delay line bracketing method, realize at a piece of field programmable logic array FPGA. sending obtained data into computer for calculation to gain time interval, base on voltage peak ratio of every time to indirectly reduce impulse form, and obtain pulsewidth. The invention has low cost, small bulk, and light weight, can apply to laser range finder.

The invention belongs to the field of blood vessel endoscopic imaging and discloses a device and method for endovascular optical coherence tomography - opto-acoustic - ultrasonic multimode imaging. The device comprises a computer, an optical coherence tomography (OCT) excitation and collection system, an opto-acoustic signal excitation and collection system, an ultrasonic signal excitation and collection system and an integrated probe. The OCT excitation and collection system comprises a field programmable logic array (PFGA) panel, a superluminescent diode, an isolator, a first optical fiber coupler, a reference arm, a linear array charge coupled device (CCD) and a first collecting card. The opto-acoustic signal excitation and collection system comprises a pulsed laser, a diaphragm, a second optical fiber coupler and a doubly clad optical fiber. The ultrasonic signal excitation and collection system comprises a pulse ultrasonic emitter/receiver, a signal amplifier, a signal filter and a second collecting card. The OCT, opto-acoustic and ultrasonic tri-modal blood vessel endoscopic imaging system integrates three imaging modes and respective advantages thereof, and multi-parameter physiological function information and multiscale structural information of a blood vessel can be obtained.

A method and a device for repairing single event upset in a field programmable logic gate array are disclosed, a high-reliability monitoring unit, which is connected with the field programmable logic gate array and used for realizing the detection and the repair of the single event upset, is set; a read-back process of a configuration memory of the field programmable logic gate array is implemented by the high-reliability monitoring unit in order to read configuration frames of the field programmable logic gate array, and original configuration frames, which are read from a non-volatile memory via a standard NVRAM interface, are then implemented by the high-reliability monitoring unit; the high-reliability monitoring unit compares the read-back configuration frames with the original configuration frames by bytes, when comparison error occurs on the configuration frames, it is judged that the single event upset in the configuration memory of the field programmable logic gate array occurs, and the high-reliability monitoring unit executes a repair process to repair the incorrect configuration frames of the field programmable logic gate array. The invention has the advantages of simple structural principal, convenient operation, high reliability and good stability.

The invention discloses a reliable time scale pulse measurement method, which comprises the following steps: 1) converting a 10MHz frequency signal of a precise clock source, a standard 1PPS signal and 1PPS, 1PPM and 1PPH signals to be measured to pulse signals; 2) carrying out frequency doubling on the 10MHz frequency signal of the precise clock source for obtaining a 100MHz frequency signal, and taking the 100MHz frequency signal as the working frequency of an FPGA; simultaneously carrying out frequency division on the standard 1PPS signal and respectively obtaining a 1PPM reference signal and a 1PPH reference signal; and 3) measuring the precision of the 1PPS, the 1PPM and the 1PPH signals to be measured according to the reference signals of 1PPS, 1PPM and 1PPH under the working frequency of 100MHz. The method can realize the high-speed and high-efficient counting operation by adopting a field programmable logic sequence, realize the multi-path and multi-group pulse fast detection, and send the detection result to a user and is characterized by stable performances and convenient maintenance.

The invention belongs to programmable component structure technology field, specially a local programmable logic array wiring resource structure and modeling method which supports the crutch line. The wiring resource structure of the invention includes: programmable interconnected line, uniform switch matrix, input and output multi path selector array and logic unit. It breaks the limit of level and uprightness interlinkage resource, introduces the concept of crutch line, makes the wiring path not pass the programmable switch, it gives attention to speed and agility. The description of wiring line resource, the interconnected line is distributed to the repeated unit then integral interconnected resource is described by describing an interconnected line resource in a repeated unit. This describing method is very flexible, the kind, amount, proportion of interconnected resource can be changed conveniently, and any switch array can be generated.

The invention provides an all-digital closed-loop system of a Coriolis mass flowmeter (CMF). A hardware circuit is based on digital components to achieve the stable closed-loop control of the CMF, particularly, the digital signal processing circuit is mainly based on a field programmable gate array (FPGA), and a digital signal processing method is used in the FPGA to achieve the digital closed-loop control algorithm for the CMF and track the frequency on a real-time basis; by using the non-linear amplitude control method and introducing FIFO (first in, first out) components to the phase control, stable and accurate control can be achieved on the amplitude and phase; by better tracking the changes in the vibration of the measuring tube of the CMF to obtain vibration pickup signals reflecting the information of fluid more accurately and further output the vibration pickup signals at a stable amplitude, the invention is favorable for resolving a secondary meter, further improving the accuracy and stability in the measurement of the CMF and ensuring that the resource consumption and operation load are lower; and the invention further solves the problem of two-phase flow, particularly, when the CMF undergoes the problem of two-phase flow, the sinusoidal signal at the controllable amplitude and at the same frequency as the natural frequency of the measuring tubes of the CMF can be actively outputted to force the measuring tubes of the CMF to continue vibrating, thus ensuring the non-stop vibration and non-interrupted measurement when the CMF undergoes the problem of two-phase flow and enabling the CMF to carry out the flow measurement when undergoing the problem of the two-phase flow.

The invention relates to a Brillouin optical-time-domain analyzer based on a coherence dual-pulse pair sequence technology and a method for restraining common-mode noise by utilizing the same, belongs to the field of optics, and solves the problems that a traditional Brillouin optical-time-domain analyzer is low in spatial resolution, long in measuring signal time and low in signal-to-noise ratio. A laser is adopted, an upper branch of light divided by an optical-fiber coupler I is used as pump light, pulse pairs with different pulse widths can be periodically generated by a field-programmable logic array in a programming manner, and the pulse pairs are continuously and optically modulated to form a coherence pulse pair sequence through a photoelectric modulator; a lower branch provides detection light, the detection light enters a photoelectric modulator after a polarization state is adjusted, upper marginal frequency light and lower marginal frequency light which having the frequency difference of Brillouin frequency shifting gamma B are generated on the basis of carrier light, the pump light consisting of the coherence pulse pair sequence and the modulated detection light has a Brillouin scattering phenomenon in a sensing optical fiber, and two Brillouin signals are detected by a photoelectric detector. The Brillouin optical-time-domain analyzer and the method are suitable for restraining the common-mode noise.

Methods for monitoring and improving the fabrication process of integrated circuits using configurable devices are described. In one aspect, the method includes instantiating a test pattern on one or more configurable devices fabricated using the fabrication process, identifying an underperforming region of the configurable devices, and determining if the underperforming region is layout sensitive. At least one of the fabrication process and the layout of the configurable device can then be adjusted based on the determination. In some embodiments, the configurable device may be a programmable logic device, such as a field programmable logic array.

The three-axis stepping motor control platform disclosed in the invention is used for position controlling of wafer detection microscope three-axis. The device comprises ARM treater, scene programmable logical gate array FPGA, stepping motor driver, hand grip control module and grating ruler for feedback X, Y, Z shafts stepping motor position. The scene programmable logical gate array FPGA has X, Y, Z shafts sport parameter register, position feedback register and other control register. The ARM treater obtains control command from control computer through communication line, codes and decodes the control command into controlling parameter needed by FPGA and configures in corresponding control register in FPGA, and the FPGA detects the variation value in the control register and drives each shaft stepping motor operation according to given values. The stepping motor control platform overcomes the limits caused by using special purpose stepping motor by adapting combined control policy of ARM and FPGA, brings great spreading space for user quadric exploiture and enhancing the control stabilizing ability.