137 results about "Power gating" patented technology

A chip includes a power grid, power switches coupled between the power grid and a circuit, and current sensors configured to generate sense currents based on load currents passing through the power switches. The chip also includes a readout circuit having an input and an output, and signal routing coupling the current sensors to the input of the readout circuit.

The invention discloses a power gating system, a power gating method and a system on chip. Relates to the technical field of power management, and comprises a central processing unit used for writing software power-down configuration information into a register module; the register module is used for triggering a software power-down request according to the software power-down configuration information and sending the software power-down request to the power gating controller; the system power consumption controller is used for determining a system power consumption mode according to the state of the central processing unit, triggering a hardware power-down request and sending the hardware power-down request to the power gating controller under the condition that the system power consumption mode is a low-power-consumption mode; and the power gate controller is used for detecting the state of a bus of the power domain based on the software power-down request or the hardware power-down request, and executing power-down time sequence control on the power domain under the condition that the state of the bus is detected to be an idle state. The technical problems that the power gating speed is low and the software overhead is large when the bus state is inquired through software with high complexity in the prior art are solved.

An IC device includes a first interconnect structure configured to distribute a power supply voltage, a second interconnect structure configured to distribute a reference voltage, a third interconnect structure configured to distribute a first power gating signal, and a plurality of logic circuits. Each logic circuit of the plurality of logic circuits includes a power switch coupled in series with a logic gate between the first and second interconnect structures, and the power switch includes a control terminal coupled to the third interconnect structure.

The disclosed systems and methods include a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer. The context can be saved to a non-volatile memory device or by keeping a retention supply voltage to a register of the memory controller. Various other methods, systems, and computer-readable media are also disclosed.

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

One aspect of the present disclosure pertains to a device. The device includes a substrate, a logic circuit disposed on the substrate, and a nanoelectromechanical systems (NEMS) device electrically connected to the logic circuit and formed on the substrate. The NEMS device includes a first electrode electrically connected to the logic circuit, a second electrode electrically connected to a first power supply, a movable feature electrically connected to the second electrode, and a control electrode operable to move the movable feature relative to the first electrode.

The invention relates to a cloud mobile phone terminal decoding chip architecture and a collaborative optimization method thereof, processing equipment and a storage medium, the chip architecture adopts an ASIC (Application Specific Integrated Circuit) chip and comprises a video decoding module, a communication interface module, a touch processing module, a dynamic power management module and a communication protocol switching module; the video decoding module is used for performing motion compensation processing and entropy decoding on input video data and determining a power gating driving signal of the dynamic power management module; the touch control processing module is used for carrying out wavelet processing and Kalman filtering processing on an input touch control signal; the dynamic power management module is used for dynamically adjusting the power supply voltage and frequency according to the power consumption information and cutting off power supply according to the power gating driving signal and / or the detected temperature; the communication protocol switching module is used for controlling switching of communication protocols; the communication interface module is used for determining power consumption information; and sending the decoded video data and the filtered touch signal to the cloud. The method and the device can be widely applied to the technical field of cloud mobile phones.

One aspect of the present disclosure pertains to a device. The device includes a substrate, a logic circuit disposed on the substrate, and a nanoelectromechanical systems (NEMS) device electrically connected to the logic circuit and formed on the substrate. The NEMS device includes a first electrode electrically connected to the logic circuit, a second electrode electrically connected to a first power supply, a movable feature electrically connected to the second electrode, and a control electrode operable to move the movable feature relative to the first electrode.

An integrated circuit includes: a backside wiring layer on a back side of a substrate, the backside wiring layer including a first backside pattern and a second backside pattern isolated from each other; and a power gating switch on a front side of the substrate, the power gating switch connected to the first and second backside patterns. The power gating switch includes: a first source / drain region connected to the first backside pattern, and configured to receive a first supply voltage from the first backside pattern; a gate line structure configured to receive a power gating signal; and a second source / drain region connected to the second backside pattern, and configured to receive a power signal from the first source / drain region based on the power gating signal.

Provided are a semiconductor system for reducing idle power when a specific block is idle and an operating method thereof. The semiconductor system includes a first block, the first block including a plurality of intellectual property (IP) blocks each configured to generate active information, and a first control logic configured to determine an active state of each of the plurality of IP blocks based on the active information and, in response to the active states of the plurality of IP blocks all being idle states, perform a power gating operation on the first block.

This invention discloses an adaptive sleep method and system for LoRa terminals used in dam monitoring, based on multi-dimensional environmental feature perception and hardware collaboration. The core of the method is as follows: after waking the terminal via RTC, it collects multi-dimensional parameters such as water level, ambient temperature, battery voltage, and channel signal-to-noise ratio, and calculates the dynamically adaptive sleep duration based on the weighted multi-dimensional features; it achieves active wireless channel avoidance through LoRa CAD channel listening, abandoning invalid transmissions and extending the sleep duration in harsh environments; it physically cuts off the power supply to the sensors during non-operation periods through a hardware-level anti-interference power gating circuit, eliminating static leakage; and it sets up a fallback mechanism for abnormal fault diagnosis to avoid unnecessary power consumption under extreme conditions. This invention completely solves the core contradiction between "long battery life" and "high responsiveness" in existing dam monitoring terminals, improving battery life performance.

A chip includes a power grid, power switches coupled between the power grid and a circuit, and current sensors configured to generate sense currents based on load currents passing through the power switches. The chip also includes a readout circuit having an input and an output, and signal routing coupling the current sensors to the input of the readout circuit.

The embodiment of the invention provides a switch setting method and device for a power gate control circuit, electronic equipment and a medium, and the method comprises the steps: constructing graph theory node models corresponding to a plurality of switches in a one-to-one manner, and obtaining the time sequence feature information of each switch; obtaining time sequence characteristic information of a plurality of switches; based on an ant colony algorithm, determining a target connection path for connecting each node by taking the time sequence characteristic information of the plurality of switches as path cost; and determining a series connection sequence of the plurality of switches according to the target connection path. According to the embodiment of the invention, a graph theory path is efficiently solved through a bionic optimization algorithm, falling into a local optimal solution is avoided, power gating time sequence delay and voltage fluctuation are remarkably reduced, meanwhile, static power consumption is optimized, and an intelligent optimization scheme is provided for a complex power gating circuit.

A three-dimensional integrated circuit and a manufacturing method therefor is used for improving the performance of the integrated circuit when the integrated circuit includes a power gating circuit. The three-dimensional integrated circuit includes a substrate, and a front-section circuit, a rear-section metal interconnection layer, and a rear-section power gating circuit that are formed on the substrate; the rear-section metal interconnection layer is formed on the front-section circuit; the rear-section power gating circuit is located in the rear-section metal interconnection layer; and the front-section circuit is electrically connected to a power supply or a ground wire by means of the rear-section metal interconnection layer and the rear-section power gating circuit.

Methods, systems, and devices for transfer command power gating within a memory system are described. A memory device may dynamically activate data path circuitry within the memory device according to an operation to be performed at the memory device. In response to receiving signaling that indicates a transfer of data stored in the memory device, the memory device may generate a power gating signal associated with activation of the data path circuitry. The signaling may include a command from a controller before a data transfer, a preamble associated with the data transfer, or both. The memory device may transfer the data via the data path using the activated data path circuitry in response to the signaling. The memory device may receive second signaling to deactivate the data path circuitry after the data transfer is complete to reduce power consumption and improve performance.

Embodiments of the present invention provide an integrated circuit, a power gating cell on the integrated circuit, and a method of manufacturing the same. The power gating cell includes a center region, a perimeter region surrounding the center region, a first active region in the center region having a first width in a first direction, the first width corresponding to at least four fin structures extending in a second direction perpendicular to the first direction, and a plurality of second active regions in the perimeter region, each second active region having a second width in the first direction, the second width corresponding to at least one and no more than three fin structures extending in the second direction.

The invention relates to a data retention method and system during power gating. The method comprises the following steps: sending a power-off request to a turn-off module, wherein the power-off request is used for indicating the turn-off module to return to-be-stored data; receiving a data storage request sent by each turn-off module, and centrally storing to-be-stored data carried by each data storage request into a first retention memory; and under the condition that a data recovery signal is received, the data stored in the first holding memory is returned to the corresponding turn-off module, and the data recovery signal is generated after the turn-off module is powered on again. By adopting the method, an additional power supply can be avoided, and the low-power-consumption implementation complexity is reduced.

A power gating circuit including: a power gating transistor; a gate bias generating circuit configured to provide a gate bias control signal to the gate of the power gating transistor; and a body bias generating circuit configured to provide a body bias control signal to the body of the power gating transistor, wherein when the power gating transistor is turned on, the gate bias generating circuit provides the gate bias control signal having a positive voltage level and the body bias generating circuit provides the body bias control signal having the positive voltage level, and when the power gating transistor is turned off, the gate bias generating circuit provides the gate bias control signal having a ground voltage level or a negative voltage level, and the body bias generating circuit provides the body bias control signal having the ground voltage level or the negative voltage level.

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronous circuits connected by a scan chain, a test data input (TDI) line, a test data output (TDO) line connected to the output terminal, a test access port (TAP) controller that controls operations of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal, a power management unit that controls power gating of the blocks, and a clock management unit that controls a clock signal supplied to the blocks. The TAP controller includes a first register that stores first data used to generate a first control signal that controls the power and clock management unit, the power and clock management unit controlling operations of the blocks based on the first control signal.

A system on chip (SoC) includes at least a first core and a second core, a first power gating switch and a second power gating switch, and a first power switch. The first power gating switch is arranged between the first core and a first power rail receiving a first voltage and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail receiving a second voltage and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail and is selectively turned on in response to a first power control signal, thereby connecting the first power gating switch or the second power gating switch to both the first power rail and the second power rail.

A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.

An apparatus has a phase lock loop with an adaptive loop filter that has a reset circuit controlled by a power gating pulse circuit.

A dynamic random-access memory (DRAM) device has a layer of backend transistors that are formed over the DRAM array. For example, the backend transistors may include channel regions or other transistor structures that are in direct contact with an etch stop layer formed over the DRAM array. The backend transistors may increase the amount of surface area that can be utilized for memory cells by moving transistors for implementing power gating, SRAM tags, or other features to a backend layer that is over the storage capacitors. Low temperature processes may be used to fabricate the backend transistors while minimizing damage to frontend structures.

The invention provides a low-power-consumption working method and system based on a wireless HART (Highway Addressable Remote Transducer) wireless temperature transmitter. The low-power-consumption working method comprises the steps that S1, a main communication unit is responsible for protocol stack and data processing, a coprocessor manages RTC (Real Time Clock) awakening and power gating, and zero static power consumption in a non-communication time period is realized through partitioned power supply; s2, the coprocessor obtains a TDMA scheduling table from the main unit; s3, comparing the threshold value of the local temperature data delta T, and triggering reporting only when the threshold value exceeds the limit; rSSI / SNR is dynamically evaluated, a non-key broadcast time slot is intelligently skipped, and deep dormancy in a stable period is realized; and S4, the equipment reports an energy state through a Join Request and a health report, the network manager allocates relay tasks by adopting an energy weighting algorithm, and if the electric quantity of the battery node is lower than a threshold value, a terminal mode can be entered. And S5, the LSTM predicts the node electric quantity and the network load, reinforcement learning dynamically adjusts the TDMA scheduling and routing strategy, and active prediction maintenance and whole network energy balance are realized.

In accordance with the described techniques, a device includes a host processor, a memory, and a memory physical layer. The memory physical layer enters an enhanced low power state in which a power supply is disconnected from a portion of the memory physical layer while the memory is inactive with respect to servicing memory requests of the host processor. In addition, the memory physical layer exits the enhanced low power state responsive to the memory being active with respect to servicing memory requests of the host processor and / or at least one memory request being enqueued for servicing by the memory.

A signal sampling circuitry comprises: a plurality of sampling units receiving an input signal for time-interleaved sampling, each sampling unit comprising: a sampling capacitor having a first plate connected to an output of the sampling unit; a first plate switch between the first plate and a first reference voltage, a second plate switch between a second plate of the sampling capacitor and a second reference voltage; an input buffer for outputting a buffered input signal to the second plate; wherein the input buffer is connected to at least one power gating switch for powering down the input buffer.

The invention discloses a high-density embedded dynamic random access on-chip cache device and an implementation method. The high-density embedded dynamic random access on-chip cache device comprises an improved read-out current difference enhanced high-density eDRAM storage array and a read-out circuit, the reading circuit comprises a group of two-step power gating sensing amplifiers and a reading time sequence control circuit; threshold voltage selection of an on-chip cache reading transistor is optimized, and the difference proportion of reading current when different values are stored is expanded; by optimizing the structure of the cache memory array, the influence of interference current is eliminated; and a two-step power gating sensing amplifier is designed, and the reading current resolution capability is improved and the power consumption is effectively controlled by accurately controlling the starting time of two stages of circuits with different characteristics in the sensing process. The on-chip cache technical scheme provided by the invention realizes good balance among data retention time, energy efficiency and storage density, and is particularly suitable for edge computing equipment and artificial intelligence application scenes with strict requirements on energy efficiency and storage capacity.

A memory device includes a core peripheral circuit structure including a first bonding metal pad connected to an internal power supply voltage line; and a cell array structure disposed on the core peripheral circuit structure and including a second bonding metal pad in contact with the first bonding metal pad. The cell array structure includes a memory cell array and a power gating switch connected between an external power supply voltage line and the first bonding metal pad, and the power gating switch is located in a region of the cell array structure different from a memory cell array and selectively provides an external power supply voltage to the internal power supply voltage line.

A power gating circuit includes a collection of weak-strong switch units and strong switch units chained together in a daisy chain. The layout (footprint) of each weak-strong unit is compatible with that of strong-only units such that replacing weak-strong units with strong-only units or vice versa during the design phase of the power gating circuit does not affect the routing or timing operation of the circuitry that the power gating circuit powers. This allows the ratio of weak switches to strong switches for minimizing inrush current to be optimally set during the design phase of the IC. Each weak-strong unit couples power rails together via weak transistors in response to a weak enable signal and via strong transistors in response to a strong enable signal. Each strong-only unit couples power rails together via weak and strong transistors in response to a strong enable signal.