445 results about "Power gating" patented technology

Embodiments of a system that reduces power consumption by power-gating media decoders are described. During operation of the system, a decoder circuit receives encoded audio data and outputs corresponding decoded audio data to a memory, which is electrically coupled to the decoder circuit. Moreover, control logic, which is electrically coupled to the memory and the decoder circuit, provides commands to the memory and the decoder circuit that selectively disable at least a portion of the memory based on an amount of decoded audio data in the memory.

A system and method for dynamic function based power control is disclosed. In one embodiment, a system includes a bridge unit having a memory controller and a communication hub coupled to the memory controller. The system further includes a power management unit, wherein the power management unit is configured to clock-gate the communication hub responsive to determining that each of a plurality of processor cores are in an idle state and that an I/O interface unit has been idle for an amount of time exceeding a first threshold. The power management unit is further configured to clock-gate the memory controller responsive to clock-gating the communication hub and determining that a memory coupled to the memory controller is in a first low power state. The power management unit may also perform power-gating of functional units subsequent to clock-gating the same.

Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration memory cells, and so forth. Embodiments describe circuits and methods for implementing multiple supplies as sources of V_dd, multiple voltage thresholding V_t, signal level translators, and power gating of circuitry to deactivate portions of the circuit which are inactive. The supply voltage levels can be fixed, or programmable. Methods are described for performing circuit CAD in the routing and assignment process on FPGAs, in particular for optimizing FPGA use having the power reduction circuits taught. Routing methods describe utilizing slack timing, power sensitivity, trace-based simulations, and other techniques to optimize circuit utilization on a multi V_dd FPGA.

A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands.

A downlink beam frame signal processing system (100) for a communication satellite includes a packet switch (608) that routes self addressed uplink data to a memory (804). The memory (804) stores queues for at least a first and a second downlink beam hop locations (302, 304). The processing system (100) also includes a power amplifier (108) that amplifies a waveform formed using the uplink data. A power gating circuit (1200) coupled to the power amplifier (108) includes a power gate input (1216) responsive to a power gating signal to remove RF power from at least a portion of the waveform before transmission.

The invention relates to a power-gating control method for a graphics processing unit having a unified shader unit, which includes a plurality of shaders. The method includes the steps of: rendering a plurality of previous frames; calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame; determining a second number of active shaders for rendering a next frame immediately following the previous frame according to the first number of active shaders and the corresponding frame rate of each previous frame; and activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders.

Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter includes a plurality of delay stages configured to enable propagation of a transitioning signal through the delay stages during an enabled state and configured to inhibit propagation of the transitioning signal through the delay stages during a disabled state. Delay stages are interconnected to allow sustained transitions to propagate through the delay stages during the enabled state and to preserve a state of the gated ring oscillator time-to-digital converter during the disabled state. The state represents a time resolution that is finer than the delay of at least one of the delay stages. A measurement module determines the number of transitions of the delay stages.

The present invention provides a power gating structure having data retention and intermediate modes and able to operate under multiple modes. A conventional power gating structure has only turn-on and turn-off functions, and is used to suppress a leakage current problem which has become more and more serious in advance manufacture processes, under a turn-off mode. However, in a memory circuit, such as latch, register and SRAM, when the power gate is turned off, a new power gating structure is required for data retention. The power gating structure of the present invention can be set into one of 4 different operational modes: a data retention mode for maintaining the static noise margin of the memory, an intermediate mode for reducing the interference on ground and power levels, an active mode used when the circuit operates in normal condition, and a standby mode used when the circuit does not operate.

An integrated circuit device comprising at least one signal processing module and a power gating control module arranged to control gating of at least one power supply to at least a part of the at least one signal processing module. The power gating control module is arranged to receive at least one operating parameter; configure at least one power gating setting of the power gating control module based at least partly on the at least one received operating parameter; and apply power gating for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting.

A power gated variable hop cycle beam laydown (700) manifests itself as first cells (C, D) supported by a first hop cycle, second cells (G, H) supported by a second hop cycle, and transition cells (E, F) supported by a transition hop cycle. The transition hop cycle uses power gating to transition the laydown (700) from cells (C, D) operating at the first hop cycle to cells (G, H) operating at the second hop cycle. To this end, the transition hop cycle power gates its downlink beam for a portion of time needed to reduce interference between nearby (e.g., adjacent) cells.

A method and a structure provide a space efficient integrated circuit using standard cells and power gating by switch cells. The standard cells may be tapless, i.e., not provided a substrate connection to a power supply or ground rail by a tap within the cell. The substrate connection for these standard cells may be provided by the switch cells or by specialized tap cells. The tapless standard cells may include only a context-sensitive rail, which may be configured to be a virtual ground rail by a power gating connection to a switch cell or by a direct connection to a power supply or ground rail.

A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.

A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The source of the PMOS transistor can be coupled to a power supply line through an additional PMOS transistor for power gating of voltage VDD. The inverter receives an input signal IN and its complementary version that has transitioned earlier than the input signal. In response to the input signal, the inverter produces an output signal. A NAND gate that receives the output signal and the complementary input signal controls the power gating NMOS transistor. A NOR gate that receives the output signal and the complementary input signal controls the power gating PMOS transistor. The power gating to the CMOS inverter is performed by feedback of the output signal and the complementary input signal, with the result that current leakage reduction through the CMOS controlled inverter is achieved. A self leakage reduction with power gating transistors is applicable to another type of logic gates such as NAND, NOR and Exclusive-OR, AND, OR.

A new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual supply/ground bounce for the proposed scheme is also presented.

The invention discloses an optimization method of a low-power-consumption circuit design, belonging to the field of automation of integrated circuits. The optimization method comprises the following steps of: assigning positions of information of a gate-level circuit network table, simulation excitation, a unit library and a device model, reading the information in to execute the gate-level circuit simulation, partitioning gate-level circuits, executing circuit analysis and simulation result analysis, and executing optimization processing on the circuits according to the analysis results based on low-power-consumption technologies. According to the optimization method disclosed by the invention, the design of the gate-level circuit network table is optimized, and a part of units are inserted and/or replaced in the circuit network table to support the low-power-consumption technologies of an MTCMOS (Multi-threshold Complementary Metal Oxide Semiconductor), a VTCMOS (Variable Threshold Complementary Metal Oxide Semiconductor), power source gate control, multi-voltage and DVFS (Dynamic Voltage and Frequency Scaling), power gating d the like, thus the power consumption of a chip system is the minimum on the premise of ensuring circuit performances of the chip system.

An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

A power gating circuit includes a first current switch, a second current switch, and a switching controller. The first current switch is connected between a power rail and a circuit block operated by an operating supply voltage, and provides a first current when turned on. The second current switch is connected between the power rail and circuit block, and provides a second current larger than the first current when turned on. The switching controller turns on first current switch when transitioned from a sleep mode to an active mode to change the operating supply voltage using the first current, generates a reference voltage based on the operating supply voltage that changes more slowly than the operating supply voltage, and turns on the second current switch based on the reference voltage to provide the second current to the circuit block.

To provide a semiconductor device including a plurality of circuit blocks each of which is capable of performing power gating by setting off periods appropriate to temperatures of the respective circuit blocks. Specifically, the semiconductor device includes an arithmetic circuit, a memory circuit configured to hold data obtained by the arithmetic circuit, a power supply control switch configured to control supply of the power supply voltage to the arithmetic circuit, a temperature detection circuit configured to detect the temperature of the memory circuit and to estimate overhead from the temperature, and a controller configured to set a period during which supply of the power supply voltage is stopped in the case where a power consumption of the arithmetic circuit during the period is larger than the overhead period and to control the power supply control switch.

A power supply control circuit for controlling power supply or stop of power supply is provided between a power source and a circuit block such as a processor. The power supply control circuit not only performs power supply to the circuit block or intentionally stops power supply but also is able to hold the power supply potential when the power supply is suddenly stopped, so that a loss of data in the circuit block can be prevented. By utilizing the power supply potential held by the power supply control circuit, data in the circuit block is saved in the nonvolatile memory device, so that a loss of data in the circuit block can be prevented. As described above, the power supply control circuit functions as a power gating switch and a circuit for holding the power supply potential in the case where power supply is suddenly stopped.