79 results about "Power gating" patented technology

One aspect of the present disclosure pertains to a device. The device includes a substrate, a logic circuit disposed on the substrate, and a nanoelectromechanical systems (NEMS) device electrically connected to the logic circuit and formed on the substrate. The NEMS device includes a first electrode electrically connected to the logic circuit, a second electrode electrically connected to a first power supply, a movable feature electrically connected to the second electrode, and a control electrode operable to move the movable feature relative to the first electrode.

This invention discloses an adaptive sleep method and system for LoRa terminals used in dam monitoring, based on multi-dimensional environmental feature perception and hardware collaboration. The core of the method is as follows: after waking the terminal via RTC, it collects multi-dimensional parameters such as water level, ambient temperature, battery voltage, and channel signal-to-noise ratio, and calculates the dynamically adaptive sleep duration based on the weighted multi-dimensional features; it achieves active wireless channel avoidance through LoRa CAD channel listening, abandoning invalid transmissions and extending the sleep duration in harsh environments; it physically cuts off the power supply to the sensors during non-operation periods through a hardware-level anti-interference power gating circuit, eliminating static leakage; and it sets up a fallback mechanism for abnormal fault diagnosis to avoid unnecessary power consumption under extreme conditions. This invention completely solves the core contradiction between "long battery life" and "high responsiveness" in existing dam monitoring terminals, improving battery life performance.

The embodiment of the invention provides a switch setting method and device for a power gate control circuit, electronic equipment and a medium, and the method comprises the steps: constructing graph theory node models corresponding to a plurality of switches in a one-to-one manner, and obtaining the time sequence feature information of each switch; obtaining time sequence characteristic information of a plurality of switches; based on an ant colony algorithm, determining a target connection path for connecting each node by taking the time sequence characteristic information of the plurality of switches as path cost; and determining a series connection sequence of the plurality of switches according to the target connection path. According to the embodiment of the invention, a graph theory path is efficiently solved through a bionic optimization algorithm, falling into a local optimal solution is avoided, power gating time sequence delay and voltage fluctuation are remarkably reduced, meanwhile, static power consumption is optimized, and an intelligent optimization scheme is provided for a complex power gating circuit.

Methods, systems, and devices for transfer command power gating within a memory system are described. A memory device may dynamically activate data path circuitry within the memory device according to an operation to be performed at the memory device. In response to receiving signaling that indicates a transfer of data stored in the memory device, the memory device may generate a power gating signal associated with activation of the data path circuitry. The signaling may include a command from a controller before a data transfer, a preamble associated with the data transfer, or both. The memory device may transfer the data via the data path using the activated data path circuitry in response to the signaling. The memory device may receive second signaling to deactivate the data path circuitry after the data transfer is complete to reduce power consumption and improve performance.

Embodiments of the present invention provide an integrated circuit, a power gating cell on the integrated circuit, and a method of manufacturing the same. The power gating cell includes a center region, a perimeter region surrounding the center region, a first active region in the center region having a first width in a first direction, the first width corresponding to at least four fin structures extending in a second direction perpendicular to the first direction, and a plurality of second active regions in the perimeter region, each second active region having a second width in the first direction, the second width corresponding to at least one and no more than three fin structures extending in the second direction.

A power gating circuit including: a power gating transistor; a gate bias generating circuit configured to provide a gate bias control signal to the gate of the power gating transistor; and a body bias generating circuit configured to provide a body bias control signal to the body of the power gating transistor, wherein when the power gating transistor is turned on, the gate bias generating circuit provides the gate bias control signal having a positive voltage level and the body bias generating circuit provides the body bias control signal having the positive voltage level, and when the power gating transistor is turned off, the gate bias generating circuit provides the gate bias control signal having a ground voltage level or a negative voltage level, and the body bias generating circuit provides the body bias control signal having the ground voltage level or the negative voltage level.

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronous circuits connected by a scan chain, a test data input (TDI) line, a test data output (TDO) line connected to the output terminal, a test access port (TAP) controller that controls operations of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal, a power management unit that controls power gating of the blocks, and a clock management unit that controls a clock signal supplied to the blocks. The TAP controller includes a first register that stores first data used to generate a first control signal that controls the power and clock management unit, the power and clock management unit controlling operations of the blocks based on the first control signal.

A system on chip (SoC) includes at least a first core and a second core, a first power gating switch and a second power gating switch, and a first power switch. The first power gating switch is arranged between the first core and a first power rail receiving a first voltage and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail receiving a second voltage and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail and is selectively turned on in response to a first power control signal, thereby connecting the first power gating switch or the second power gating switch to both the first power rail and the second power rail.

An apparatus has a phase lock loop with an adaptive loop filter that has a reset circuit controlled by a power gating pulse circuit.

A dynamic random-access memory (DRAM) device has a layer of backend transistors that are formed over the DRAM array. For example, the backend transistors may include channel regions or other transistor structures that are in direct contact with an etch stop layer formed over the DRAM array. The backend transistors may increase the amount of surface area that can be utilized for memory cells by moving transistors for implementing power gating, SRAM tags, or other features to a backend layer that is over the storage capacitors. Low temperature processes may be used to fabricate the backend transistors while minimizing damage to frontend structures.

The invention provides a low-power-consumption working method and system based on a wireless HART (Highway Addressable Remote Transducer) wireless temperature transmitter. The low-power-consumption working method comprises the steps that S1, a main communication unit is responsible for protocol stack and data processing, a coprocessor manages RTC (Real Time Clock) awakening and power gating, and zero static power consumption in a non-communication time period is realized through partitioned power supply; s2, the coprocessor obtains a TDMA scheduling table from the main unit; s3, comparing the threshold value of the local temperature data delta T, and triggering reporting only when the threshold value exceeds the limit; rSSI / SNR is dynamically evaluated, a non-key broadcast time slot is intelligently skipped, and deep dormancy in a stable period is realized; and S4, the equipment reports an energy state through a Join Request and a health report, the network manager allocates relay tasks by adopting an energy weighting algorithm, and if the electric quantity of the battery node is lower than a threshold value, a terminal mode can be entered. And S5, the LSTM predicts the node electric quantity and the network load, reinforcement learning dynamically adjusts the TDMA scheduling and routing strategy, and active prediction maintenance and whole network energy balance are realized.

In accordance with the described techniques, a device includes a host processor, a memory, and a memory physical layer. The memory physical layer enters an enhanced low power state in which a power supply is disconnected from a portion of the memory physical layer while the memory is inactive with respect to servicing memory requests of the host processor. In addition, the memory physical layer exits the enhanced low power state responsive to the memory being active with respect to servicing memory requests of the host processor and / or at least one memory request being enqueued for servicing by the memory.

The invention discloses a high-density embedded dynamic random access on-chip cache device and an implementation method. The high-density embedded dynamic random access on-chip cache device comprises an improved read-out current difference enhanced high-density eDRAM storage array and a read-out circuit, the reading circuit comprises a group of two-step power gating sensing amplifiers and a reading time sequence control circuit; threshold voltage selection of an on-chip cache reading transistor is optimized, and the difference proportion of reading current when different values are stored is expanded; by optimizing the structure of the cache memory array, the influence of interference current is eliminated; and a two-step power gating sensing amplifier is designed, and the reading current resolution capability is improved and the power consumption is effectively controlled by accurately controlling the starting time of two stages of circuits with different characteristics in the sensing process. The on-chip cache technical scheme provided by the invention realizes good balance among data retention time, energy efficiency and storage density, and is particularly suitable for edge computing equipment and artificial intelligence application scenes with strict requirements on energy efficiency and storage capacity.

An integrated circuit device is provided. The integrated circuit device includes: a substrate with a first active area and a second active area spaced apart from each other in a first horizontal direction; a plurality of normal cells arranged on a first surface of the substrate; a power wiring structure arranged on a second surface of the substrate; and a power gating cell arranged on the first surface of the substrate. The power gating cell includes: a sleep control transistor arranged in the first active area; and a through via penetrating the second active area of the substrate. The power gating cell is configured to provide a virtual power voltage to the plurality of normal cells through a virtual power line based on a power voltage supplied from the power wiring structure through the through via and a power line.

Methods and apparatus for a diagnostic in situ ring oscillator (RO) circuit for DC and transient characterization. The RO circuit includes a plurality of symmetrical stages coupled via an RO feedback signal line and forming an inverter chain, where each stage includes a CMOS inverter comprising a pair of pMOS and nMOS transistors coupled between power-gating transistors respectively coupled to a positive voltage source and ground, wherein an output of a CMOS inverter for the stage is coupled to an input for the CMOS inverter of a next stage. The first stage is a configurable enable stage to enable the inverter chain to be set into a defined logic state, followed by multiple pre-stage-DUT stages. The output of the last stage is feed back to the input of the enable stage to form an RO feedback signal. The RO circuit can operate in multiple modes including an AC mode, a DC mode, and a hybrid mode.

A power gating circuit includes a power gating switch and a switching circuit. The power gating switch is coupled to a function block and operates in response to a voltage level of a first node. The switching circuit turns off the power gating switch by discharging the first node to a second driving voltage level during a first time period after blocking a first driving voltage from being applied to the first node in accordance with a plurality of control signals, and applying a third driving voltage to the first node during a second time period after the first time period.

The techniques described herein can relate to providing a programmable interconnection network (e.g., a programmable network-on-chip (NOC)). A method can include determining a transmission parameter, combining one or more lanes of the interconnection network based at least in part on the transmission parameter, and power gating any unused lanes after the combining.

In accordance with the described techniques, a device or system includes a digital logic circuit organized into multiple partitions, and a power gating circuit. Further, the digital logic circuit includes base logic representing the digital logic circuit before being modified by external logic of the system that is external to the digital logic circuit. The power gating circuit is configured to independently control power supplied to the multiple partitions of the digital logic circuit. As part of this, the power gating circuit initiates a power state transition to a power state in which an entirety of the base logic of the digital logic circuit is powered off.

The embodiment of the invention relates to a peripheral device power gating system and method. Various techniques are provided for managing power modes (e.g., also referred to as power states) in a peripheral device connected to a host device. In one example, a method includes receiving, by an intermediary device communicatively connected between a host device and a peripheral device, a notification that the host device will transition from a high power mode to a reduced power mode. The method also includes receiving, by the intermediary device from the peripheral device, context data associated with an operational state of the peripheral device. The method also includes storing, by the intermediary device, the context data and power gating, by the intermediary device, the peripheral device while the host device remains at least partially on in the reduced power mode. Additional embodiments are also provided that use the stored context data to restore the operating state of the peripheral device. Additional systems, apparatuses, and methods are also provided.

Provided is a memory device and a method of operating same, the memory device including: a mode register configured to store a first setting value corresponding to a power-down operation to be performed in a power-down state and a second setting value corresponding to a start time of a power gating operation; and a power-down control circuit, wherein the power-down control circuit is configured to: control the memory device to perform the power-down operation based on a first command for causing the memory device to enter the power-down state, and based on the power-down operation comprising the power gating operation, control the memory device to perform the power gating operation at the start time after the memory device enters the power-down state.

A frequency multiplier includes a first ring oscillator, a second ring oscillator that is turned on complementarily to the first ring oscillator, a combining circuit that combines a first output signal of the first ring oscillator and a second output signal of the second ring oscillator to generate a final output signal, and a calibration circuit that corrects a discontinuous pulse included in the final output signal based on feedback of the final output signal.

A power gating circuit for a memory includes a plurality of header switches, the plurality of header switches comprising: a first transistor having a source tied to an external power supply line; and a second transistor coupled to a drain of the first transistor and having its own drain coupled to an internal voltage line of the memory, wherein the second transistor is structured to be used as a transistor or a diode based on control of a gate of the second transistor; and a selection device coupled to the gate of the second transistor to controllably couple the gate of the second transistor in a first state to the drain of the second transistor for diode operation and in a second state to a second voltage line for transistor operation.

A single-ended wired transmitter based on adaptive amplitude-phase cross-domain equalization comprises a data unit and a clock unit, and the clock unit provides multi-frequency and multi-phase clock signals for a serialization and driving circuit of the data unit through frequency division, duty cycle calibration and quadrature phase calibration according to an external differential input clock; the data unit performs amplitude pre-emphasis processing according to the hopping information to generate an equalization control signal, and performs phase control on the four-phase clock according to the length of the continuous same code element to obtain a clock signal for phase domain equalization; through the adaptive amplitude-phase cross-domain equalization technology, the mixed-mode driver technology, the current multiplexing technology of the phase modulator and the power gating technology of the serializer, the power consumption and the power noise can be remarkably reduced and the equalization capability can be improved in the memory interface and core particle interconnection application scene.

An example semiconductor device includes a lower wiring including a lower wiring line; an upper wiring layer including an upper wiring line; and a power gating unit between the lower wiring layer and the upper wiring layer. The power gating unit includes: a first active region on the substrate and including first and second lower source / drain patterns and a first channel pattern connecting the first and second lower source / drain patterns to each other; a second active region on the first active region and including a first upper source / drain pattern and a second upper source / drain pattern; and a power gate electrode surrounding the first channel pattern and extending in a first direction parallel to the top surface of the substrate. The lower wiring layer includes: a global power line connected to the first lower source / drain pattern; and a local power line connected to the second lower source / drain pattern.

A data flip-flop circuit includes a flip-flop, a recovery latch and a cut-off transistor. The flip-flop stores a data signal that is input, using a clock signal and a virtual power supply voltage and provides the stored data signal as an output signal at an output node in response to a rising transition of the clock signal. The recovery latch is connected to a power supply voltage and a ground voltage, is connected to the flip-flop at the output node, stores the output signal internally in response to a first transition of a chip enable signal, recovers the stored output signal in response to end of a power gating interval based on the chip enable signal, and provides the recovered output signal to the flip-flop. The cut-off transistor floats the virtual power supply voltage provided to the flip-flop based on a first power gating signal.

Semiconductor devices are provided. A semiconductor device includes a power-gating cell having a p-type metal-oxide-semiconductor (PMOS) region. The semiconductor device also includes a backside (BS) global power rail. Moreover, the semiconductor device includes a contact that is in contact with both the PMOS region and the BS global power rail.

Aspects presented herein relate to methods and devices for communication including an apparatus, e.g., an SoC or AP. The apparatus may obtain an indication of data for a set of components or a set of signals associated with a hardware system. The apparatus may also identify whether the data for each of the set of components or the set of signals is within a suitable range for the hardware system. Further, the apparatus may output an indication of whether the data for each of the set of components or the set of signals is within the suitable range for the hardware system.

The present disclosure relates to a method and system for data retention during power gating. The method includes: sending a power-off request to a shut-off module, the power-off request being configured to instruct the shut-off module to return to-be-stored data; receiving a data saving request sent by each shut-off module, and centrally storing the to-be-stored data carried by each data saving request in a first retention memory; and in response to receiving a data restore signal, returning data stored in the first retention memory to a corresponding shut-off module. The data restore signal is generated after the shut-off module is powered on again.

Example embodiments relate to a memory device that can selectively interrupt power supply to a circuit that performs a single operation. The memory device includes a power line, a ground source line, a power gated switch circuit, and a row decoder having a plurality of word line driver circuits. The word line driver circuit is divided into a first group and a second group based on a first most significant bit (MSB) signal among decoded row addresses. The power-gated switch circuit connects a power line and a ground source line to a first power voltage line and a first ground voltage line of the word line driver circuit in the first group, respectively, in response to a first control signal, and connecting the power supply line and the ground source line to a first power supply voltage line and a first ground voltage line of the word line driver circuit in the second group, respectively, in response to a second control signal.