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64results about "Majority/minority circuits" patented technology
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Controlling and powering multiple chips
ActiveUS12341514B1Majority/minority circuitsDigital data processing detailsControl busEmbedded system
An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.
Owner:AURADINE INC
Exclusive-or logic gate with non-linear input capacitors
ActiveUS12308838B1Majority/minority circuitsLogic circuits coupling/interface using field-effect transistorsCMOSTelecommunications
A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.
Owner:KEPLER COMPUTING INC
Ferroelectric or paraelectric based low power multiplier
A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and / or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.
Owner:KEPLER COMPUTING INC
Asynchronous full-adder with majority or minority gates to generate carry-out true output
Asynchronous full-adder circuit is described. The full-adder includes majority and / or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and / or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.
Owner:KEPLER COMPUTING INC
Diode connected non-linear input capacitors based majority gate
ActiveUS12445134B1Majority/minority circuitsLogic circuits using dielectric elementsCapacitanceSoftware engineering
A logic gate includes a first capacitor to receive a first input, the first capacitor coupled to a node and a first diode structure coupled to the first input and the node. The logic gate future includes a second capacitor to receive a second input, the second capacitor coupled to the node and a second diode structure coupled to the second input and the node. The logic gate further includes a third capacitor to receive a third input, wherein the third capacitor is coupled to the node and a third diode structure coupled to the third input and the node.
Owner:KEPLER COMPUTING INC
Integrated circuit
Provided is an integrated circuit capable of maintaining high reliability even under a severe environment such as a high radiation environment. An integrated circuit 1 comprises: a master latch 3 for receiving an input of an input signal, and outputting a signal at a timing based on a master clock signal; and N (N is an odd number of 3 or more) slave latches 4 for receiving an input of the signal outputted from the master latch 3, and outputting an output signal at a timing based on a slave clock signal. The master latch 3 outputs, to the slave latches 4, a signal of a value determined on the basis of the input signal and the input of the outputted signal. Each of the slave latches 4 is configured to output an output signal of a value determined on the basis of a majority decision result of signals respectively outputted from the N slave latches 4 or a majority decision result of signals, which the slave latches 4 have respectively received, as inputs, from the master latch 3.
Redundancy circuit
In an embodiment, an integrated circuit (700) includes: a voting circuit (706) including N scan flip-flops (402, 404, 406), where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop (402) and a second scan flip-flop (406), where an output of the first scan flip-flop (402) is coupled to a scan input of the second scan flip-flop (406); a scan chain (720) including the N scan flip-flops (402, 404, 406) of the voting circuit (706), and third (704) and fourth (708) scan flip-flops, the scan chain configured to receive a scan enable signal (scan_en); and a scan enable control circuit (550, 552) configured to control a scan enable input of the first (402) or second (406) scan flip-flops based on the scan enable signal (scan_en) and based on a scan input of the third scan flip-flop (704) or an output of the fourth scan flip-flop (708).
Owner:STMICROELECTRONICS INT NV
Server system and method for improving pin reuse rate of programmable devices
The present invention proposes a server system for improving the pin reuse rate of a programmable device. The system includes a programmable device, a power supply, a first device, and a second device. The programmable device is connected to the power supply, the first device, and the second device. The programmable device includes a main logic communication module, a detection module, a storage module, and a multiplexing pin. The main logic communication module is connected to the first device via the multiplexing pin. The detection module is connected to the second device via the multiplexing pin, and the storage module is connected to the detection module. The multiplexing pin is used to receive an in-place signal sent when the second device is powered on and to send the in-place signal to the detection module. The detection module is used to send the in-place signal to the storage module, and the storage module stores the in-place signal. The main logic communication module is used to communicate with the first device via the multiplexing pin. The present application improves the pin reuse rate. The present invention also provides a method for improving the pin reuse rate of a programmable device.
Owner:FULIAN PRESION ELECTRONICS (TIANJIN) CO LTD
SFQ-based pulse conservation logic gate
PendingCN119678370AMajority/minority circuitsLogic circuits using superconductive devicesSoftware engineeringInductor
Josephson junction-based logic devices and methods of using the same are described. An example of a logic device based on a Josephson junction includes a dual input OR / AND (or / and) (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first and second input sources are configured to provide a single flux quantum (SFQ) pulse. The OA2 gate also includes a first plurality of inductors coupled between the first input node and one of: a first output node or a second output node. The OA2 gate also includes a second plurality of inductors coupled between the second input node and one of the first or second output node. The OA2 gate also includes a Josephson junction coupled between the common node and one of: the first or second input node, or the first or second output node.
Owner:INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
Thermal-electric logic integrated circuit and use of said integrated circuit
ActiveUS12191858B2Majority/minority circuitsSemiconductor/solid-state device detailsMetal insulator phase transitionLogic network
The invention is based on the integrated application of a thermal-electric active device (phonon transistor). Phonon transistors consist of resistors that respond to temperature changes with a metal-insulator phase transition, or possibly other resistors suitable for heat generation. These resistors are thermally and electrically coupled to each other as needed, and are thermally and electrically insulated from each other. The thermal-electric system built in this way is suitable for the implementation of high-integration logic networks.
Owner:MIZSEI JANOS +1
Majority logic gate based sequential circuits
The low power sequential circuit (e.g., a latch) uses nonlinear polarized capacitors to hold charge with fewer transistors than conventional CMOS sequential circuits. The sequential circuit includes a three-input majority gate having first, second and third inputs and a first output. The sequential circuit includes a driver coupled to the first output, the driver generating a second output. The sequential circuit further includes an exclusive-or (XOR) gate for receiving a clock and the second output, the XOR gate generating a third output coupled to the second input, the first input receiving the data and the third input receiving the second output.
Owner:KEPLER COMPUTING INC
Majority-decision logic device, photoelectric conversion device, optical communication logic device, and method for controlling majority-decision logic device
A majority-decision logic device 1 comprises a non-magnetic semiconductor layer 10 made of a material that, when irradiated with light having at least two kinds of mutually different polarization states, generates electron spin waves having different phases corresponding to the polarization states. The non-magnetic semiconductor layer 10 comprises: three or more input portions to which a light signal is input; and at least one output portion that outputs a result of interference of the electron spin waves. The length of the distance between adjacent input portions as projected in the direction of vibration of the electron spin waves is an integer multiple of the wavelength of the electron spin waves.
Owner:THE JAPAN SCI & TECH AGENCY
Dynamic logic style-based energy efficient logic of spin torque majority gate
PCT designated stage expiredWO2025075270A1Majority/minority circuitsDigital data processing detailsSoftware engineeringTransistor
A dynamic logic style-based energy efficient logic of a spin torque majority gate is presented. A dynamic logic-based spin torque majority gate circuit proposed by the present invention dynamically adjusts a current flow for each STMG through a transistor which is turned on / off according to a clock signal, in order to solve cascading and fan-out problems.
Owner:INHA UNIV RES & BUSINESS FOUNDATION
Chaotic computer including spin soliton, operation method of chaotic computer, and chaotic computing method using spin soliton
An operating method of a chaotic computer including a chaotic logic device includes setting a first initial value based on a first initial state corresponding to a first logical operation, applying the set first initial value to the chaotic logic device, setting a first input value to be applied to the chaotic logic device based on first input data, applying the first input value to the chaotic logic device, generating a chaos signal to have the chaotic logic device operate in a chaotic mode, applying the chaos signal to the chaotic logic device, and measuring a first output value from the chaotic logic device operating based on the first input value and the chaos signal, and generating first output data based on the first output value. The chaotic logic device includes a magnetic thin film configured to have spin soliton formed therein.
Owner:SAMSUNG ELECTRONICS CO LTD +1
Non-linear polar material based low power multiplier with transmission-gate based reset mechanism
ActiveUS12436739B1Power reduction in field effect transistorsMajority/minority circuitsDielectricCMOS
A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and / or minority gates. The majority and / or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and / or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and / or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.
Owner:KEPLER COMPUTING INC
Circuit architecture and layout for a voting interlocked logic cell
This invention comprises an integrated circuit in CMOS technology which can act as a regular sequential logic latch, having one data signal input, or as a voting latch, having three data signal inputs. The circuit schematic of this integrated circuit is such that it allows for a certain placement of the devices in the physical, manufactured integrated circuit that makes it possible to optimize the arrangement of the n-type MOSFET devices and p-type MOSFET devices in the circuit independently, using the Layout Optimization through Error Aware Positioning (LEAP), and thereby to remove, or reduce, the occurrence of radiation generated soft errors.
Owner:LILJA KLAS
Single cycle binary matrix multiplication
PCT designated stageWO2025235540A1Digital data information retrievalMajority/minority circuitsAlgorithmTheoretical computer science
A system and method for single cycle binary matrix multiplication in neural network computations is disclosed. The system includes a memory array storing binary weights, an input unit for activating rows based on a binary activation vector, and per-column majority sense amplifiers. The system performs binary matrix multiplication in a single cycle, enabling efficient implementation of binary neural networks. The memory array may include sections for weights and inverse weights, with corresponding activation register sections. Differential sense amplifiers may implement the majority function. The system can be applied to convolutional neural networks, using SRAM arrays for image storage and processing. Methods for determining majority votes and counting activated bits using iterative modification of the activation vector are also described.
Owner:GSI TECHNOLOGY INC
Asynchronous full-adder with majority or minority gates to generate an enable or an acknowledgement
Asynchronous full-adder circuit is described. The full-adder includes majority and / or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and / or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.
Owner:KEPLER COMPUTING INC
Controlling and powering multiple chips
ActiveUS12627299B2Majority/minority circuitsDigital data processing detailsControl busEmbedded system
An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.
Owner:AURADINE INC
Semiconductor device
PendingUS20250158621A1Reliability increasing modificationsMajority/minority circuitsDevice materialSwitching signal
A novel semiconductor device or the like is provided. The semiconductor device that includes a first flip-flop having a function of retaining input data in response to a clock signal and outputting first output data based on the input data; a second flip-flop having a function of retaining the input data in response to the clock signal and outputting second output data based on the input data; a third flip-flop having a function of retaining the input data in response to the clock signal and outputting third output data based on the input data; a majority circuit to which the first output data to the third output data are input and having a function of determining the most common logical value in the first output data to the third output data by majority decision making and outputting data of the determined logical value as fourth output data; and a switching circuit to which the first output data and the fourth output data are input and having a function of outputting output data based on the first output data or the fourth output data in response to a switching signal.
Owner:SEMICON ENERGY LAB CO LTD
Majority logic device, photoelectric conversion device, optical communication logic device, and control method for a majority logic device
A majority-decision logic device 1 comprises a non-magnetic semiconductor layer 10 made of a material that, when irradiated with light having at least two kinds of mutually different polarization states, generates electron spin waves having different phases corresponding to the polarization states. The non-magnetic semiconductor layer 10 comprises: three or more input portions to which a light signal is input; and at least one output portion that outputs a result of interference of the electron spin waves. The length of the distance between adjacent input portions as projected in the direction of vibration of the electron spin waves is an integer multiple of the wavelength of the electron spin waves.
Owner:THE JAPAN SCI & TECH AGENCY
Multiplier with non-linear polar material
ActiveUS12308837B1Majority/minority circuitsDigital data processing detailsMajority logicControl theory
A new class of multiplier cells (analog or digital) is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from first and second majority gates. The multiplier cell can also be implemented with a combination of two majority gates with majority and AND functions integrated in each of them. The two majority gates are coupled. Each of the first and second majority logic gates comprise a capacitor with non-linear polar material. The first and second majority gates receive the two inputs A and B that are to be multiplied. Other inputs received by the first and second majority gates are carry-in input, a sum-in input, and a bias voltage. The bias voltage is a negative voltage, which produces an integrated AND function in conjunction with a majority function. The second majority gate receives additional inputs, which are inverted output of the first majority gate.
Owner:KEPLER COMPUTING INC
Most voting circuit
PendingCN119315980AMultiple input and output pulse circuitsMajority/minority circuitsControl signalHemt circuits
The invention provides a majority voting circuit, which is characterized in that a control signal output end output by a comparison circuit is respectively connected with an input end of an internal circulation circuit, a control signal input end of a threshold detection circuit and a control signal input end of a voting circuit, so that the internal circulation circuit can send a received control signal to the voting circuit; the first clock signal and the second clock signal are converted into the corresponding first clock signal and the second clock signal to be output, and the second clock signal is used as a bias voltage to be input to the bias voltage input end of the threshold detection circuit, so that the threshold detection circuit can judge whether to start the voting circuit according to the received bias voltage and the first clock signal; therefore, the bias voltage can be provided for the threshold detection circuit without adopting an additional analog circuit, the detection of the amplitude of the input signal is realized, and the area and the manufacturing cost of the majority voting circuit are further reduced.
Owner:GUANGDONG GREATER BAY AREA INST OF INTEGRATED CIRCUIT & SYST
Asynchronous full-adder with majority or minority gates to generate carry-out false output
Asynchronous full-adder circuit is described. The full-adder includes majority and / or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and / or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.
Owner:KEPLER COMPUTING INC
SFQ-based pulse-conserving logic gates
ActiveUS12206413B2Majority/minority circuitsLogic circuits using superconductive devicesSoftware engineeringInductor
Josephson junction based logic devices and methods for their use are described. An example Josephson junction based logic device includes a two-input OR / AND (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first and second input sources are configured to provide single-flux-quantum (SFQ) pulses. The OA2 gate also includes first plurality of inductors coupled between the first input node and one of: a first output node or a second output node. The OA2 gate additionally includes a second plurality of inductors coupled between the second input node and one of: the first or the second output nodes. The OA2 gate also includes Josephson junctions coupled between a common node and one of: the first or the second input node, or the first or the second output node.
Owner:INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
SFQ-based pulse-conserving logic gates
Josephson junction-based logic devices and methods of use are described. An example of a Josephson junction-based logic device is a two-input OR / AND (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first and second input sources are configured to provide single flux quantum (SFQ) pulses. The OA2 gate also includes a first plurality of inductors coupled between the first input node and one of the first output node or the second output node. The OA2 gate further includes a second plurality of inductors coupled between the second input node and one of the first output node or the second output node. The OA2 gate also includes a Josephson junction coupled between a common node and either the first or second input node or the first or second output node.
Owner:IMEC VESETWAY
Triple modular redundancy flip-flop with improved performance and testability design
ActiveDE602021050226T2Majority/minority circuitsElectric pulse generatorComputer architectureFlip-flop
Owner:QUALCOMM INC
System and method for nanomagnet based adder circuit
ActiveUS12300411B1Majority/minority circuitsSubstrate/intermediate layersSoftware engineeringHemt circuits
A system and method for a device is disclosed. A first logic device and a second logic device are provided. Each of the first logic device and the second logic device include at least three inputs and one output, wherein, the output is based on majority of the inputs. The output of the first logic device is selectively fed to the second logic device, wherein, the first logic device and the second logic device together form an adder circuit.
Owner:CEREMORPHIC INC
Safety protection device
Owner:MITSUBISHI ELECTRIC CORP
Integrated circuit
PCT designated stage expiredWO2025028562A1Majority/minority circuitsElectric pulse generatorComputer hardwareSlave clock
Provided is an integrated circuit capable of maintaining high reliability even under a severe environment such as a high radiation environment. An integrated circuit 1 comprises: a master latch 3 for receiving an input of an input signal, and outputting a signal at a timing based on a master clock signal; and N (N is an odd number of 3 or more) slave latches 4 for receiving an input of the signal outputted from the master latch 3, and outputting an output signal at a timing based on a slave clock signal. The master latch 3 outputs, to the slave latches 4, a signal of a value determined on the basis of the input signal and the input of the outputted signal. Each of the slave latches 4 is configured to output an output signal of a value determined on the basis of a majority decision result of signals respectively outputted from the N slave latches 4 or a majority decision result of signals, which the slave latches 4 have respectively received, as inputs, from the master latch 3.
Owner:UNIV OKAYAMA