35results about "Majority/minority circuits" patented technology

A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and / or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Asynchronous full-adder circuit is described. The full-adder includes majority and / or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and / or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.

A logic gate includes a first capacitor to receive a first input, the first capacitor coupled to a node and a first diode structure coupled to the first input and the node. The logic gate future includes a second capacitor to receive a second input, the second capacitor coupled to the node and a second diode structure coupled to the second input and the node. The logic gate further includes a third capacitor to receive a third input, wherein the third capacitor is coupled to the node and a third diode structure coupled to the third input and the node.

In an embodiment, an integrated circuit (700) includes: a voting circuit (706) including N scan flip-flops (402, 404, 406), where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop (402) and a second scan flip-flop (406), where an output of the first scan flip-flop (402) is coupled to a scan input of the second scan flip-flop (406); a scan chain (720) including the N scan flip-flops (402, 404, 406) of the voting circuit (706), and third (704) and fourth (708) scan flip-flops, the scan chain configured to receive a scan enable signal (scan_en); and a scan enable control circuit (550, 552) configured to control a scan enable input of the first (402) or second (406) scan flip-flops based on the scan enable signal (scan_en) and based on a scan input of the third scan flip-flop (704) or an output of the fourth scan flip-flop (708).

The present invention proposes a server system for improving the pin reuse rate of a programmable device. The system includes a programmable device, a power supply, a first device, and a second device. The programmable device is connected to the power supply, the first device, and the second device. The programmable device includes a main logic communication module, a detection module, a storage module, and a multiplexing pin. The main logic communication module is connected to the first device via the multiplexing pin. The detection module is connected to the second device via the multiplexing pin, and the storage module is connected to the detection module. The multiplexing pin is used to receive an in-place signal sent when the second device is powered on and to send the in-place signal to the detection module. The detection module is used to send the in-place signal to the storage module, and the storage module stores the in-place signal. The main logic communication module is used to communicate with the first device via the multiplexing pin. The present application improves the pin reuse rate. The present invention also provides a method for improving the pin reuse rate of a programmable device.

A majority-decision logic device 1 comprises a non-magnetic semiconductor layer 10 made of a material that, when irradiated with light having at least two kinds of mutually different polarization states, generates electron spin waves having different phases corresponding to the polarization states. The non-magnetic semiconductor layer 10 comprises: three or more input portions to which a light signal is input; and at least one output portion that outputs a result of interference of the electron spin waves. The length of the distance between adjacent input portions as projected in the direction of vibration of the electron spin waves is an integer multiple of the wavelength of the electron spin waves.

An operating method of a chaotic computer including a chaotic logic device includes setting a first initial value based on a first initial state corresponding to a first logical operation, applying the set first initial value to the chaotic logic device, setting a first input value to be applied to the chaotic logic device based on first input data, applying the first input value to the chaotic logic device, generating a chaos signal to have the chaotic logic device operate in a chaotic mode, applying the chaos signal to the chaotic logic device, and measuring a first output value from the chaotic logic device operating based on the first input value and the chaos signal, and generating first output data based on the first output value. The chaotic logic device includes a magnetic thin film configured to have spin soliton formed therein.

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and / or minority gates. The majority and / or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and / or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and / or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

A system and method for single cycle binary matrix multiplication in neural network computations is disclosed. The system includes a memory array storing binary weights, an input unit for activating rows based on a binary activation vector, and per-column majority sense amplifiers. The system performs binary matrix multiplication in a single cycle, enabling efficient implementation of binary neural networks. The memory array may include sections for weights and inverse weights, with corresponding activation register sections. Differential sense amplifiers may implement the majority function. The system can be applied to convolutional neural networks, using SRAM arrays for image storage and processing. Methods for determining majority votes and counting activated bits using iterative modification of the activation vector are also described.

Asynchronous full-adder circuit is described. The full-adder includes majority and / or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and / or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

A majority-decision logic device 1 comprises a non-magnetic semiconductor layer 10 made of a material that, when irradiated with light having at least two kinds of mutually different polarization states, generates electron spin waves having different phases corresponding to the polarization states. The non-magnetic semiconductor layer 10 comprises: three or more input portions to which a light signal is input; and at least one output portion that outputs a result of interference of the electron spin waves. The length of the distance between adjacent input portions as projected in the direction of vibration of the electron spin waves is an integer multiple of the wavelength of the electron spin waves.

Asynchronous full-adder circuit is described. The full-adder includes majority and / or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and / or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.

Josephson junction-based logic devices and methods of use are described. An example of a Josephson junction-based logic device is a two-input OR / AND (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first and second input sources are configured to provide single flux quantum (SFQ) pulses. The OA2 gate also includes a first plurality of inductors coupled between the first input node and one of the first output node or the second output node. The OA2 gate further includes a second plurality of inductors coupled between the second input node and one of the first output node or the second output node. The OA2 gate also includes a Josephson junction coupled between a common node and either the first or second input node or the first or second output node.

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit (104) includes a data storage element (206) to store a data value, another data storage element (202) to store a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element, (204)) to store both the data value and the complementary data value, and voting logic (124) that may enable a complementary data storage scheme with inter-circuit redundancy to prevent SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and / or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.

Technologies for majority gates are disclosed. In one embodiment, a ferroelectric layer has three inputs and an output adjacent a surface of the ferroelectric. When a voltage is applied to each input, the inputs and a ground plane below the ferroelectric layer form a capacitor. The ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer near the output becomes polarized in the direction of polarization of the majority of the inputs. The output voltage then reflects the majority voltage of the inputs.

This invention comprises an integrated circuit in CMOS technology which can act as a regular sequential logic latch, having one data signal input, or as a voting latch, having three data signal inputs. The circuit schematic of this integrated circuit is such that it allows for a certain placement of the devices in the physical, manufactured integrated circuit that makes it possible to optimize the arrangement of the n-type MOSFET devices and p-type MOSFET devices in the circuit independently, using the Layout Optimization through Error Aware Positioning (LEAP), and thereby to remove, or reduce, the occurrence of radiation generated soft errors.

Asynchronous full-adder circuit is described. The full-adder includes majority and / or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and / or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.

A magnetic artificial honeycomb lattice is provided. The magnetic artificial honeycomb lattice includes a multiplicity of connecting elements separated by hexagonal cylindrical pores. The (a) hexagonal cylindrical pores (i) have widths that are substantially uniform; and (ii) are substantially equispaced. The (b) connecting elements includes a magnetic material layer. The connecting elements have: (i) lengths that are substantially uniform; (ii) widths that are substantially uniform; and (iii) a thickness of the magnetic material layer that is substantially uniform and an average thickness. The magnetic artificial honeycomb lattice is configured to receive two input currents and configured to output an output voltage based upon the two input currents.

A ferroelectric device and a wave computing device are provided. The ferroelectric device includes a first electrode, a second electrode, a ferroelectric layer and a wave guide. The ferroelectric layer is disposed between the first and second electrodes, and configured to transduce an electrical wave signal to a varying mechanical stress by piezoelectricity, or vice versa. A first polarization state or a second polarization state opposite to the first polarization state is programmed in the ferroelectric layer. The wave guide is in contact with the ferroelectric layer, and configured to transmit a wave signal resulted from or resulting the varying mechanical stress. The wave signal is in phase with the electrical wave signal when the ferroelectric layer is programmed with the first polarization state. The wave signal is out of phase with the electrical wave signal when the ferroelectric layer is programmed with the second polarization state.

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

A ferroelectric device and a wave computing device are provided. The ferroelectric device includes a first electrode, a second electrode, a ferroelectric layer and a wave guide. The ferroelectric layer is disposed between the first and second electrodes, and configured to transduce an electrical wave signal to a varying mechanical stress by piezoelectricity, or vice versa. A first polarization state or a second polarization state opposite to the first polarization state is programmed in the ferroelectric layer. The wave guide is in contact with the ferroelectric layer, and configured to transmit a wave signal resulted from or resulting the varying mechanical stress. The wave signal is in phase with the electrical wave signal when the ferroelectric layer is programmed with the first polarization state. The wave signal is out of phase with the electrical wave signal when the ferroelectric layer is programmed with the second polarization state.

A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and / or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Provided is a semiconductor device having a novel structure. This semiconductor device comprises: a first flip-flop having a function to hold input data in accordance with a clock signal and to output first output data that is in accordance with the input data; a second flip-flop having a function to hold the input data in accordance with the clock signal and to output second output data that is in accordance with the input data; a third flip-flop having a function to hold the input data in accordance with the clock signal and to output third output data that is in accordance with the input data; a majority vote circuit to which the first output data to the third output data are inputted and that has a function to determine the logic value that is the most abundant in the first output data to the third output data by majority vote and to output the data of the determined logic value as fourth output data; and a switch circuit to which the first output data and the fourth output data are inputted and that has a function to output output data that is in accordance with the first output data or the fourth output data in accordance with a switch signal.

Asynchronous full-adder circuit is described. The full-adder includes majority and / or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and / or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.

This disclosure describes various aspects of complementary 2(N) bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit (104) includes a data storage element (206) to store a data value, another data storage element (202) to store a complementary data value, a multi-bit data storage element (e.g., 2-bit storage element (204)) to store both the data value and the complementary data value, and voting logic (124) that can enable a complementary data storage scheme with inter-circuit redundancy for preventing SEUs. Additionally, the voting logic of the integrated circuit can implement detection and correction of data value errors and / or implement programming of voting logic criteria, which can be dynamically implemented based on the type of SEU fault detected or corrected.

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and / or minority gates. The majority and / or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and / or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and / or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

This invention provides a self-verifying data voting system, including an input verification unit, an output logic unit, an output verification unit, and a verification processing unit. Both the input and output verification units incorporate an XOR unit, a multi-channel dual-track code verifier, and a code verifier. By performing an XOR operation on two different bits of the input data, and then combining this with the multi-channel dual-track code verifier to generate a randomized test set, the code verifier can obtain a complete test code, avoiding the loss of test information. The verification processing unit determines the state of the data voting system and the processing method based on the second verification result of the input verification unit and the fifth verification result of the output verification unit. This achieves verification of both the input data and the data voting system itself, realizing true self-verification and improving the reliability of the electronic system.