A logic circuit includes an input for one or several input operands, an output for a result and an inverted result, a first circuit branch with a first logic assembly, which is coupled to the input and the output, to calculate the result, as well as a second circuit branch with a second logic assembly, which is coupled to the input and the output, to calculate the inverted result, wherein the first logic assembly and the second logic assembly have different run times for calculating the result and the inverted result, respectively. Further, a delay circuit and a compensation circuit, respectively, are provided in the first and/or second circuit branch to reduce a difference of the run times and the power consumptions, respectively, of the first and the second circuit branch.