113 results about "Clock recovery" patented technology

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

The invention discloses an LPO wired receiver adopting adaptive CTLE based on a genetic algorithm, and the receiver comprises an analog front end, a data sampler, an edge sampler, an error sampler, a 1: 32 demultiplexer, a verification module, an eye pattern monitor, a genetic algorithm module, clock recovery logic, and a clock path. The eye pattern monitor is used for calculating the eye pattern closure degree according to the data of the data sampler and the error of the error sampler and outputting the eye pattern closure degree to the genetic algorithm module; and the genetic algorithm module is used for realizing parameter adaptive control of a continuous time linear equalizer CTLE and a variable gain amplifier VGA in the analog front end. The invention aims to apply the genetic algorithm to the adaptive equalization of the adaptive continuous time linear equalizer, so that the adaptive continuous time linear equalizer has stronger global search capability and lower power consumption and is not easy to fall into local optimum, and the complexity and power consumption of the adaptive continuous time linear equalizer are reduced. And the real-time and energy-saving requirements are met.

The invention relates to the technical field of serial communication, in particular to a high-speed clock recovery method and device based on an adjustable delay chain, and the method comprises the steps: generating a recovery clock initial phase; a multi-stage programmable delay chain is adopted, and a phase-locked loop or delay-locked loop structure is combined, so that the initial phase of a recovered clock is finely adjusted and locked, and phase capture and clock edge alignment are performed; based on a multi-path recovery structure, a path with the minimum error is selected from the delay paths through a preset phase error detection mechanism to serve as an output channel; environment parameters of the environment are collected, parameters of the multi-stage programmable delay chain are dynamically adjusted, and high-speed clock recovery is completed. According to the method, the edge capture precision, the system jitter tolerance and the working frequency range of the recovered clock are remarkably improved, and then the phase consistency, the anti-interference capability and the overall data receiving reliability of the recovered clock in the high-speed communication system are effectively improved.

A test and measurement device has an input port to receive a signal from a device under test (DUT), the signal having a symbol rate, one or more analog-to-digital converters (ADC) to convert the signal to waveform samples at a sampling rate, and one or more processors, when aliasing is present: up-sample a portion of the signal having aliased samples to produce up-sampled samples; use the up-sampled samples to produce a real-time waveform; perform clock recovery on the real-time waveform to produce a recovered clock; and resample the aliased samples to produce a non-aliased waveform.

The invention discloses an optical fiber wireless heterogeneous network intelligent monitoring system and method based on energy-information co-transmission, and relates to the technical field of optical fiber wireless heterogeneous network intelligent monitoring, the system comprises a central base station unit, an energy-information co-transmission optical fiber transmission unit and a micro-nano integration unit; the central base station unit is integrated with a high-power laser with a first preset wavelength, a light receiving unit with a second preset wavelength and a data processing subunit; the high-power laser is used for generating an optical signal for transmitting energy; the light receiving unit is used for receiving monitoring data; the data processing subunit is used for realizing clock recovery, code element synchronization, serial decoding and data display functions; and the energy-information co-transmission optical fiber transmission unit takes a multi-core optical cable as a physical carrier and adopts a wavelength division multiplexing technology to realize isolated transmission of energy and information, one end of the energy-information co-transmission optical fiber transmission unit is in communication connection with the central base station unit, and the other end of the energy-information co-transmission optical fiber transmission unit is in communication connection with each micro-nano integrated monitoring unit.

The invention discloses a video clock recovery method and device, a storage medium and electronic equipment, and the method comprises the steps: extracting a video time sequence parameter from an auxiliary information packet when the auxiliary information packet transmitted by a transmitting end is received; configuring a phase-locked loop according to the video time sequence parameter, and generating a video clock; when the video data is received, counting the actual clock number of each video line by using a video clock so as to obtain the current clock error of each video line; performing coarse adjustment on the video clock according to the current clock error until the video clock is initially converged; and performing fine adjustment on the video clock after preliminary convergence until the video clock reaches a stable state. According to the invention, the precision of video clock recovery can be improved.

The invention relates to the technical field of USB audio equipment optimization, and discloses a USB audio equipment Device mode implementation method and system, a storage medium and equipment, and the method comprises the steps: dynamically recognizing a connection type through detecting a USB data line voltage threshold value, and dynamically loading a corresponding protocol stack module based on the connection type; in a Device mode, a multi-stage buffer mechanism is adopted to manage audio data streams, the number and size of buffer areas are dynamically allocated according to target delay time, and clock synchronization with a host is realized based on an adaptive clock recovery algorithm; the power consumption of the equipment is dynamically adjusted through a multi-stage power consumption state machine, switching is carried out among working states according to an audio activity state and a data transmission requirement, and a remote wakeup function is supported; according to the method, a compatibility strategy library is matched based on a device fingerprint recognition result, protocol characteristics and audio formats of different host devices are automatically adapted, meanwhile, audio playing is controlled through audio quality monitoring and self-optimization, and Device mode support is added to the USB audio device through the method.

The invention relates to the field of high-speed serial interface chips, and discloses an error calibration method of an ultra-high-speed phase interpolator. The method comprises the steps of amplitude calibration, edge searching, reference clock delay calibration, multi-phase cyclic calibration, linear interpolation and the like, a reference clock rising edge zero crossing point is used as a high-precision time reference, delay control words of a selected discrete phase are adjusted one by one, a mapping lookup table covering a full-phase range is generated through linear interpolation, and the time delay control words of the selected discrete phase are adjusted one by one. And compensation of the nonlinear error of the phase interpolator is realized. According to the invention, high-precision linearity calibration can be completed before normal operation of the chip, the clock recovery precision is significantly improved, the nonlinear error is reduced from + / -1.5 LSB to + / -0.5 LSB, the error rate of the system is reduced, and the power consumption and the area overhead are low.

The invention discloses a multi-protocol self-adaptive management docking station core board control method and system, and belongs to the technical field of docking station core board monitoring control, and the method comprises the steps: analyzing the stability risk analysis necessity of a docking station core board, analyzing the stability risk score of the docking station core board, and determining the stability risk of the docking station core board; and performing control optimization adjustment on the docking station core board based on the stability risk score of the docking station core board, performing protocol layer clock recovery circuit sampling phase drift analysis, analyzing a protocol layer clock recovery circuit sampling phase drift characterization factor, and executing control adjustment of sampling phase drift. According to the method, the stability and reliability of system operation can be improved, the link retraining frequency is reduced, sampling phase adjustment is optimized, sampling point dislocation, inter-frame phase lock out-of-step and systematic communication faults are prevented under the condition of multi-protocol concurrent working, and long-term stable operation and multi-protocol compatibility of the docking station core board are guaranteed.

Provided are a wired transmission time division duplex system and a node device thereof. The node device comprises a receiver configured to receive a data frame; a transmitter configured to send a processed data frame; a frame header detection circuit configured to identify a frame header and a preamble in a non-return-to-zero coding format from the data frame based on a specific code sequence, and obtain frame header information accordingly, and detect a level jump edge in the frame header and the preamble, and output a reference clock signal based on the detection result; and a clock and data recovery circuit configured to map a multi-level digital signal of a data segment after the frame header and the preamble into binary data bits using a corresponding pulse amplitude modulation format based on the frame header information, and recover a local receiving clock based on the reference clock signal. The slave node device effectively overcomes the synchronization difficulty and slow clock recovery in a multi-level pulse amplitude modulation system.

The application discloses a kind of self-adapting nonlinear impairment compensation methods based on low-cost optical performance monitoring, and its technical scheme main points are as follows: in transmitting end, low-speed mark is modulated to the envelope of high-speed data signal on top signal;A section of zero-power gap is inserted into signal, after digital-analog conversion and electro-optical conversion are successively carried out to data, into optical fiber link;In receiving end, the signal received is successively carried out photoelectric conversion, analog-digital conversion, IQ orthogonalization, clock recovery;Combining the step number of FD-Volterra-CDE back propagation process in different optical transmission link state parameter range N span Nonlinear effect introduced by the calculation of nonlinear impairment causes optical signal-to-noise ratio penalty;The adaptive nonlinear impairment compensation method in the application solves the problem of too high calculation complexity in the traditional nonlinear impairment compensation process, and by establishing the LUT of the step number N step , filter number N k In the process of FD-Volterra-CDE back propagation in different optical transmission link state parameter range, the calculation complexity is effectively reduced while the compensation accuracy is guaranteed.

The embodiment of the invention provides a CBR service clock rate recovery method. The method comprises the following steps: receiving an OSU frame; the OSU frame carries timestamp information of the CBR service signal, and the timestamp information comprises a timestamp difference value for transmitting the CBR service signal; sampling the OSU frame through a frequency divider, and counting an accumulated timestamp difference value and an accumulated local clock period number in a sampling period number; and recovering the CBR service clock rate according to the sampling period number, the accumulated timestamp difference value and the accumulated local clock period number. Compared with an existing CBR clock recovery technology, step-by-step recovery is not needed, the clock recovery performance is greatly improved, the complexity is greatly reduced, the precision is greatly improved based on point-to-point recovery, and the problems that in long-distance service transmission cascading in the related technology, step-by-step recovery is needed, offset exists in the step-by-step clock recovery process, and the clock recovery efficiency is poor are solved. And the finally recovered clock performance loss is caused.

A system includes a crystal oscillator, a central switch transceiver coupled to the crystal oscillator, and a sensor transceiver. The central switch transceiver includes transmitter circuitry to generate a self- clocked signal carrying first data using a timing reference from the crystal oscillator, and clock and data recovery loop circuitry to operate at a first bandwidth to sample second data received from the sensor transceiver. The sensor transceiver includes reference clock recovery circuitry to decode a reference clock from the self- clocked signal. A phase-locked loop (PLL) circuit generates a transmission clock operating at a second bandwidth from the reference clock for generating the second data. The first bandwidth is greater than or equal to the second bandwidth of the PLL circuit to mitigate jitter experienced by the clock and data recovery loop circuitry due to jitter in the transmission clock.

This invention discloses a code-assisted baud rate sampling clock recovery method and system, applicable to the field of optical fiber communication technology. The method includes the following steps: performing matched filtering on the received signal; using the M&M algorithm to complete primary clock recovery on data from an oscilloscope to obtain baud rate sampling data; performing equalization processing on the baud rate sampling data; using a belief propagation algorithm to decode the equalized baud rate sampling data and output reliability estimation information; modulating the reliability estimation information of each baud rate sampling data into a PAM4 auxiliary symbol according to the PAM4 mapping rule; using the PAM4 auxiliary symbol to replace the decision symbol in the M&M algorithm to re-estimate the clock error and perform high-precision clock recovery. This invention, by combining primary and auxiliary clock recovery stages, significantly reduces the bit error rate and provides more stable clock synchronization in high data rate scenarios.

The invention relates to the technical field of electronic system time sequence control, in particular to a multi-system clock synchronization method based on a low-frequency calibration clock, which is characterized in that a main system adopts a high-stability clock source and simultaneously generates a high-frequency data clock and the low-frequency calibration clock of which the frequency is less than one thousandth of that of the data clock through a clock management unit; the characteristics of strong anti-interference and high transmission quality of the low-frequency clock are utilized, and the low-frequency clock is sent to each slave system through the optimized clock distribution network. Each slave system extracts a low-frequency calibration clock through a clock recovery circuit, a high-precision time interval measurement unit is adopted to measure the time difference between a local clock and the calibration clock, and the measurement precision and stability are improved through digital signal processing. And each slave system inputs the time difference as a control quantity into a digital regulation system, dynamically regulates the phase of a local clock, and judges a synchronous locking state through a locking state detection mechanism, thereby realizing high-precision, long-term and stable clock synchronization among multiple systems.

The invention relates to the technical field of wireless communication networks, and discloses a wireless communication anti-interference method of an avionics system, which comprises the following steps: nodes in a network autonomously and synchronously switch channels based on a shared key and a public time reference, and when the public time reference is invalid, a mobile node calibrates a local clock by monitoring the channel switching time of a central node, according to the method, synchronization can be achieved without real-time signaling, interference can be avoided, the problem of network lock losing caused by coordination signaling failure is solved, when the external public time reference is lost, the hopping behavior of the network itself is used as an internal clock beacon, the nodes can be self-healed to recover synchronization, and the reliability of avionics communication is ensured.

The invention discloses a high-precision low-jitter clock recovery method, relates to the field of digital signal processing, and solves the problem of inaccuracy during clock jitter deviation recovery. Preprocessing the original clock signal and generating a corresponding square wave diagram based on the preprocessed processing clock signal; the clock fluctuation period of the processing clock signal is analyzed based on the square wave diagram, and the existence condition of the jitter deviation corresponding to the processing clock signal is judged; calculating the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period in combination with the square wave diagram; inputting a processing clock signal into the ultrafast clock fan-out buffer, and performing comprehensive jitter recovery on the clock jitter deviation of the clock fluctuation period; and calculating the proportion of the processing clock signal output by the ultrafast clock fan-out buffer, and judging the validity of the ultrafast clock fan-out buffer. The method and the device provided by the invention realize accurate identification and recovery of the clock jitter deviation.

The application relates to the technical field of wireless communication networks, and discloses a wireless communication anti-interference method for an avionics system, which comprises the following steps: nodes in a network autonomously synchronize channel switching based on a shared key and a public time reference; when the public time reference is invalid, a mobile node calibrates a local clock by monitoring the channel switching time of a central node to restore synchronization; the application can avoid interference by synchronizing without real-time signaling, solves the network lockout problem caused by invalid coordination signaling, and ensures the reliability of avionics communication by using the hopping behavior of the network itself as an internal clock beacon to enable the nodes to self-recover and synchronize when an external public time reference is lost.

Apparatus and methods for discovery, synchronization and operation of network components. In one embodiment, the network comprises a passive optical network (PON), and the components being synchronized include an enhanced OLT (eOLT) and one or more enhanced ONUs (eONUs). The eOLT is configured in one variant to utilize control protocol messaging (such as those used in the MPCP or Multi Point Control Protocol) to communicate particular synchronization parameters and durations to the eONU(s), whether individually or via multicast / broadcast. The synchronization parameter and durations are selected to optimize discovery and synchronization of the eONU(s) with the eOLT, and also optimize (subsequent) normal operation, in one implementation through selection of synchronization patterns which enable most efficient AGC determination, clock recovery (CDR), SBD, and EBD identification.

A clock recovery loop in a digital signal processor for a serializer-deserializer data interface can be modified to achieve fractional lock and operate in a sampling scope mode. The clock recovery loop can control a phase locked loop to produce a clock signal that is at a rational fraction of a baud rate. The clock signal can be used by time-interleaved analog-to-digital converters to achieve oversampling of a periodic signal received over a receive channel. The samples can be used to reconstruct a continuous time signal bit response to characterize or debug the receive channel.

The application belongs to the technical field of optical fiber communication, and discloses an optical fiber transmission link quality monitoring and dispersion compensation optimization method and system, which comprises the following steps: extracting an error vector amplitude, an optical signal-to-noise ratio and constellation distortion features from a coherent receiver and fusing them into a comprehensive quality evaluation index; jointly estimating residual dispersion by using a clock recovery phase and equalizer coefficient distribution; adopting a variable step gradient descent to adaptively optimize dispersion compensation filter parameters; performing performance degradation trend analysis and early warning; and jointly monitoring and cooperatively optimizing multiple wavelength channels.

A system includes an optical transmitter configured to modulate a pulsed laser signal based on a plurality of data signals to form a plurality of modulated optical data signals, perform optical time division multiplexing of the plurality of modulated optical data signals to obtain a multiplexed optical data signal, and transmitting the multiplexed optical data signal together with an optical clock signal derived from the pulsed laser signal; and an optical receiver comprising a clock recovery branch configured to recover the optical clock signal to a plurality of phase shift recovered optical clock signals and a data branch having a plurality of saturable absorbers (SAs), each SA being in optical communication with one of the phase shift recovered optical clock signals, and configured to receive the multiplexed optical data signal and to transmit one of the plurality of modulated optical data signals according to the recovered optical clock signal.

The application discloses a method for automatically identifying and matching a 5G front transmission network interface, and belongs to the technical field of computers.The method comprises the following steps: a QSFP interface detection step and an SFP interface detection step.The method adopts a receiving side clock phase-locked loop adaptive configuration technology, a clock recovery circuit automatic adjustment and sampling technology and an encoding error code detection technology, and realizes the functions of fast automatic scanning and matching of port rate, line encoding and frame protocol by judging whether the following conditions are normal: PLL locking, frequency deviation range, short-time frequency stability, encoding without exception and frame synchronization, so that the testing and troubleshooting time of the 5G front transmission interface is greatly shortened.

The invention discloses a method and system for recovering a clock at a VOIP receiving end through an FPGA, and relates to the field of clock recovery. The method for recovering the clock at the VOIP receiving end through the FPGA comprises the steps that a sending end packages source data transmitted by a falling edge of a source clock into a message and then transmits the message to the receiving end; a receiving end extracts source data in the message and stores the source data in a receiving buffer area; outputting a recovery clock by adopting a clock control algorithm according to the change of the number of the data in the receiving buffer area, and outputting the data in the receiving buffer area through the rising edge of the recovery clock; the clock control algorithm introduces the data transmission rate and the maximum network jitter delay of a source clock. According to the method, the accuracy and the stability of clock recovery can be improved, the influence of the maximum network jitter time delay is solved, and meanwhile, the operation scale of an algorithm is reduced.

This invention proposes a low-complexity time-domain parallel clock recovery method based on a 4 / 3 sampling rate. First, a new error extraction model is proposed. Interpolation processing based on a sinusoidal interpolation algorithm is introduced to achieve clock offset compensation. Next, loop filtering and NCO parallel processing are designed specifically for 4 / 3 symbol rate sampling. After interpolation, redundant sampling points are removed through decision making and elastic buffering. Finally, a sinusoidal interpolation algorithm with fixed interpolation coefficients is used to recover the optimal sampling points under 4 / 3 symbol rate sampling, achieving reliable and accurate recovery of transmitted information. This method can achieve high-precision and high-stability parallel time-domain clock recovery in a 4 / 3 symbol rate sampling receiving system, making it particularly suitable for resource-constrained and limited satellite communication systems.

The application relates to an improved ABSPD clock recovery method under single baud rate sampling, clock synchronization of transceiving end signals is realized through a full-digital type clock recovery loop, a timing error detector is used to replace numerical multiplication operation with symbol judgment and shift operation when calculating timing error e; after the timing error e is calculated by the timing error detector, the timing error e is input into a loop filter to remove noise and control words W are obtained; then the control words W are used to control a digital controlled oscillator, fractional interval mu k is calculated from the output NCO of the digital controlled oscillator and the control words W k The integer mark m k of the symbol and the calculated fractional interval mu k The received signal is interpolated in an interpolation filter, so that timing correct data are calculated. The application realizes ABSPD clock recovery under single baud rate sampling without multiplication operation, and significantly reduces the complexity of the whole clock recovery loop.

The embodiment of the invention provides a clock recovery method and device based on burst data and an optical line terminal. The method comprises the following steps: under the condition that a first lead code sent by ONU equipment is received in a stream sending stage, setting a CDR loop to be in an open loop mode, so as to sample a second lead code sent by the ONU equipment based on a local clock, and adjust a sampling phase of the local clock based on the second lead code to generate a first recovery clock; and sampling a third preamble sent by the ONU equipment based on the first recovery clock, and setting the CDR loop to be in a closed loop mode, so as to circularly adjust the locking bandwidth of the CDR loop in stages to generate a second recovery clock, so that the phase of the second recovery clock is consistent with the phase of a sending clock of the ONU equipment. According to the method and the device, the problem of quick recovery of the burst data is at least solved, so that the effects of reducing data dependence and realizing quick recovery of the burst data are achieved.

The invention relates to an analog-to-digital converter background calibration system and method, and the system comprises a multiplier, an equalization and judgment module, an adaptive module, a clock recovery module, a phase error calibration module, and a gain calibration module. The adaptive module is used for adaptively generating a signal amplitude and a judgment amplitude according to q data and e data output by the equalization and judgment module; the equalization and judgment module outputs the data q and the data e according to the output signal of the multiplier, the gain adjustment signal, the signal amplitude and the judgment amplitude; the clock recovery module outputs a phase control signal according to the q data and the e data and provides the phase control signal to a phase adjustment circuit; the phase error calibration module outputs a phase error control signal according to the q data and the e data and provides the phase error control signal to the phase adjustment circuit; and the gain calibration module outputs the gain adjustment signal according to the q data and the e data and provides the gain adjustment signal to the multiplier.

A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.

The invention discloses a clock data recovery circuit applied to a multi-channel array high-speed SerDes receiver. A half-rate decision feedback equalizer carries out signal recovery processing on an original analog signal input in a current period according to a first target sampling clock output from a clock network in a previous period and outputs a digital serial signal; the target sampler carries out sampling processing on the digital serial signal according to a second target sampling clock output from the clock network in the previous period and outputs serial judgment data; the demultiplexer carries out parallel processing on the digital serial signals and the serial judgment data according to a third target sampling clock output from the clock network in the previous period and outputs multiple paths of parallel signals; the clock recovery module generates a target four-phase clock according to the local clock signal and the multi-path parallel signal; and the clock network generates a first target sampling clock, a second target sampling clock and a third target sampling clock of the next period according to the target four-phase clock. The clock data recovery circuit has the advantages of low power consumption and high speed.