170 results about "Clock recovery" patented technology

The invention is suitable for the technical field of signal testing, and provides a high-speed serial signal testing method and system and semiconductor testing equipment, and the high-speed serial signal testing method comprises the steps: carrying out the time sequence adjustment of a testing signal through a phase-adjustable clock reference, actively introducing controllable jitter, and carrying out the jitter tolerance testing; a target test signal is sent to a receiving end through an emission driver, after a receiving signal is obtained, a target sampling time sequence is extracted based on clock recovery, a programmable receiving delay chain is controlled to carry out time scanning, and receiving data at multiple sampling moments are obtained; comparing each sampling data with the test signal, counting the bit error rate under each delay setting, and completing signal quality evaluation; the scheme has the advantages of modularization, high precision, low cost and the like, and the comprehensive test efficiency and reliability of the semiconductor test equipment on high-speed serial signals are improved.

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

An oscilloscope having a Nyquist frequency lower than an analog bandwidth includes an input configured to receive a signal under test; an analog-to-digital converter (ADC) to receive the signal under test, sample the signal under test at a sample rate, and produce digital samples of the signal under test; one or more processors configured to execute code that causes the one or more processors to: determine a set of candidate unit intervals by generating corresponding candidate histograms using the candidate unit intervals; determine a best unit interval from the candidate unit intervals based upon entropy measures of each candidate histogram; and reconstruct a representation of the signal under test using the digital samples and the best unit interval.

The invention discloses an LPO wired receiver adopting adaptive CTLE based on a genetic algorithm, and the receiver comprises an analog front end, a data sampler, an edge sampler, an error sampler, a 1: 32 demultiplexer, a verification module, an eye pattern monitor, a genetic algorithm module, clock recovery logic, and a clock path. The eye pattern monitor is used for calculating the eye pattern closure degree according to the data of the data sampler and the error of the error sampler and outputting the eye pattern closure degree to the genetic algorithm module; and the genetic algorithm module is used for realizing parameter adaptive control of a continuous time linear equalizer CTLE and a variable gain amplifier VGA in the analog front end. The invention aims to apply the genetic algorithm to the adaptive equalization of the adaptive continuous time linear equalizer, so that the adaptive continuous time linear equalizer has stronger global search capability and lower power consumption and is not easy to fall into local optimum, and the complexity and power consumption of the adaptive continuous time linear equalizer are reduced. And the real-time and energy-saving requirements are met.

The invention discloses an optical fiber signal transmission system and method based on quantum noise encryption, and relates to the technical field of optical fiber communication, and the system comprises a composite modulation transmitting module, a dispersion compensation relay module, a coherent receiving module and a digital signal processor. The composite modulation transmitting module comprises an electro-optical modulator and a quantum noise randomization encoder; the dispersion compensation relay module comprises an adjustable dispersion compensator and a Raman amplifier; the coherent receiving module comprises a local oscillator laser and a 90-degree optical mixer; a digital signal processor includes a clock recovery unit and a maximum likelihood sequence detector. All the modules are sequentially connected and cooperatively work. And the adjustable dispersion compensator dynamically applies reverse dispersion compensation calculated based on a dispersion coefficient and a transmission distance according to the dispersion amount monitored in real time. According to the invention, through technologies of quantum noise encryption, dynamic dispersion compensation, Raman amplification, coherent reception and the like, safe and efficient transmission with single-wave 400Gbps and 100km transmission bit error rate less than or equal to 1 * 10 <-12 > is realized.

The invention relates to the technical field of serial communication, in particular to a high-speed clock recovery method and device based on an adjustable delay chain, and the method comprises the steps: generating a recovery clock initial phase; a multi-stage programmable delay chain is adopted, and a phase-locked loop or delay-locked loop structure is combined, so that the initial phase of a recovered clock is finely adjusted and locked, and phase capture and clock edge alignment are performed; based on a multi-path recovery structure, a path with the minimum error is selected from the delay paths through a preset phase error detection mechanism to serve as an output channel; environment parameters of the environment are collected, parameters of the multi-stage programmable delay chain are dynamically adjusted, and high-speed clock recovery is completed. According to the method, the edge capture precision, the system jitter tolerance and the working frequency range of the recovered clock are remarkably improved, and then the phase consistency, the anti-interference capability and the overall data receiving reliability of the recovered clock in the high-speed communication system are effectively improved.

A test and measurement device has an input port to receive a signal from a device under test (DUT), the signal having a symbol rate, one or more analog-to-digital converters (ADC) to convert the signal to waveform samples at a sampling rate, and one or more processors, when aliasing is present: up-sample a portion of the signal having aliased samples to produce up-sampled samples; use the up-sampled samples to produce a real-time waveform; perform clock recovery on the real-time waveform to produce a recovered clock; and resample the aliased samples to produce a non-aliased waveform.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

The invention relates to a high-speed serial interface circuit, and discloses a linearity calibration and precision expansion method of a numerical control phase interpolator. According to the method, a digital delay converter (DDC) is cascaded behind a digital control phase interpolator (DPI), and delay compensation is carried out on an interpolated clock signal; sampling the compensated clock signal by using an analog-to-digital converter (ADC) to obtain a phase sampling value; the calibration control module calculates a phase error and generates a delay control word; when the numerical control phase interpolator DPI works, phase control words and delay control words are synchronously provided for corresponding modules, and linearity calibration and precision expansion are achieved. According to the method, a special detection circuit does not need to be added, hardware resources existing in a high-speed serial interface are utilized, the method can be achieved through simple digital control logic, the phase integral linearity is improved to be within 25 fs from 250 fs, meanwhile, the precision of an 8-bit phase interpolator is improved to be close to the 11-bit level, and the method is suitable for large-scale popularization and application. And the clock recovery performance and the data transmission reliability of the high-speed communication system are obviously improved.

A signal receiving circuit includes first to third pulse generators; and a clock signal recovery unit 100 for generating a recovery clock signal RCLK and a recovery clock delay signal RCLKD, which is a signal obtained by delaying the recovery clock signal as much as a first delay time, using at least one of pulses including a first pulse, a second pulse, a third pulse, and first to third inversion pulses, wherein the clock signal recovery unit includes: a loop interruption circuit including an input node and an output node and turned on and off by at least one of the pulses; and a delay circuit having an input terminal connected to the output node and an output terminal connected to the input node. A signal value of the input node and a signal value of the output node are in an inverse relationship.

The invention discloses an optical fiber wireless heterogeneous network intelligent monitoring system and method based on energy-information co-transmission, and relates to the technical field of optical fiber wireless heterogeneous network intelligent monitoring, the system comprises a central base station unit, an energy-information co-transmission optical fiber transmission unit and a micro-nano integration unit; the central base station unit is integrated with a high-power laser with a first preset wavelength, a light receiving unit with a second preset wavelength and a data processing subunit; the high-power laser is used for generating an optical signal for transmitting energy; the light receiving unit is used for receiving monitoring data; the data processing subunit is used for realizing clock recovery, code element synchronization, serial decoding and data display functions; and the energy-information co-transmission optical fiber transmission unit takes a multi-core optical cable as a physical carrier and adopts a wavelength division multiplexing technology to realize isolated transmission of energy and information, one end of the energy-information co-transmission optical fiber transmission unit is in communication connection with the central base station unit, and the other end of the energy-information co-transmission optical fiber transmission unit is in communication connection with each micro-nano integrated monitoring unit.

The invention discloses a video clock recovery method and device, a storage medium and electronic equipment, and the method comprises the steps: extracting a video time sequence parameter from an auxiliary information packet when the auxiliary information packet transmitted by a transmitting end is received; configuring a phase-locked loop according to the video time sequence parameter, and generating a video clock; when the video data is received, counting the actual clock number of each video line by using a video clock so as to obtain the current clock error of each video line; performing coarse adjustment on the video clock according to the current clock error until the video clock is initially converged; and performing fine adjustment on the video clock after preliminary convergence until the video clock reaches a stable state. According to the invention, the precision of video clock recovery can be improved.

The invention relates to the technical field of USB audio equipment optimization, and discloses a USB audio equipment Device mode implementation method and system, a storage medium and equipment, and the method comprises the steps: dynamically recognizing a connection type through detecting a USB data line voltage threshold value, and dynamically loading a corresponding protocol stack module based on the connection type; in a Device mode, a multi-stage buffer mechanism is adopted to manage audio data streams, the number and size of buffer areas are dynamically allocated according to target delay time, and clock synchronization with a host is realized based on an adaptive clock recovery algorithm; the power consumption of the equipment is dynamically adjusted through a multi-stage power consumption state machine, switching is carried out among working states according to an audio activity state and a data transmission requirement, and a remote wakeup function is supported; according to the method, a compatibility strategy library is matched based on a device fingerprint recognition result, protocol characteristics and audio formats of different host devices are automatically adapted, meanwhile, audio playing is controlled through audio quality monitoring and self-optimization, and Device mode support is added to the USB audio device through the method.

The invention relates to the field of high-speed serial interface chips, and discloses an error calibration method of an ultra-high-speed phase interpolator. The method comprises the steps of amplitude calibration, edge searching, reference clock delay calibration, multi-phase cyclic calibration, linear interpolation and the like, a reference clock rising edge zero crossing point is used as a high-precision time reference, delay control words of a selected discrete phase are adjusted one by one, a mapping lookup table covering a full-phase range is generated through linear interpolation, and the time delay control words of the selected discrete phase are adjusted one by one. And compensation of the nonlinear error of the phase interpolator is realized. According to the invention, high-precision linearity calibration can be completed before normal operation of the chip, the clock recovery precision is significantly improved, the nonlinear error is reduced from + / -1.5 LSB to + / -0.5 LSB, the error rate of the system is reduced, and the power consumption and the area overhead are low.

A clock recovery system for recovering an in-band communication clock in a wireless power transfer system can in include: a phase locked loop; and a bit decision block and a multiplexer that cooperate to selectively provide the error signal to the loop filter responsive to detected bits in the in-band communication bitstream. The phase locked loop can further include: a phase detector that computes an error signal from a difference between an instantaneous peak location and an estimated peak location correlated to a symbol in an in-band communication bitstream; a loop filter that selectively receives the error signal; and a voltage controlled oscillator that adjusts its output frequency responsive to an output of the loop filter.

The invention discloses a multi-protocol self-adaptive management docking station core board control method and system, and belongs to the technical field of docking station core board monitoring control, and the method comprises the steps: analyzing the stability risk analysis necessity of a docking station core board, analyzing the stability risk score of the docking station core board, and determining the stability risk of the docking station core board; and performing control optimization adjustment on the docking station core board based on the stability risk score of the docking station core board, performing protocol layer clock recovery circuit sampling phase drift analysis, analyzing a protocol layer clock recovery circuit sampling phase drift characterization factor, and executing control adjustment of sampling phase drift. According to the method, the stability and reliability of system operation can be improved, the link retraining frequency is reduced, sampling phase adjustment is optimized, sampling point dislocation, inter-frame phase lock out-of-step and systematic communication faults are prevented under the condition of multi-protocol concurrent working, and long-term stable operation and multi-protocol compatibility of the docking station core board are guaranteed.

The present invention relates to a method for processing data related to time information for a controller that may be connected to at least one sensor device, for example, via a first data link, and / or connected to the controller, the method comprising: using a time synchronization protocol for synchronizing a clock device of the controller and a clock device of at least one sensor device in a first time domain; and using a signal for clock recovery for at least one of the following elements in a second time domain different from the first time domain, namely, a) maintaining the synchronization of the clock device of the controller and the clock device of at least one sensor device, and / or b) synchronization of the clock device of the controller and the clock device of at least one sensor device, such as resynchronization.

The present invention relates to the field of optical communication technologies, and discloses an optical clock recovery system and method. The present invention converts an optical signal of a clock to be recovered into an electrical signal, and outputs the electrical signal to a digital signal processing module; outputs a configuration instruction to the digital signal processing module, and when the digital signal configuration rate in the configuration instruction matches the electrical signal, performs signal locking, controls an indication module to perform corresponding locking indication, and configures the digital signal processing module to enable a clock output module to output the recovered clock in the optical signal of the clock to be recovered. The present invention has the technical effects of supporting single-mode and multi-mode optical signal input, fast signal locking, stability, and small output clock jitter.

Provided are a wired transmission time division duplex system and a node device thereof. The node device comprises a receiver configured to receive a data frame; a transmitter configured to send a processed data frame; a frame header detection circuit configured to identify a frame header and a preamble in a non-return-to-zero coding format from the data frame based on a specific code sequence, and obtain frame header information accordingly, and detect a level jump edge in the frame header and the preamble, and output a reference clock signal based on the detection result; and a clock and data recovery circuit configured to map a multi-level digital signal of a data segment after the frame header and the preamble into binary data bits using a corresponding pulse amplitude modulation format based on the frame header information, and recover a local receiving clock based on the reference clock signal. The slave node device effectively overcomes the synchronization difficulty and slow clock recovery in a multi-level pulse amplitude modulation system.

The application discloses a kind of self-adapting nonlinear impairment compensation methods based on low-cost optical performance monitoring, and its technical scheme main points are as follows: in transmitting end, low-speed mark is modulated to the envelope of high-speed data signal on top signal;A section of zero-power gap is inserted into signal, after digital-analog conversion and electro-optical conversion are successively carried out to data, into optical fiber link;In receiving end, the signal received is successively carried out photoelectric conversion, analog-digital conversion, IQ orthogonalization, clock recovery;Combining the step number of FD-Volterra-CDE back propagation process in different optical transmission link state parameter range N span Nonlinear effect introduced by the calculation of nonlinear impairment causes optical signal-to-noise ratio penalty;The adaptive nonlinear impairment compensation method in the application solves the problem of too high calculation complexity in the traditional nonlinear impairment compensation process, and by establishing the LUT of the step number N step , filter number N k In the process of FD-Volterra-CDE back propagation in different optical transmission link state parameter range, the calculation complexity is effectively reduced while the compensation accuracy is guaranteed.

The embodiment of the invention provides a CBR service clock rate recovery method. The method comprises the following steps: receiving an OSU frame; the OSU frame carries timestamp information of the CBR service signal, and the timestamp information comprises a timestamp difference value for transmitting the CBR service signal; sampling the OSU frame through a frequency divider, and counting an accumulated timestamp difference value and an accumulated local clock period number in a sampling period number; and recovering the CBR service clock rate according to the sampling period number, the accumulated timestamp difference value and the accumulated local clock period number. Compared with an existing CBR clock recovery technology, step-by-step recovery is not needed, the clock recovery performance is greatly improved, the complexity is greatly reduced, the precision is greatly improved based on point-to-point recovery, and the problems that in long-distance service transmission cascading in the related technology, step-by-step recovery is needed, offset exists in the step-by-step clock recovery process, and the clock recovery efficiency is poor are solved. And the finally recovered clock performance loss is caused.

A system includes a crystal oscillator, a central switch transceiver coupled to the crystal oscillator, and a sensor transceiver. The central switch transceiver includes transmitter circuitry to generate a self- clocked signal carrying first data using a timing reference from the crystal oscillator, and clock and data recovery loop circuitry to operate at a first bandwidth to sample second data received from the sensor transceiver. The sensor transceiver includes reference clock recovery circuitry to decode a reference clock from the self- clocked signal. A phase-locked loop (PLL) circuit generates a transmission clock operating at a second bandwidth from the reference clock for generating the second data. The first bandwidth is greater than or equal to the second bandwidth of the PLL circuit to mitigate jitter experienced by the clock and data recovery loop circuitry due to jitter in the transmission clock.

This invention discloses a code-assisted baud rate sampling clock recovery method and system, applicable to the field of optical fiber communication technology. The method includes the following steps: performing matched filtering on the received signal; using the M&M algorithm to complete primary clock recovery on data from an oscilloscope to obtain baud rate sampling data; performing equalization processing on the baud rate sampling data; using a belief propagation algorithm to decode the equalized baud rate sampling data and output reliability estimation information; modulating the reliability estimation information of each baud rate sampling data into a PAM4 auxiliary symbol according to the PAM4 mapping rule; using the PAM4 auxiliary symbol to replace the decision symbol in the M&M algorithm to re-estimate the clock error and perform high-precision clock recovery. This invention, by combining primary and auxiliary clock recovery stages, significantly reduces the bit error rate and provides more stable clock synchronization in high data rate scenarios.

An oscilloscope having a Nyquist frequency lower than an analog bandwidth includes an input configured to receive a signal under test; an analog-to-digital converter (ADC) to receive the signal under test, sample the signal under test at a sampling rate, and generate digital samples of the signal under test; one or more processors configured to execute code that causes the one or more processors to: determine a set of candidate unit intervals by generating corresponding candidate histograms using the candidate unit intervals; determine a best unit interval from the candidate unit intervals based on entropy measures of each candidate histogram; and reconstruct a representation of the signal under test using the digital samples and the best unit interval.

According to the invention, the optical signal wavelength test module, the optical signal frequency test module, the optical signal intensity test module and the optical signal rate test module are arranged to detect the wavelength, frequency, intensity and rate of an input optical signal; the method comprises the following steps: firstly, carrying out all-optical clock recovery processing on optical signals with different wavelengths and rates by setting a single recovery module and a multi-recovery module; classifying the optical signals with different wavelengths and rates; whether to carry out photoelectric signal conversion is to carry out mode locking by using a traditional electric module or directly carry out optical mode locking by using an active mode-locking laser module capable of carrying out mode locking on an optical signal with a higher transmission rate is determined by detecting the rate of the optical signal, so that the situation that the traditional electric module cannot process the optical signal with an overhigh rate is prevented; processing can be carried out according to different optical signal transmission rates; the mode locking modes of different electric signals after photoelectric transmission are determined by detecting the intensity and frequency of optical transmission signals.

Near field communications (NFC) may be used of radio frequency identification (RFID) tags and may use amplitude modulated (AM) / amplitude shift keyed (ASK) signals, for instance on-off keying (OOK). The invention discloses an AM scheme where the duration / width of the high amplitude pulse is used to encode data. The invention may encode each symbol to a fixed duration (e.g. 8 periods) with one or two low amplitude periods (P) inserted therein (see Fig. 4). Demodulation may need to consider the duration multiple high amplitude segments together (see. Fig. 6). The amplitude modulation scheme of the invention is intended to enable demodulation without the need for clock recovery. The invention may be used to encode NFC-V or ISO / IEC 15693 symbols / commands.

The invention relates to a clock recovery device and a display driving device including the same. A clock recovery apparatus according to an embodiment may include: a clock generator configured to generate a master clock signal from embedded transmission data; a delay line for generating a multi-level clock signal by delaying the master clock signal by a preset reference delay time unit based on an input frequency; and a delay controller configured to receive two clock signals delayed by a reference delay time unit among the multi-stage clock signals and detect a delay time, output a selection signal based on the delay time and the reference delay time, correct a delay time of the master clock signal to the reference delay time based on the selection signal, and output a clock signal to the master clock signal based on the corrected delay time. And outputs the master clock signal corrected to the reference delay time to the delay line; and a data recovery module configured to recover the multi-level clock signal corrected to the reference delay time by the delay line.

The present application discloses a clock data recovery circuit system and a clock recovery operation method based thereon. The clock data recovery circuit system includes: a data detection control module, a phase detector, a filter, and a voltage-controlled oscillator. The first input of the phase detector is used to receive a signal to be processed, and the second input of the phase detector is connected to the output of the voltage-controlled oscillator, which is the output of the clock data recovery circuit system. The filter includes: a gain module, an integration module, and an adder. The input of the gain module and the input of the integration module are both connected to the output of the phase detector. The clock data recovery circuit system and the clock recovery operation method based thereon solve the problem in the prior art that when the clock data recovery circuit system is started, the integration module is simultaneously started. Due to a large initial frequency difference and insufficient gain of the gain circuit, the integration module is locked into an error interval state, resulting in frequency tracking errors.

A method for reclocking an input signal, the method comprising the following steps: - receiving a digital data stream with an average data rate corresponding to a first clock rate; - receiving a clock signal having a second clock rate from an adjustable clock source; and - adjusting a clock edge timing of transitions within the digital data stream based on the clock signal to generate a modulated output signal having a power spectrum, wherein the rising and falling clock edges of the digital data stream are re-clocked such that the power spectrum of the modulated output signal includes spectral zeros at the second clock frequency and at multiples of the second clock frequency without changing the average data rate.