261 results about "Clock recovery" patented technology

A test and measurement instrument has a port to receive a signal from a device under test (DUT), one or more processors configured to execute code that causes the one or more processors to acquire a waveform from the signal, derive a pattern waveform from the waveform using one of either hardware or software clock recovery, perform linear fit pulse response (LFPR) extractions on the pattern waveform to extract more than one LFPR, determine a reference pulse response from the more than one LFPRs, compare at least one of the LFPRs to the reference pulse response to determine a difference, and tune the DUT to reduce the difference. The test and measurement instrument may also use the multiple LFPRs as an input to a machine learning network to perform measurement predictions for the DUT.

The invention is suitable for the technical field of signal testing, and provides a high-speed serial signal testing method and system and semiconductor testing equipment, and the high-speed serial signal testing method comprises the steps: carrying out the time sequence adjustment of a testing signal through a phase-adjustable clock reference, actively introducing controllable jitter, and carrying out the jitter tolerance testing; a target test signal is sent to a receiving end through an emission driver, after a receiving signal is obtained, a target sampling time sequence is extracted based on clock recovery, a programmable receiving delay chain is controlled to carry out time scanning, and receiving data at multiple sampling moments are obtained; comparing each sampling data with the test signal, counting the bit error rate under each delay setting, and completing signal quality evaluation; the scheme has the advantages of modularization, high precision, low cost and the like, and the comprehensive test efficiency and reliability of the semiconductor test equipment on high-speed serial signals are improved.

The invention provides a signal clock recovery method and device for high-speed serial data and communication equipment, and relates to the technical field of digital signal processing, and the method comprises the steps: carrying out the histogram statistical analysis of a collected signal based on a voltage direction, and obtaining a probability density curve; obtaining a bottom value and a top value based on the probability density curve; obtaining a high level threshold value and a low level threshold value based on the bottom value and the top value; based on the high level threshold value and the low level threshold value, extracting and obtaining a signal edge cross point sequence; calculating a signal edge cross point difference value based on the signal edge cross point sequence; and performing clock recovery based on the signal edge cross point difference to obtain standard clock data. Through the steps, the problem that in the prior art, the reliability of generating the jitter signal is relatively low is solved.

The utility model relates to a phase interpolator circuit, a clock recovery circuit and a chip, and the phase interpolator circuit mainly comprises a first clock filter which is used for filtering a high-frequency harmonic wave of a first clock signal to generate a first filtering signal; the second clock filter is used for filtering the high-frequency harmonic wave of the second clock signal to generate a second filtering signal; the phase mixer is coupled to the first clock filter and the second clock filter and is used for generating a phase mixed signal according to the first filtering signal and the second filtering signal; and the alternating current coupling output circuit is used for receiving the phase mixed signal and generating an interpolation clock signal according to the phase mixed signal. The phase interpolator circuit can support phase interpolation operation in a wide frequency range, the output linearity performance is optimized, the sensitivity of INL and DNL to power supply amplitude changes is weakened, the duty ratio of the output interpolation clock signal can be optimized, and the interpolation clock signal can support a high-speed interface half-rate transmission mode.

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

The invention relates to a low-cost HDMI (High Definition Multimedia Interface) video optical transmission device and a transmission method based on an FPGA (Field Programmable Gate Array), which are characterized in that the FPGA is used for encoding and decoding HDMI video signals, and a professional video encoding and decoding chip is replaced; meanwhile, a brand-new video transmission frame architecture is designed, effective video data are framed into data frames for transmission at a transmitting end, frame identifiers are set in the data frames, the data frames are deframed into video data according to the frame identifiers at a video recovery end, and according to different resolutions, an IP core of a local clock of an FPGA is used for dynamic adjustment to adapt to various resolutions. Video signals such as line and field signals are output, and a professional pixel clock recovery chip and a DDR3 cache chip are replaced; the whole scheme is high in transmission efficiency, small in transmission delay, capable of achieving real-time transmission, low in hardware system cost, small in size and suitable for application and popularization.

An oscilloscope having a Nyquist frequency lower than an analog bandwidth includes an input configured to receive a signal under test; an analog-to-digital converter (ADC) to receive the signal under test, sample the signal under test at a sample rate, and produce digital samples of the signal under test; one or more processors configured to execute code that causes the one or more processors to: determine a set of candidate unit intervals by generating corresponding candidate histograms using the candidate unit intervals; determine a best unit interval from the candidate unit intervals based upon entropy measures of each candidate histogram; and reconstruct a representation of the signal under test using the digital samples and the best unit interval.

The invention discloses an LPO wired receiver adopting adaptive CTLE based on a genetic algorithm, and the receiver comprises an analog front end, a data sampler, an edge sampler, an error sampler, a 1: 32 demultiplexer, a verification module, an eye pattern monitor, a genetic algorithm module, clock recovery logic, and a clock path. The eye pattern monitor is used for calculating the eye pattern closure degree according to the data of the data sampler and the error of the error sampler and outputting the eye pattern closure degree to the genetic algorithm module; and the genetic algorithm module is used for realizing parameter adaptive control of a continuous time linear equalizer CTLE and a variable gain amplifier VGA in the analog front end. The invention aims to apply the genetic algorithm to the adaptive equalization of the adaptive continuous time linear equalizer, so that the adaptive continuous time linear equalizer has stronger global search capability and lower power consumption and is not easy to fall into local optimum, and the complexity and power consumption of the adaptive continuous time linear equalizer are reduced. And the real-time and energy-saving requirements are met.

The invention discloses a time interval error jitter extraction method based on Hilbert transform, and relates to the field of high-speed data signal processing, and the method comprises the steps: firstly carrying out the statistics through a level histogram after a detected data signal is obtained, and determining a corresponding level judgment reference; secondly, performing Hilbert transform on the tested data signal to obtain time information of a jump edge of the tested data signal; an accurate code element rate of a measured data signal is extracted by adopting a coarse frequency estimation and fine frequency estimation method, and high-precision constant frequency clock recovery is carried out; according to the Hilbert transform-based time interval error jitter extraction method provided by the invention, a basis is provided for high-precision time interval error jitter, and jitter measurement is accurately carried out on a measured data signal.

The invention discloses an optical fiber signal transmission system and method based on quantum noise encryption, and relates to the technical field of optical fiber communication, and the system comprises a composite modulation transmitting module, a dispersion compensation relay module, a coherent receiving module and a digital signal processor. The composite modulation transmitting module comprises an electro-optical modulator and a quantum noise randomization encoder; the dispersion compensation relay module comprises an adjustable dispersion compensator and a Raman amplifier; the coherent receiving module comprises a local oscillator laser and a 90-degree optical mixer; a digital signal processor includes a clock recovery unit and a maximum likelihood sequence detector. All the modules are sequentially connected and cooperatively work. And the adjustable dispersion compensator dynamically applies reverse dispersion compensation calculated based on a dispersion coefficient and a transmission distance according to the dispersion amount monitored in real time. According to the invention, through technologies of quantum noise encryption, dynamic dispersion compensation, Raman amplification, coherent reception and the like, safe and efficient transmission with single-wave 400Gbps and 100km transmission bit error rate less than or equal to 1 * 10 <-12 > is realized.

The invention relates to the technical field of serial communication, in particular to a high-speed clock recovery method and device based on an adjustable delay chain, and the method comprises the steps: generating a recovery clock initial phase; a multi-stage programmable delay chain is adopted, and a phase-locked loop or delay-locked loop structure is combined, so that the initial phase of a recovered clock is finely adjusted and locked, and phase capture and clock edge alignment are performed; based on a multi-path recovery structure, a path with the minimum error is selected from the delay paths through a preset phase error detection mechanism to serve as an output channel; environment parameters of the environment are collected, parameters of the multi-stage programmable delay chain are dynamically adjusted, and high-speed clock recovery is completed. According to the method, the edge capture precision, the system jitter tolerance and the working frequency range of the recovered clock are remarkably improved, and then the phase consistency, the anti-interference capability and the overall data receiving reliability of the recovered clock in the high-speed communication system are effectively improved.

A test and measurement device has an input port to receive a signal from a device under test (DUT), the signal having a symbol rate, one or more analog-to-digital converters (ADC) to convert the signal to waveform samples at a sampling rate, and one or more processors, when aliasing is present: up-sample a portion of the signal having aliased samples to produce up-sampled samples; use the up-sampled samples to produce a real-time waveform; perform clock recovery on the real-time waveform to produce a recovered clock; and resample the aliased samples to produce a non-aliased waveform.

Fast sampling phase and frequency acquisition suitable for incorporation into various high bandwidth receivers and receiving methods. One illustrative integrated circuit receiver or “deserializer” design has: a clock circuit that provides a sample clock; an analog to digital converter that samples a receive signal in accordance with the sample clock to provide receive signal samples; and a clock recovery circuit. The clock recovery circuit includes: a phase and frequency acquisition module to determine and correct an initial frequency offset and an initial phase offset of the sample clock; and a feedback circuit to minimize timing error of the sample clock after the initial frequency offset and initial phase offset have been corrected.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

The invention relates to a high-speed serial interface circuit, and discloses a linearity calibration and precision expansion method of a numerical control phase interpolator. According to the method, a digital delay converter (DDC) is cascaded behind a digital control phase interpolator (DPI), and delay compensation is carried out on an interpolated clock signal; sampling the compensated clock signal by using an analog-to-digital converter (ADC) to obtain a phase sampling value; the calibration control module calculates a phase error and generates a delay control word; when the numerical control phase interpolator DPI works, phase control words and delay control words are synchronously provided for corresponding modules, and linearity calibration and precision expansion are achieved. According to the method, a special detection circuit does not need to be added, hardware resources existing in a high-speed serial interface are utilized, the method can be achieved through simple digital control logic, the phase integral linearity is improved to be within 25 fs from 250 fs, meanwhile, the precision of an 8-bit phase interpolator is improved to be close to the 11-bit level, and the method is suitable for large-scale popularization and application. And the clock recovery performance and the data transmission reliability of the high-speed communication system are obviously improved.

A signal receiving circuit includes first to third pulse generators; and a clock signal recovery unit 100 for generating a recovery clock signal RCLK and a recovery clock delay signal RCLKD, which is a signal obtained by delaying the recovery clock signal as much as a first delay time, using at least one of pulses including a first pulse, a second pulse, a third pulse, and first to third inversion pulses, wherein the clock signal recovery unit includes: a loop interruption circuit including an input node and an output node and turned on and off by at least one of the pulses; and a delay circuit having an input terminal connected to the output node and an output terminal connected to the input node. A signal value of the input node and a signal value of the output node are in an inverse relationship.

The invention discloses an optical fiber wireless heterogeneous network intelligent monitoring system and method based on energy-information co-transmission, and relates to the technical field of optical fiber wireless heterogeneous network intelligent monitoring, the system comprises a central base station unit, an energy-information co-transmission optical fiber transmission unit and a micro-nano integration unit; the central base station unit is integrated with a high-power laser with a first preset wavelength, a light receiving unit with a second preset wavelength and a data processing subunit; the high-power laser is used for generating an optical signal for transmitting energy; the light receiving unit is used for receiving monitoring data; the data processing subunit is used for realizing clock recovery, code element synchronization, serial decoding and data display functions; and the energy-information co-transmission optical fiber transmission unit takes a multi-core optical cable as a physical carrier and adopts a wavelength division multiplexing technology to realize isolated transmission of energy and information, one end of the energy-information co-transmission optical fiber transmission unit is in communication connection with the central base station unit, and the other end of the energy-information co-transmission optical fiber transmission unit is in communication connection with each micro-nano integrated monitoring unit.

The invention discloses a video clock recovery method and device, a storage medium and electronic equipment, and the method comprises the steps: extracting a video time sequence parameter from an auxiliary information packet when the auxiliary information packet transmitted by a transmitting end is received; configuring a phase-locked loop according to the video time sequence parameter, and generating a video clock; when the video data is received, counting the actual clock number of each video line by using a video clock so as to obtain the current clock error of each video line; performing coarse adjustment on the video clock according to the current clock error until the video clock is initially converged; and performing fine adjustment on the video clock after preliminary convergence until the video clock reaches a stable state. According to the invention, the precision of video clock recovery can be improved.

A clock buffer has a clock-in port that inputs a reference clock and an enable port that inputs a video-clock-enable signal from a video receiver. The clock buffer generates a video pixel clock signal that has pulses of the reference signal as enabled by the video-clock-enable signal. The video receiver includes a link symbol extractor, a link-to-pixel mapper, and a timing generator that work to mirror the actual pixel data rate from the active period in a blanking period and thereby recover the actual video pixel clock.

The invention provides a self-adaptive equalization method and device and SerDes equipment, and the method comprises the steps: receiving an input signal with a predicted frequency characteristic, and carrying out the equalization of the input signal through an equalizer; obtaining frequency information of the balanced input signal; and adjusting configuration parameters of the equalizer according to the difference between the frequency information of the equalized input signal and the known frequency characteristic of the input signal until a target configuration parameter enabling the frequency information of the equalized input signal to be matched with the known frequency characteristic is obtained. According to the invention, based on the frequency domain, the data balance of the receiving end is evaluated and the equalizer is correspondingly adjusted without depending on a clock recovery circuit, so that rapid and accurate adaptive equalization can be realized.

The invention discloses a clock data recovery device, which is characterized in that a differential conversion module converts a serial signal into a single-bit signal, a delay module processes the single-bit signal to obtain a delay data signal, a sampling module performs sampling to obtain target sampling data, a jump edge detection module performs XOR operation on the target sampling data, and a clock data recovery module performs clock data recovery. The method comprises the following steps: obtaining current data hopping phase information, storing a mapping relation between a sampling phase and an ideal data hopping phase sequence by a storage module, determining the ideal data hopping phase sequence corresponding to the current sampling phase by a phase adjustment module, and adjusting the current data hopping phase information, a sampling phase deviation result is searched in the phase adjustment table based on the adjusted data hopping phase information, the current sampling phase is adjusted based on the search result, the optimal sampling phase is obtained, and a data clock recovery module carries out data and clock recovery on target sampling data based on the optimal sampling phase. Therefore, the clock to be recovered can be quickly locked, and the clock locking efficiency is improved.

The invention relates to the technical field of optical fiber communication, and discloses a clock recovery system and method for a multi-aperture coherent optical signal, and the system comprises an interpolator which obtains coherent optical signals received through a plurality of different apertures, and carries out the preliminary adjustment of the clock phase of the coherent optical signals; the MIMO equalizer equalizes and synthesizes a plurality of coherent optical signals of which the clock phases are readjusted, and the error detector tracks the clock phases of the transmitted coherent optical signals in real time and extracts the clock phase error of each coherent optical signal relative to the transmitted coherent optical signals in the synthesized coherent optical signals. The clock generation chip is used for generating a reference clock with a corresponding clock phase according to the clock phase error of each coherent optical signal, so that the clock phase of each coherent optical signal is readjusted through the reference clock, and at the moment, the coherent optical signals with the readjusted clock phases are balanced and synthesized; the quality of the synthesized multi-aperture signal can be improved.

The invention relates to an improved ABSPD clock recovery method under single Baud rate sampling, clock synchronization of receiving and transmitting end signals is realized through a clock recovery loop based on a full number font, and when a provided timing error detector calculates a timing error e, symbol judgment and shift operation are used for replacing numerical multiplication; after a timing error e is calculated by the timing error detector, the timing error e is input into a loop filter for noise filtering, and a control word W is obtained; controlling the numerically controlled oscillator by using the control word W, and calculating a fractional interval mu k according to the output NCO of the numerically controlled oscillator and the control word W; and carrying out interpolation on the received signal in an interpolation filter by utilizing the integer mark mk of the symbol and the calculated fractional interval mu k so as to calculate and obtain data with correct timing. According to the invention, ABSPD clock recovery under single Baud rate sampling without multiplication operation is realized, and the complexity of the whole clock recovery loop is obviously reduced.

The invention relates to the technical field of USB audio equipment optimization, and discloses a USB audio equipment Device mode implementation method and system, a storage medium and equipment, and the method comprises the steps: dynamically recognizing a connection type through detecting a USB data line voltage threshold value, and dynamically loading a corresponding protocol stack module based on the connection type; in a Device mode, a multi-stage buffer mechanism is adopted to manage audio data streams, the number and size of buffer areas are dynamically allocated according to target delay time, and clock synchronization with a host is realized based on an adaptive clock recovery algorithm; the power consumption of the equipment is dynamically adjusted through a multi-stage power consumption state machine, switching is carried out among working states according to an audio activity state and a data transmission requirement, and a remote wakeup function is supported; according to the method, a compatibility strategy library is matched based on a device fingerprint recognition result, protocol characteristics and audio formats of different host devices are automatically adapted, meanwhile, audio playing is controlled through audio quality monitoring and self-optimization, and Device mode support is added to the USB audio device through the method.

The invention relates to the field of high-speed serial interface chips, and discloses an error calibration method of an ultra-high-speed phase interpolator. The method comprises the steps of amplitude calibration, edge searching, reference clock delay calibration, multi-phase cyclic calibration, linear interpolation and the like, a reference clock rising edge zero crossing point is used as a high-precision time reference, delay control words of a selected discrete phase are adjusted one by one, a mapping lookup table covering a full-phase range is generated through linear interpolation, and the time delay control words of the selected discrete phase are adjusted one by one. And compensation of the nonlinear error of the phase interpolator is realized. According to the invention, high-precision linearity calibration can be completed before normal operation of the chip, the clock recovery precision is significantly improved, the nonlinear error is reduced from + / -1.5 LSB to + / -0.5 LSB, the error rate of the system is reduced, and the power consumption and the area overhead are low.

The utility model provides an optical module debugging device, which is characterized in that an optical module to be tested is located on a test board, and an upper computer controls the optical module to be tested through the test board; the upper computer is configured to automatically adjust the voltage and current of the tested optical module according to the optical eye diagram of the tested optical module, so that the power of the tested optical module meets the test requirement; the bit error tester is connected with the test board; the wavelength division module is connected with the tested optical module and the optical switch; the optical switch is connected with the wavelength division module and the clock recovery unit; the clock recovery unit is connected with the optical switch and the oscilloscope; and an oscilloscope. According to the optical module debugging method and device, the configured upper computer communicates with the micro-control unit of the tested optical module to debug the tested optical module, so that the performance of the tested optical module meets requirements, and automation of optical module debugging is achieved.

Systems and methods for biopotential recording integrated circuits are illustrated. One embodiment includes a wireless receiver configured to receive a first radio frequency (RF) signal; one or more wireless transmitters; and a processing circuitry, comprising: a power harvesting circuit configured to harvest energy from the first RF signal; a clock recovery circuit configured to extract a clock signal from the first RF signal; at least one sensing electrode configured to record an electric signal as at least one of a voltage, current, and electric charge; and an analog-to-digital converter (ADC) communicatively coupled to the clock recovery circuit.

A clock recovery system for recovering an in-band communication clock in a wireless power transfer system can in include: a phase locked loop; and a bit decision block and a multiplexer that cooperate to selectively provide the error signal to the loop filter responsive to detected bits in the in-band communication bitstream. The phase locked loop can further include: a phase detector that computes an error signal from a difference between an instantaneous peak location and an estimated peak location correlated to a symbol in an in-band communication bitstream; a loop filter that selectively receives the error signal; and a voltage controlled oscillator that adjusts its output frequency responsive to an output of the loop filter.

The invention discloses a multi-protocol self-adaptive management docking station core board control method and system, and belongs to the technical field of docking station core board monitoring control, and the method comprises the steps: analyzing the stability risk analysis necessity of a docking station core board, analyzing the stability risk score of the docking station core board, and determining the stability risk of the docking station core board; and performing control optimization adjustment on the docking station core board based on the stability risk score of the docking station core board, performing protocol layer clock recovery circuit sampling phase drift analysis, analyzing a protocol layer clock recovery circuit sampling phase drift characterization factor, and executing control adjustment of sampling phase drift. According to the method, the stability and reliability of system operation can be improved, the link retraining frequency is reduced, sampling phase adjustment is optimized, sampling point dislocation, inter-frame phase lock out-of-step and systematic communication faults are prevented under the condition of multi-protocol concurrent working, and long-term stable operation and multi-protocol compatibility of the docking station core board are guaranteed.