75 results about "Clock recovery" patented technology

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

The invention relates to the technical field of serial communication, in particular to a high-speed clock recovery method and device based on an adjustable delay chain, and the method comprises the steps: generating a recovery clock initial phase; a multi-stage programmable delay chain is adopted, and a phase-locked loop or delay-locked loop structure is combined, so that the initial phase of a recovered clock is finely adjusted and locked, and phase capture and clock edge alignment are performed; based on a multi-path recovery structure, a path with the minimum error is selected from the delay paths through a preset phase error detection mechanism to serve as an output channel; environment parameters of the environment are collected, parameters of the multi-stage programmable delay chain are dynamically adjusted, and high-speed clock recovery is completed. According to the method, the edge capture precision, the system jitter tolerance and the working frequency range of the recovered clock are remarkably improved, and then the phase consistency, the anti-interference capability and the overall data receiving reliability of the recovered clock in the high-speed communication system are effectively improved.

The invention discloses an optical fiber wireless heterogeneous network intelligent monitoring system and method based on energy-information co-transmission, and relates to the technical field of optical fiber wireless heterogeneous network intelligent monitoring, the system comprises a central base station unit, an energy-information co-transmission optical fiber transmission unit and a micro-nano integration unit; the central base station unit is integrated with a high-power laser with a first preset wavelength, a light receiving unit with a second preset wavelength and a data processing subunit; the high-power laser is used for generating an optical signal for transmitting energy; the light receiving unit is used for receiving monitoring data; the data processing subunit is used for realizing clock recovery, code element synchronization, serial decoding and data display functions; and the energy-information co-transmission optical fiber transmission unit takes a multi-core optical cable as a physical carrier and adopts a wavelength division multiplexing technology to realize isolated transmission of energy and information, one end of the energy-information co-transmission optical fiber transmission unit is in communication connection with the central base station unit, and the other end of the energy-information co-transmission optical fiber transmission unit is in communication connection with each micro-nano integrated monitoring unit.

The invention discloses a multi-protocol self-adaptive management docking station core board control method and system, and belongs to the technical field of docking station core board monitoring control, and the method comprises the steps: analyzing the stability risk analysis necessity of a docking station core board, analyzing the stability risk score of the docking station core board, and determining the stability risk of the docking station core board; and performing control optimization adjustment on the docking station core board based on the stability risk score of the docking station core board, performing protocol layer clock recovery circuit sampling phase drift analysis, analyzing a protocol layer clock recovery circuit sampling phase drift characterization factor, and executing control adjustment of sampling phase drift. According to the method, the stability and reliability of system operation can be improved, the link retraining frequency is reduced, sampling phase adjustment is optimized, sampling point dislocation, inter-frame phase lock out-of-step and systematic communication faults are prevented under the condition of multi-protocol concurrent working, and long-term stable operation and multi-protocol compatibility of the docking station core board are guaranteed.

Provided are a wired transmission time division duplex system and a node device thereof. The node device comprises a receiver configured to receive a data frame; a transmitter configured to send a processed data frame; a frame header detection circuit configured to identify a frame header and a preamble in a non-return-to-zero coding format from the data frame based on a specific code sequence, and obtain frame header information accordingly, and detect a level jump edge in the frame header and the preamble, and output a reference clock signal based on the detection result; and a clock and data recovery circuit configured to map a multi-level digital signal of a data segment after the frame header and the preamble into binary data bits using a corresponding pulse amplitude modulation format based on the frame header information, and recover a local receiving clock based on the reference clock signal. The slave node device effectively overcomes the synchronization difficulty and slow clock recovery in a multi-level pulse amplitude modulation system.

The application discloses a kind of self-adapting nonlinear impairment compensation methods based on low-cost optical performance monitoring, and its technical scheme main points are as follows: in transmitting end, low-speed mark is modulated to the envelope of high-speed data signal on top signal;A section of zero-power gap is inserted into signal, after digital-analog conversion and electro-optical conversion are successively carried out to data, into optical fiber link;In receiving end, the signal received is successively carried out photoelectric conversion, analog-digital conversion, IQ orthogonalization, clock recovery;Combining the step number of FD-Volterra-CDE back propagation process in different optical transmission link state parameter range N span Nonlinear effect introduced by the calculation of nonlinear impairment causes optical signal-to-noise ratio penalty;The adaptive nonlinear impairment compensation method in the application solves the problem of too high calculation complexity in the traditional nonlinear impairment compensation process, and by establishing the LUT of the step number N step , filter number N k In the process of FD-Volterra-CDE back propagation in different optical transmission link state parameter range, the calculation complexity is effectively reduced while the compensation accuracy is guaranteed.

A system includes a crystal oscillator, a central switch transceiver coupled to the crystal oscillator, and a sensor transceiver. The central switch transceiver includes transmitter circuitry to generate a self- clocked signal carrying first data using a timing reference from the crystal oscillator, and clock and data recovery loop circuitry to operate at a first bandwidth to sample second data received from the sensor transceiver. The sensor transceiver includes reference clock recovery circuitry to decode a reference clock from the self- clocked signal. A phase-locked loop (PLL) circuit generates a transmission clock operating at a second bandwidth from the reference clock for generating the second data. The first bandwidth is greater than or equal to the second bandwidth of the PLL circuit to mitigate jitter experienced by the clock and data recovery loop circuitry due to jitter in the transmission clock.

This invention discloses a code-assisted baud rate sampling clock recovery method and system, applicable to the field of optical fiber communication technology. The method includes the following steps: performing matched filtering on the received signal; using the M&M algorithm to complete primary clock recovery on data from an oscilloscope to obtain baud rate sampling data; performing equalization processing on the baud rate sampling data; using a belief propagation algorithm to decode the equalized baud rate sampling data and output reliability estimation information; modulating the reliability estimation information of each baud rate sampling data into a PAM4 auxiliary symbol according to the PAM4 mapping rule; using the PAM4 auxiliary symbol to replace the decision symbol in the M&M algorithm to re-estimate the clock error and perform high-precision clock recovery. This invention, by combining primary and auxiliary clock recovery stages, significantly reduces the bit error rate and provides more stable clock synchronization in high data rate scenarios.

The invention relates to the technical field of electronic system time sequence control, in particular to a multi-system clock synchronization method based on a low-frequency calibration clock, which is characterized in that a main system adopts a high-stability clock source and simultaneously generates a high-frequency data clock and the low-frequency calibration clock of which the frequency is less than one thousandth of that of the data clock through a clock management unit; the characteristics of strong anti-interference and high transmission quality of the low-frequency clock are utilized, and the low-frequency clock is sent to each slave system through the optimized clock distribution network. Each slave system extracts a low-frequency calibration clock through a clock recovery circuit, a high-precision time interval measurement unit is adopted to measure the time difference between a local clock and the calibration clock, and the measurement precision and stability are improved through digital signal processing. And each slave system inputs the time difference as a control quantity into a digital regulation system, dynamically regulates the phase of a local clock, and judges a synchronous locking state through a locking state detection mechanism, thereby realizing high-precision, long-term and stable clock synchronization among multiple systems.

The application relates to the technical field of wireless communication networks, and discloses a wireless communication anti-interference method for an avionics system, which comprises the following steps: nodes in a network autonomously synchronize channel switching based on a shared key and a public time reference; when the public time reference is invalid, a mobile node calibrates a local clock by monitoring the channel switching time of a central node to restore synchronization; the application can avoid interference by synchronizing without real-time signaling, solves the network lockout problem caused by invalid coordination signaling, and ensures the reliability of avionics communication by using the hopping behavior of the network itself as an internal clock beacon to enable the nodes to self-recover and synchronize when an external public time reference is lost.

Apparatus and methods for discovery, synchronization and operation of network components. In one embodiment, the network comprises a passive optical network (PON), and the components being synchronized include an enhanced OLT (eOLT) and one or more enhanced ONUs (eONUs). The eOLT is configured in one variant to utilize control protocol messaging (such as those used in the MPCP or Multi Point Control Protocol) to communicate particular synchronization parameters and durations to the eONU(s), whether individually or via multicast / broadcast. The synchronization parameter and durations are selected to optimize discovery and synchronization of the eONU(s) with the eOLT, and also optimize (subsequent) normal operation, in one implementation through selection of synchronization patterns which enable most efficient AGC determination, clock recovery (CDR), SBD, and EBD identification.

A clock recovery loop in a digital signal processor for a serializer-deserializer data interface can be modified to achieve fractional lock and operate in a sampling scope mode. The clock recovery loop can control a phase locked loop to produce a clock signal that is at a rational fraction of a baud rate. The clock signal can be used by time-interleaved analog-to-digital converters to achieve oversampling of a periodic signal received over a receive channel. The samples can be used to reconstruct a continuous time signal bit response to characterize or debug the receive channel.

The application belongs to the technical field of optical fiber communication, and discloses an optical fiber transmission link quality monitoring and dispersion compensation optimization method and system, which comprises the following steps: extracting an error vector amplitude, an optical signal-to-noise ratio and constellation distortion features from a coherent receiver and fusing them into a comprehensive quality evaluation index; jointly estimating residual dispersion by using a clock recovery phase and equalizer coefficient distribution; adopting a variable step gradient descent to adaptively optimize dispersion compensation filter parameters; performing performance degradation trend analysis and early warning; and jointly monitoring and cooperatively optimizing multiple wavelength channels.

The application discloses a method for automatically identifying and matching a 5G front transmission network interface, and belongs to the technical field of computers.The method comprises the following steps: a QSFP interface detection step and an SFP interface detection step.The method adopts a receiving side clock phase-locked loop adaptive configuration technology, a clock recovery circuit automatic adjustment and sampling technology and an encoding error code detection technology, and realizes the functions of fast automatic scanning and matching of port rate, line encoding and frame protocol by judging whether the following conditions are normal: PLL locking, frequency deviation range, short-time frequency stability, encoding without exception and frame synchronization, so that the testing and troubleshooting time of the 5G front transmission interface is greatly shortened.

The embodiment of the invention provides a clock recovery method and device based on burst data and an optical line terminal. The method comprises the following steps: under the condition that a first lead code sent by ONU equipment is received in a stream sending stage, setting a CDR loop to be in an open loop mode, so as to sample a second lead code sent by the ONU equipment based on a local clock, and adjust a sampling phase of the local clock based on the second lead code to generate a first recovery clock; and sampling a third preamble sent by the ONU equipment based on the first recovery clock, and setting the CDR loop to be in a closed loop mode, so as to circularly adjust the locking bandwidth of the CDR loop in stages to generate a second recovery clock, so that the phase of the second recovery clock is consistent with the phase of a sending clock of the ONU equipment. According to the method and the device, the problem of quick recovery of the burst data is at least solved, so that the effects of reducing data dependence and realizing quick recovery of the burst data are achieved.

The invention relates to an analog-to-digital converter background calibration system and method, and the system comprises a multiplier, an equalization and judgment module, an adaptive module, a clock recovery module, a phase error calibration module, and a gain calibration module. The adaptive module is used for adaptively generating a signal amplitude and a judgment amplitude according to q data and e data output by the equalization and judgment module; the equalization and judgment module outputs the data q and the data e according to the output signal of the multiplier, the gain adjustment signal, the signal amplitude and the judgment amplitude; the clock recovery module outputs a phase control signal according to the q data and the e data and provides the phase control signal to a phase adjustment circuit; the phase error calibration module outputs a phase error control signal according to the q data and the e data and provides the phase error control signal to the phase adjustment circuit; and the gain calibration module outputs the gain adjustment signal according to the q data and the e data and provides the gain adjustment signal to the multiplier.

A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.

The embodiment of the invention provides a clock recovery method and device for burst signals and an optical line terminal, and relates to the field of communication. The method comprises the following steps: determining the number of phase adjustment times based on a preset phase step length, so as to obtain first sampling data of different phase points based on the number of phase adjustment times; acquiring a characteristic signal data set of a sampling signal based on the first sampling data; acquiring a characteristic value data set based on the characteristic signal data set; and determining a maximum value and a secondary maximum value based on the characteristic value data set, determining a clock control signal based on the maximum value and the secondary maximum value, adjusting a sampling phase based on the clock control signal, and sampling data based on a new sampling phase. Through one embodiment of the invention, the problem of high power consumption in the process of identifying the clock sampling phase in the prior art is at least solved, so that the effect of reducing the power consumption in the process of identifying the clock sampling phase is achieved.

A communications network for a vehicle comprising: a central processing node; a zonal node; an Ethernet network coupling the central processing node to the zonal node; and an edge network coupled to the zonal node, the edge network comprising a time domain multiplexing (TDM) bus and a plurality of edge transducers coupled to the TDM bus, wherein the zonal node comprises a network bridge for bridging transducer data received from the TDM bus to the Ethernet backbone network, wherein the network bridge comprises: interface circuitry for interfacing the network bridge with the TDM bus; clock recovery circuitry for recovering a clock signal for use by the edge network from an Ethernet frame received from the Ethernet network, wherein a TDM cycle of the TDM bus is synchronised to the recovered clock signal; acoustic data receiver circuitry coupled to the interface circuitry by a first low-latency data path, wherein the acoustic data receiver circuitry is configured to transmit acoustic data contained in Ethernet frames received at the network bridge from the Ethernet network to the interface circuitry; and acoustic data transmitter circuitry coupled to the interface circuitry by a second low-latency data path, wherein the acoustic data transmitter circuitry is configured to transmit Ethernet frames containing acoustic data received at the interface circuitry from the edge network to the Ethernet network.

The invention relates to the field of heterogeneous intensity modulation format signal shaping and regeneration, and provides a multi-type service access adaptive signal shaping and regeneration method and system, and the method comprises the steps: receiving a mixed signal, and extracting time-frequency domain features; identifying the time-frequency domain feature vector to obtain a probability distribution vector and a probability weight of each modulation format; activating a plurality of shaping filter branches according to the probability distribution vector, and performing parallel shaping processing on the mixed signal to obtain branch signals; carrying out weighted fusion on the branch signals to obtain shaping signals; adjusting the judgment threshold matrix; performing clock recovery pre-compensation and state space prediction optimization; and after regeneration processing, business separation is performed to obtain multi-type data. According to the invention, the precision and adaptability of signal shaping and regeneration processing are improved, and the requirements of a multi-type service access system for high-reliability and high-quality data transmission are met.

The invention discloses a burst mode communication system, which may include one or more channels. Each channel is configured to receive a burst data stream transmitted according to a clock signal and recover the clock signal. The channel can receive a first burst data stream and a second burst data stream in two adjacent clock periods of a clock signal, convert the first burst data stream into a first pulse signal and convert the second burst data stream into a second pulse signal. The channel may recover the clock signal by detecting a time interval between rising edges of the first pulse signal and the second pulse signal. The burst data streams are different signals and are transmitted to a burst mode communication system in a time division multiple access (TDMA) scheme. And a clock recovery circuit is also arranged in the channel and is used for recovering a clock signal.

The present invention provides a data clock recovery circuit with optimized clock jitter tolerance. The circuit includes a multi-task integrator, a controller, and a series of an analog-to-digital converter, an equalizer, a decision device, an error calculator, a phase detection estimator, a loop filter, and a phase interpolator. The multi-task integrator is coupled between the coupling path of the phase interpolator and the loop filter, and outputs one of a phase adjustment signal and a bias signal to the phase interpolator according to a mode selection signal. The controller is coupled to the multi-task integrator for generating the mode selection signal.

The application discloses a clock data recovery circuit and a method for preventing false locking or non-locking of the clock data recovery circuit. The method uses a locking detector in the clock data recovery circuit to judge four kinds of information, i.e. clock advance, clock lag, clock error 1 and clock error 2, detected by a phase detector in the clock data recovery circuit, so that whether the input data rate of the current clock recovery circuit matches the sampling clock can be effectively judged. When the input data rate is high, the clock data recovery circuit is prevented from running off-center and being non-locked, and when the input data rate is low, the clock data recovery circuit is prevented from being false-locked. Meanwhile, the upper protocol layer is rapidly informed. Compared with a traditional speed negotiation mechanism based on the upper protocol layer, the efficiency is improved, and the clock data recovery circuit is effectively prevented from being non-locked.

This invention provides a 100G coherent acquisition closed-loop demodulation method and system integrating TIADC and demodulation, belonging to the field of digital signal processing. The method includes: TIADC mismatch correction, frame synchronization and symbol synchronization, resampling clock recovery, frequency domain full dispersion compensation, three-level polarization demultiplexing (CMA+LMS+DDLMS), joint carrier frequency offset estimation and compensation, Viterbi-Viterbi carrier phase recovery, soft decision and full performance monitoring. This invention is the first to use TIADC front-end correction as the first stage of demodulation, achieving deep integration of acquisition and demodulation. The three-level cascaded equalization architecture balances convergence speed and compensation accuracy. A joint carrier recovery closed loop is established through phase residual feedback, significantly improving demodulation robustness and accuracy. This method can output full test indicators in real time, uses FPGA parallel pipelines to reduce processing latency, and is suitable for engineering applications such as 100G coherent acquisition cards and optical communication test instruments.

The application provides a clock recovery method, device and system. The method can be applied to an optical transport network. The method comprises the following steps: receiving a first optical transport network (OTN) frame data stream, obtaining a service layer clock and phase difference information carried by a second OTN frame from the first OTN frame data stream, and then adjusting a reference clock of the second OTN frame according to the service layer clock and the phase difference information, wherein the reference clock of the second OTN frame is used for recovering a clock of the second OTN frame. The clock recovery method provided by the application can improve the accuracy of clock recovery of the OTN frame, thereby achieving the purpose of improving system performance.

The application provides a real-time transmission and processing method and system for an uplink burst mode passive optical network signal, and the method comprises the following steps: receiving each group of signals in the continuously and parallelly transmitted uplink burst mode passive optical network signal and directly detecting and analog-to-digital converting the signals in real time to obtain each group of digital signals, wherein the passive optical network signal comprises a preamble sequence comprising a first sequence, a second sequence and a third sequence and a sequence carrying transmission information; overlapping each group of digital signals in real time at an overlap ratio to obtain each group of overlapped digital signals; performing real-time frequency domain clock recovery on each group of overlapped digital signals based on the first sequence, performing real-time frequency domain equalization on each group of digital signals after clock recovery based on the third sequence; performing real-time de-overlapping on each group of equalized digital signals in the time domain at the overlap ratio; and determining the frame header position of each group of de-overlapped digital signals based on the second sequence to realize real-time frame synchronization and obtain the recovered passive optical network signal.

The application provides a field bus remote diagnosis method and related device, and belongs to the technical field of industrial communication network diagnosis.The application solves the problems that the traditional field bus diagnosis system is difficult to realize real-time monitoring of remote equipment and remote communication is susceptible to electromagnetic interference, resulting in low data transmission reliability.The device comprises an optical communication unit, a data processing unit and a diagnosis analysis unit;the optical communication unit performs photoelectric conversion on the received optical signal and outputs a clock synchronization electrical signal;the data processing unit decodes and protocol analyzes the field bus sending data;the diagnosis analysis unit extracts the slave station response delay time, frame error rate, signal amplitude attenuation coefficient and bus load rate based on the analyzed data, and identifies faults accordingly.The application adopts optical communication transmission and adaptive clock recovery technology, realizes high-reliability remote real-time monitoring and intelligent fault diagnosis against strong electromagnetic interference within a range of 10 kilometers, and can be widely applied to large industrial fields such as thermal power generation and petrochemical industry.

A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors a logic value “1” or “0” a master latch, during time period B, recovering at least a portion of energy comprising the input with a first clock, during a time period C, moving the input in the master latch to an isolation stage, during time period D, recovering at least a portion of energy comprising the input from the isolation stage with a second clock, during time period E, recovering at least a portion of energy comprising the input from a follower latch with a third clock, and during time period F, moving at least a portion of the input from the isolation stage to the follower latch.

The invention belongs to the technical field of optical fiber communication, and discloses an optical fiber transmission link quality monitoring and dispersion compensation optimization method and system, and the method comprises the steps: extracting an error vector amplitude, an optical signal-to-noise ratio and a constellation diagram distortion feature from a coherent receiver, and fusing the features into a comprehensive quality evaluation index; according to the method, residual dispersion is jointly estimated by using clock recovery phase and equalizer coefficient distribution, parameters of a dispersion compensation filter are adaptively optimized by adopting variable step gradient descent, and performance degradation trend analysis and early warning and multi-wavelength channel joint monitoring and collaborative optimization are carried out.

The invention discloses a jitter decomposition method based on a multi-Dirac model, and the method comprises the steps: collecting a discretized original signal through a data collection system, and carrying out the clock recovery of the original signal, and obtaining a reference clock signal; the method comprises the following steps: performing edge detection on an original signal and a reference clock signal to obtain hopping moments of the original signal and the reference clock signal, and further calculating a time interval error sequence as a data sample of subsequent jitter decomposition; then constructing a multi-Dirac model, solving parameters of the TJ model by using a maximum likelihood estimation method, finally constructing a bathtub curve under the known parameters of the TJ model, and calculating a jitter decomposition result according to the bathtub curve, thereby improving the characterization precision of the DJ model and improving the jitter decomposition precision.